multiply.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4
   5 library work;
   6 use work.common.all;
   7
   8 entity multiply is
   9     generic (
  10         PIPELINE_DEPTH : natural := 4
  11         );
  12     port (
  13         clk   : in std_logic;
  14
  15         m_in  : in MultiplyInputType;
  16         m_out : out MultiplyOutputType
  17         );
  18 end entity multiply;
  19
  20 architecture behaviour of multiply is
  21     signal m: MultiplyInputType := MultiplyInputInit;
  22
  23     type multiply_pipeline_stage is record
  24         valid     : std_ulogic;
  25         data      : unsigned(127 downto 0);
  26         is_32bit  : std_ulogic;
  27         not_res   : std_ulogic;
  28     end record;
  29     constant MultiplyPipelineStageInit : multiply_pipeline_stage := (valid => '0',
  30                                                                      is_32bit => '0', not_res => '0',
  31                                                                      data => (others => '0'));
  32
  33     type multiply_pipeline_type is array(0 to PIPELINE_DEPTH-1) of multiply_pipeline_stage;
  34     constant MultiplyPipelineInit : multiply_pipeline_type := (others => MultiplyPipelineStageInit);
  35
  36     type reg_type is record
  37         multiply_pipeline : multiply_pipeline_type;
  38     end record;
  39
  40     signal r, rin : reg_type := (multiply_pipeline => MultiplyPipelineInit);
  41     signal overflow : std_ulogic;
  42     signal ovf_in   : std_ulogic;
  43 begin
  44     multiply_0: process(clk)
  45     begin
  46         if rising_edge(clk) then
  47             m <= m_in;
  48             r <= rin;
  49             overflow <= ovf_in;
  50         end if;
  51     end process;
  52
  53     multiply_1: process(all)
  54         variable v : reg_type;
  55         variable d : std_ulogic_vector(127 downto 0);
  56         variable d2 : std_ulogic_vector(63 downto 0);
  57         variable ov : std_ulogic;
  58     begin
  59         v := r;
  60         v.multiply_pipeline(0).valid := m.valid;
  61         v.multiply_pipeline(0).data := (unsigned(m.data1) * unsigned(m.data2)) + unsigned(m.addend);
  62         v.multiply_pipeline(0).is_32bit := m.is_32bit;
  63         v.multiply_pipeline(0).not_res := m.not_result;
  64
  65         loop_0: for i in 1 to PIPELINE_DEPTH-1 loop
  66             v.multiply_pipeline(i) := r.multiply_pipeline(i-1);
  67         end loop;
  68
  69         d := std_ulogic_vector(v.multiply_pipeline(PIPELINE_DEPTH-1).data);
  70         if v.multiply_pipeline(PIPELINE_DEPTH-1).not_res = '1' then
  71             d := not d;
  72         end if;
  73
  74         ov := '0';
  75         if v.multiply_pipeline(PIPELINE_DEPTH-1).is_32bit = '1' then
  76             ov := (or d(63 downto 31)) and not (and d(63 downto 31));
  77         else
  78             ov := (or d(127 downto 63)) and not (and d(127 downto 63));
  79         end if;
  80         ovf_in <= ov;
  81
  82         m_out.result <= d;
  83         m_out.overflow <= overflow;
  84         m_out.valid <= v.multiply_pipeline(PIPELINE_DEPTH-1).valid;
  85
  86         rin <= v;
  87     end process;
  88 end architecture behaviour;