nonrandom.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4
   5 library work;
   6
   7 entity random is
   8     port (
   9         clk  : in std_ulogic;
  10         data : out std_ulogic_vector(63 downto 0);
  11         raw  : out std_ulogic_vector(63 downto 0);
  12         err  : out std_ulogic
  13         );
  14 end entity random;
  15
  16 architecture behaviour of random is
  17
  18 begin
  19     data <= (others => '1');
  20     raw <= (others => '1');
  21     err <= '1';
  22 end behaviour;