plru_tb.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3
   4 library work;
   5 use work.common.all;
   6 use work.wishbone_types.all;
   7
   8 entity plru_tb is
   9 end plru_tb;
  10
  11 architecture behave of plru_tb is
  12     signal clk          : std_ulogic;
  13     signal rst          : std_ulogic;
  14
  15     constant clk_period : time := 10 ns;
  16
  17     signal acc_en : std_ulogic;
  18     signal acc : std_ulogic_vector(2 downto 0);
  19     signal lru : std_ulogic_vector(2 downto 0);
  20
  21 begin
  22     plru0: entity work.plru
  23         generic map(
  24             BITS => 3
  25             )
  26         port map(
  27             clk => clk,
  28             rst => rst,
  29
  30             acc => acc,
  31             acc_en => acc_en,
  32             lru => lru
  33             );
  34
  35     clk_process: process
  36     begin
  37         clk <= '0';
  38         wait for clk_period/2;
  39         clk <= '1';
  40         wait for clk_period/2;
  41     end process;
  42
  43     rst_process: process
  44     begin
  45         rst <= '1';
  46         wait for 2*clk_period;
  47         rst <= '0';
  48         wait;
  49     end process;
  50
  51     stim: process
  52     begin
  53         wait for 4*clk_period;
  54
  55         report "accessing 1:";
  56         acc <= "001";
  57         acc_en <= '1';
  58         wait for clk_period;
  59         report "lru:" & to_hstring(lru);
  60
  61         report "accessing 2:";
  62         acc <= "010";
  63         wait for clk_period;
  64         report "lru:" & to_hstring(lru);
  65
  66         report "accessing 7:";
  67         acc <= "111";
  68         wait for clk_period;
  69         report "lru:" & to_hstring(lru);
  70
  71         report "accessing 4:";
  72         acc <= "100";
  73         wait for clk_period;
  74         report "lru:" & to_hstring(lru);
  75
  76         report "accessing 3:";
  77         acc <= "011";
  78         wait for clk_period;
  79         report "lru:" & to_hstring(lru);
  80
  81         report "accessing 5:";
  82         acc <= "101";
  83         wait for clk_period;
  84         report "lru:" & to_hstring(lru);
  85
  86         report "accessing 3:";
  87         acc <= "011";
  88         wait for clk_period;
  89         report "lru:" & to_hstring(lru);
  90
  91         report "accessing 5:";
  92         acc <= "101";
  93         wait for clk_period;
  94         report "lru:" & to_hstring(lru);
  95
  96         report "accessing 6:";
  97         acc <= "110";
  98         wait for clk_period;
  99         report "lru:" & to_hstring(lru);
 100
 101         report "accessing 0:";
 102         acc <= "000";
 103         wait for clk_period;
 104         report "lru:" & to_hstring(lru);
 105
 106         std.env.finish;
 107     end process;
 108 end;