random.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4
   5 library work;
   6 use work.glibc_random.all;
   7
   8 entity random is
   9     port (
  10         clk  : in std_ulogic;
  11         data : out std_ulogic_vector(63 downto 0);
  12         raw  : out std_ulogic_vector(63 downto 0);
  13         err  : out std_ulogic
  14         );
  15 end entity random;
  16
  17 architecture behaviour of random is
  18 begin
  19     err <= '0';
  20
  21     process(clk)
  22         variable rand : std_ulogic_vector(63 downto 0);
  23     begin
  24         if rising_edge(clk) then
  25             rand := pseudorand(64);
  26             data <= rand;
  27             raw <= rand;
  28         end if;
  29     end process;
  30 end behaviour;