rotator_tb.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4
   5 library work;
   6 use work.common.all;
   7 use work.glibc_random.all;
   8 use work.ppc_fx_insns.all;
   9 use work.insn_helpers.all;
  10
  11 entity rotator_tb is
  12 end rotator_tb;
  13
  14 architecture behave of rotator_tb is
  15     constant clk_period: time := 10 ns;
  16     signal ra, rs: std_ulogic_vector(63 downto 0);
  17     signal shift: std_ulogic_vector(6 downto 0) := (others => '0');
  18     signal insn: std_ulogic_vector(31 downto 0) := (others => '0');
  19     signal is_32bit, right_shift, arith, clear_left, clear_right: std_ulogic := '0';
  20     signal result: std_ulogic_vector(63 downto 0);
  21     signal carry_out: std_ulogic;
  22     signal extsw: std_ulogic;
  23
  24 begin
  25     rotator_0: entity work.rotator
  26         port map (
  27             rs => rs,
  28             ra => ra,
  29             shift => shift,
  30             insn => insn,
  31             is_32bit => is_32bit,
  32             right_shift => right_shift,
  33             arith => arith,
  34             clear_left => clear_left,
  35             clear_right => clear_right,
  36             sign_ext_rs => extsw,
  37             result => result,
  38             carry_out => carry_out
  39         );
  40
  41     stim_process: process
  42         variable behave_ra: std_ulogic_vector(63 downto 0);
  43         variable behave_ca_ra: std_ulogic_vector(64 downto 0);
  44     begin
  45         -- rlwinm, rlwnm
  46         report "test rlw[i]nm";
  47         ra <= (others => '0');
  48         is_32bit <= '1';
  49         right_shift <= '0';
  50         arith <= '0';
  51         clear_left <= '1';
  52         clear_right <= '1';
  53         extsw <= '0';
  54         rlwnm_loop : for i in 0 to 1000 loop
  55             rs <= pseudorand(64);
  56             shift <= pseudorand(7);
  57             insn <= x"00000" & '0' & pseudorand(10) & '0';
  58             wait for clk_period;
  59             behave_ra := ppc_rlwinm(rs, shift(4 downto 0), insn_mb32(insn), insn_me32(insn));
  60             assert behave_ra = result
  61                 report "bad rlwnm expected " & to_hstring(behave_ra) & " got " & to_hstring(result);
  62         end loop;
  63
  64         -- rlwimi
  65         report "test rlwimi";
  66         is_32bit <= '1';
  67         right_shift <= '0';
  68         arith <= '0';
  69         clear_left <= '1';
  70         clear_right <= '1';
  71         rlwimi_loop : for i in 0 to 1000 loop
  72             rs <= pseudorand(64);
  73             ra <= pseudorand(64);
  74             shift <= "00" & pseudorand(5);
  75             insn <= x"00000" & '0' & pseudorand(10) & '0';
  76             wait for clk_period;
  77             behave_ra := ppc_rlwimi(ra, rs, shift(4 downto 0), insn_mb32(insn), insn_me32(insn));
  78             assert behave_ra = result
  79                 report "bad rlwimi expected " & to_hstring(behave_ra) & " got " & to_hstring(result);
  80         end loop;
  81
  82         -- rldicl, rldcl
  83         report "test rld[i]cl";
  84         ra <= (others => '0');
  85         is_32bit <= '0';
  86         right_shift <= '0';
  87         arith <= '0';
  88         clear_left <= '1';
  89         clear_right <= '0';
  90         rldicl_loop : for i in 0 to 1000 loop
  91             rs <= pseudorand(64);
  92             shift <= pseudorand(7);
  93             insn <= x"00000" & '0' & pseudorand(10) & '0';
  94             wait for clk_period;
  95             behave_ra := ppc_rldicl(rs, shift(5 downto 0), insn_mb(insn));
  96             assert behave_ra = result
  97                 report "bad rldicl expected " & to_hstring(behave_ra) & " got " & to_hstring(result);
  98         end loop;
  99
 100         -- rldicr, rldcr
 101         report "test rld[i]cr";
 102         ra <= (others => '0');
 103         is_32bit <= '0';
 104         right_shift <= '0';
 105         arith <= '0';
 106         clear_left <= '0';
 107         clear_right <= '1';
 108         rldicr_loop : for i in 0 to 1000 loop
 109             rs <= pseudorand(64);
 110             shift <= pseudorand(7);
 111             insn <= x"00000" & '0' & pseudorand(10) & '0';
 112             wait for clk_period;
 113             behave_ra := ppc_rldicr(rs, shift(5 downto 0), insn_me(insn));
 114             --report "rs = " & to_hstring(rs);
 115             --report "ra = " & to_hstring(ra);
 116             --report "shift = " & to_hstring(shift);
 117             --report "insn me = " & to_hstring(insn_me(insn));
 118             --report "result = " & to_hstring(result);
 119             assert behave_ra = result
 120                 report "bad rldicr expected " & to_hstring(behave_ra) & " got " & to_hstring(result);
 121         end loop;
 122
 123         -- rldic
 124         report "test rldic";
 125         ra <= (others => '0');
 126         is_32bit <= '0';
 127         right_shift <= '0';
 128         arith <= '0';
 129         clear_left <= '1';
 130         clear_right <= '1';
 131         rldic_loop : for i in 0 to 1000 loop
 132             rs <= pseudorand(64);
 133             shift <= '0' & pseudorand(6);
 134             insn <= x"00000" & '0' & pseudorand(10) & '0';
 135             wait for clk_period;
 136             behave_ra := ppc_rldic(rs, shift(5 downto 0), insn_mb(insn));
 137             assert behave_ra = result
 138                 report "bad rldic expected " & to_hstring(behave_ra) & " got " & to_hstring(result);
 139         end loop;
 140
 141         -- rldimi
 142         report "test rldimi";
 143         is_32bit <= '0';
 144         right_shift <= '0';
 145         arith <= '0';
 146         clear_left <= '1';
 147         clear_right <= '1';
 148         rldimi_loop : for i in 0 to 1000 loop
 149             rs <= pseudorand(64);
 150             ra <= pseudorand(64);
 151             shift <= '0' & pseudorand(6);
 152             insn <= x"00000" & '0' & pseudorand(10) & '0';
 153             wait for clk_period;
 154             behave_ra := ppc_rldimi(ra, rs, shift(5 downto 0), insn_mb(insn));
 155             assert behave_ra = result
 156                 report "bad rldimi expected " & to_hstring(behave_ra) & " got " & to_hstring(result);
 157         end loop;
 158
 159         -- slw
 160         report "test slw";
 161         ra <= (others => '0');
 162         is_32bit <= '1';
 163         right_shift <= '0';
 164         arith <= '0';
 165         clear_left <= '0';
 166         clear_right <= '0';
 167         slw_loop : for i in 0 to 1000 loop
 168             rs <= pseudorand(64);
 169             shift <= pseudorand(7);
 170             wait for clk_period;
 171             behave_ra := ppc_slw(rs, std_ulogic_vector(resize(unsigned(shift), 64)));
 172             assert behave_ra = result
 173                 report "bad slw expected " & to_hstring(behave_ra) & " got " & to_hstring(result);
 174         end loop;
 175
 176         -- sld
 177         report "test sld";
 178         ra <= (others => '0');
 179         is_32bit <= '0';
 180         right_shift <= '0';
 181         arith <= '0';
 182         clear_left <= '0';
 183         clear_right <= '0';
 184         sld_loop : for i in 0 to 1000 loop
 185             rs <= pseudorand(64);
 186             shift <= pseudorand(7);
 187             wait for clk_period;
 188             behave_ra := ppc_sld(rs, std_ulogic_vector(resize(unsigned(shift), 64)));
 189             assert behave_ra = result
 190                 report "bad sld expected " & to_hstring(behave_ra) & " got " & to_hstring(result);
 191         end loop;
 192
 193         -- srw
 194         report "test srw";
 195         ra <= (others => '0');
 196         is_32bit <= '1';
 197         right_shift <= '1';
 198         arith <= '0';
 199         clear_left <= '0';
 200         clear_right <= '0';
 201         srw_loop : for i in 0 to 1000 loop
 202             rs <= pseudorand(64);
 203             shift <= pseudorand(7);
 204             wait for clk_period;
 205             behave_ra := ppc_srw(rs, std_ulogic_vector(resize(unsigned(shift), 64)));
 206             assert behave_ra = result
 207                 report "bad srw expected " & to_hstring(behave_ra) & " got " & to_hstring(result);
 208         end loop;
 209
 210         -- srd
 211         report "test srd";
 212         ra <= (others => '0');
 213         is_32bit <= '0';
 214         right_shift <= '1';
 215         arith <= '0';
 216         clear_left <= '0';
 217         clear_right <= '0';
 218         srd_loop : for i in 0 to 1000 loop
 219             rs <= pseudorand(64);
 220             shift <= pseudorand(7);
 221             wait for clk_period;
 222             behave_ra := ppc_srd(rs, std_ulogic_vector(resize(unsigned(shift), 64)));
 223             assert behave_ra = result
 224                 report "bad srd expected " & to_hstring(behave_ra) & " got " & to_hstring(result);
 225         end loop;
 226
 227         -- sraw[i]
 228         report "test sraw[i]";
 229         ra <= (others => '0');
 230         is_32bit <= '1';
 231         right_shift <= '1';
 232         arith <= '1';
 233         clear_left <= '0';
 234         clear_right <= '0';
 235         sraw_loop : for i in 0 to 1000 loop
 236             rs <= pseudorand(64);
 237             shift <= '0' & pseudorand(6);
 238             wait for clk_period;
 239             behave_ca_ra := ppc_sraw(rs, std_ulogic_vector(resize(unsigned(shift), 64)));
 240             --report "rs = " & to_hstring(rs);
 241             --report "ra = " & to_hstring(ra);
 242             --report "shift = " & to_hstring(shift);
 243             --report "result = " & to_hstring(carry_out & result);
 244             assert behave_ca_ra(63 downto 0) = result and behave_ca_ra(64) = carry_out
 245                 report "bad sraw expected " & to_hstring(behave_ca_ra) & " got " & to_hstring(carry_out & result);
 246         end loop;
 247
 248         -- srad[i]
 249         report "test srad[i]";
 250         ra <= (others => '0');
 251         is_32bit <= '0';
 252         right_shift <= '1';
 253         arith <= '1';
 254         clear_left <= '0';
 255         clear_right <= '0';
 256         srad_loop : for i in 0 to 1000 loop
 257             rs <= pseudorand(64);
 258             shift <= pseudorand(7);
 259             wait for clk_period;
 260             behave_ca_ra := ppc_srad(rs, std_ulogic_vector(resize(unsigned(shift), 64)));
 261             --report "rs = " & to_hstring(rs);
 262             --report "ra = " & to_hstring(ra);
 263             --report "shift = " & to_hstring(shift);
 264             --report "result = " & to_hstring(carry_out & result);
 265             assert behave_ca_ra(63 downto 0) = result and behave_ca_ra(64) = carry_out
 266                 report "bad srad expected " & to_hstring(behave_ca_ra) & " got " & to_hstring(carry_out & result);
 267         end loop;
 268
 269         -- extswsli
 270         report "test extswsli";
 271         ra <= (others => '0');
 272         is_32bit <= '0';
 273         right_shift <= '0';
 274         arith <= '0';
 275         clear_left <= '0';
 276         clear_right <= '0';
 277         extsw <= '1';
 278         extswsli_loop : for i in 0 to 1000 loop
 279             rs <= pseudorand(64);
 280             shift <= '0' & pseudorand(6);
 281             wait for clk_period;
 282             behave_ra := rs;
 283             behave_ra(63 downto 32) := (others => rs(31));
 284             behave_ra := std_ulogic_vector(shift_left(unsigned(behave_ra),
 285                                                       to_integer(unsigned(shift))));
 286             --report "rs = " & to_hstring(rs);
 287             --report "ra = " & to_hstring(ra);
 288             --report "shift = " & to_hstring(shift);
 289             --report "result = " & to_hstring(carry_out & result);
 290             assert behave_ra = result
 291                 report "bad extswsli expected " & to_hstring(behave_ra) & " got " & to_hstring(result);
 292         end loop;
 293
 294         std.env.finish;
 295     end process;
 296 end behave;