sim_no_flash.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3
   4 entity s25fl128s is
   5     generic (
   6         LongTimming       : boolean := true;
   7         TimingModel       : string := "";
   8         tdevice_PU        : time := 10 ns;
   9         tdevice_PP256     : time := 10 ns;
  10         tdevice_PP512     : time := 10 ns;
  11         tdevice_WRR       : time := 10 ns;
  12         UserPreload       : boolean := false
  13     );
  14     PORT (
  15         SI                : inout std_ulogic := 'Z';
  16         SO                : inout std_ulogic := 'Z';
  17         SCK               : in    std_ulogic := 'Z';
  18         CSNeg             : in    std_ulogic := 'Z';
  19         RSTNeg            : in    std_ulogic := 'Z';
  20         WPNeg             : inout std_ulogic := 'Z';
  21         HOLDNeg           : inout std_ulogic := 'Z'
  22     );
  23 end entity;
  24
  25 architecture behaviour of s25fl128s is
  26 begin
  27     SO <= '1';
  28 end architecture;