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Add Tercel PHY reset synchronization
[microwatt.git] / soc.vhdl
1 library ieee;
2 use ieee.std_logic_1164.all;
3 use ieee.numeric_std.all;
4 use ieee.math_real.all;
5 use std.textio.all;
6 use std.env.stop;
7
8 library work;
9 use work.common.all;
10 use work.wishbone_types.all;
11
12
13 -- Memory map. *** Keep include/microwatt_soc.h updated on changes ***
14 --
15 -- Main bus:
16 -- 0x00000000: Block RAM (MEMORY_SIZE) or DRAM depending on syscon
17 -- 0x40000000: DRAM (when present)
18 -- 0x80000000: Block RAM (aliased & repeated)
19
20 -- IO Bus:
21 -- 0xc0000000: SYSCON
22 -- 0xc0002000: UART0
23 -- 0xc0003000: UART1 (if any)
24 -- 0xc0004000: XICS ICP
25 -- 0xc0005000: XICS ICS
26 -- 0xc0006000: SPI Flash controller
27 -- 0xc8nnnnnn: External IO bus
28 -- 0xf0000000: Flash "ROM" mapping
29 -- 0xff000000: DRAM init code (if any) or flash ROM (**)
30
31 -- External IO bus:
32 -- 0xc8000000: LiteDRAM control (CSRs)
33 -- 0xc8020000: LiteEth CSRs (*)
34 -- 0xc8030000: LiteEth MMIO (*)
35
36 -- (*) LiteEth must be a single aligned 32KB block as the CSRs and MMIOs
37 -- are actually decoded as a single wishbone which LiteEth will
38 -- internally split based on bit 16.
39
40 -- (**) DRAM init code is currently special and goes to the external
41 -- IO bus, this will be fixed when it's moved out of litedram and
42 -- into the main SoC once we have a common "firmware".
43
44 -- Interrupt numbers:
45 --
46 -- 0 : UART0
47 -- 1 : Ethernet
48
49 entity soc is
50 generic (
51 MEMORY_SIZE : natural;
52 RAM_INIT_FILE : string;
53 CLK_FREQ : positive;
54 SIM : boolean;
55 HAS_FPU : boolean := true;
56 HAS_BTC : boolean := true;
57 DISABLE_FLATTEN_CORE : boolean := false;
58 HAS_DRAM : boolean := false;
59 DRAM_SIZE : integer := 0;
60 DRAM_INIT_SIZE : integer := 0;
61 HAS_SPI_FLASH : boolean := false;
62 SPI_FLASH_DLINES : positive := 1;
63 SPI_FLASH_OFFSET : integer := 0;
64 SPI_FLASH_DEF_CKDV : natural := 2;
65 SPI_FLASH_DEF_QUAD : boolean := false;
66 SPI_BOOT_CLOCKS : boolean := true;
67 LOG_LENGTH : natural := 512;
68 HAS_LITEETH : boolean := false;
69 HAS_TERCEL : boolean := false;
70 HAS_LPC_SLAVE : boolean := false;
71 UART0_IS_16550 : boolean := true;
72 HAS_UART1 : boolean := false;
73 ICACHE_NUM_LINES : natural := 64;
74 ICACHE_NUM_WAYS : natural := 2;
75 ICACHE_TLB_SIZE : natural := 64;
76 DCACHE_NUM_LINES : natural := 64;
77 DCACHE_NUM_WAYS : natural := 2;
78 DCACHE_TLB_SET_SIZE : natural := 64;
79 DCACHE_TLB_NUM_WAYS : natural := 2
80 );
81 port(
82 rst : in std_ulogic;
83 system_clk : in std_ulogic;
84
85 -- "Large" (64-bit) DRAM wishbone
86 wb_dram_in : out wishbone_master_out;
87 wb_dram_out : in wishbone_slave_out := wishbone_slave_out_init;
88
89 -- "Small" (32-bit) external IO wishbone
90 wb_ext_io_in : out wb_io_master_out;
91 wb_ext_io_out : in wb_io_slave_out := wb_io_slave_out_init;
92 wb_ext_is_dram_csr : out std_ulogic;
93 wb_ext_is_dram_init : out std_ulogic;
94 wb_ext_is_eth : out std_ulogic;
95 wb_ext_is_tercel : out std_ulogic;
96 wb_ext_is_lpc_slave : out std_ulogic;
97
98 -- External interrupts
99 ext_irq_eth : in std_ulogic := '0';
100
101 -- UART0 signals:
102 uart0_txd : out std_ulogic;
103 uart0_rxd : in std_ulogic := '0';
104
105 -- UART1 signals:
106 uart1_txd : out std_ulogic;
107 uart1_rxd : in std_ulogic := '0';
108
109 -- SPI Flash controller signals:
110 wb_spiflash_in : out wb_io_master_out;
111 wb_spiflash_out : in wb_io_slave_out := wb_io_slave_out_init;
112
113 -- LPC slave DMA signals
114 wb_lpc_slave_in : out wishbone_slave_out;
115 wb_lpc_slave_out : in wishbone_master_out;
116
117 -- DRAM controller signals
118 alt_reset : in std_ulogic := '0'
119 );
120 end entity soc;
121
122 architecture behaviour of soc is
123
124 -- Wishbone master signals:
125 signal wishbone_dcore_in : wishbone_slave_out;
126 signal wishbone_dcore_out : wishbone_master_out;
127 signal wishbone_icore_in : wishbone_slave_out;
128 signal wishbone_icore_out : wishbone_master_out;
129 signal wishbone_debug_in : wishbone_slave_out;
130 signal wishbone_debug_out : wishbone_master_out;
131 signal wishbone_lpc_in : wishbone_slave_out;
132 signal wishbone_lpc_out : wishbone_master_out;
133
134 -- Arbiter array (ghdl doesnt' support assigning the array
135 -- elements in the entity instantiation)
136 constant NUM_WB_MASTERS : positive := 4;
137 signal wb_masters_out : wishbone_master_out_vector(0 to NUM_WB_MASTERS-1);
138 signal wb_masters_in : wishbone_slave_out_vector(0 to NUM_WB_MASTERS-1);
139
140 -- Wishbone master (output of arbiter):
141 signal wb_master_in : wishbone_slave_out;
142 signal wb_master_out : wishbone_master_out;
143
144 -- Main "IO" bus, from main slave decoder to the latch
145 signal wb_io_in : wishbone_master_out;
146 signal wb_io_out : wishbone_slave_out;
147
148 -- Secondary (smaller) IO bus after the IO bus latch
149 signal wb_sio_out : wb_io_master_out;
150 signal wb_sio_in : wb_io_slave_out;
151
152 -- Syscon signals
153 signal dram_at_0 : std_ulogic;
154 signal do_core_reset : std_ulogic;
155 signal wb_syscon_in : wb_io_master_out;
156 signal wb_syscon_out : wb_io_slave_out;
157
158 -- UART0 signals:
159 signal wb_uart0_in : wb_io_master_out;
160 signal wb_uart0_out : wb_io_slave_out;
161 signal uart0_dat8 : std_ulogic_vector(7 downto 0);
162 signal uart0_irq : std_ulogic;
163
164 -- UART1 signals:
165 signal wb_uart1_in : wb_io_master_out;
166 signal wb_uart1_out : wb_io_slave_out;
167 signal uart1_dat8 : std_ulogic_vector(7 downto 0);
168 signal uart1_irq : std_ulogic;
169
170 -- XICS signals:
171 signal wb_xics_icp_in : wb_io_master_out;
172 signal wb_xics_icp_out : wb_io_slave_out;
173 signal wb_xics_ics_in : wb_io_master_out;
174 signal wb_xics_ics_out : wb_io_slave_out;
175 signal int_level_in : std_ulogic_vector(15 downto 0);
176 signal ics_to_icp : ics_to_icp_t;
177 signal core_ext_irq : std_ulogic;
178
179 -- Main memory signals:
180 signal wb_bram_in : wishbone_master_out;
181 signal wb_bram_out : wishbone_slave_out;
182
183 -- DMI debug bus signals
184 signal dmi_addr : std_ulogic_vector(7 downto 0);
185 signal dmi_din : std_ulogic_vector(63 downto 0);
186 signal dmi_dout : std_ulogic_vector(63 downto 0);
187 signal dmi_req : std_ulogic;
188 signal dmi_wr : std_ulogic;
189 signal dmi_ack : std_ulogic;
190
191 -- Per slave DMI signals
192 signal dmi_wb_dout : std_ulogic_vector(63 downto 0);
193 signal dmi_wb_req : std_ulogic;
194 signal dmi_wb_ack : std_ulogic;
195 signal dmi_core_dout : std_ulogic_vector(63 downto 0);
196 signal dmi_core_req : std_ulogic;
197 signal dmi_core_ack : std_ulogic;
198
199 -- Delayed/latched resets and alt_reset
200 signal rst_core : std_ulogic := '1';
201 signal rst_uart : std_ulogic := '1';
202 signal rst_xics : std_ulogic := '1';
203 signal rst_spi : std_ulogic := '1';
204 signal rst_bram : std_ulogic := '1';
205 signal rst_dtm : std_ulogic := '1';
206 signal rst_wbar : std_ulogic := '1';
207 signal rst_wbdb : std_ulogic := '1';
208 signal alt_reset_d : std_ulogic;
209
210 -- IO branch split:
211 type slave_io_type is (SLAVE_IO_SYSCON,
212 SLAVE_IO_UART,
213 SLAVE_IO_ICP,
214 SLAVE_IO_ICS,
215 SLAVE_IO_UART1,
216 SLAVE_IO_SPI_FLASH_MAP,
217 SLAVE_IO_EXTERNAL,
218 SLAVE_IO_NONE);
219 signal slave_io_dbg : slave_io_type;
220
221 -- This is the component exported by the 16550 compatible
222 -- UART from FuseSoC.
223 --
224 component uart_top port (
225 wb_clk_i : in std_ulogic;
226 wb_rst_i : in std_ulogic;
227 wb_adr_i : in std_ulogic_vector(2 downto 0);
228 wb_dat_i : in std_ulogic_vector(7 downto 0);
229 wb_dat_o : out std_ulogic_vector(7 downto 0);
230 wb_we_i : in std_ulogic;
231 wb_stb_i : in std_ulogic;
232 wb_cyc_i : in std_ulogic;
233 wb_ack_o : out std_ulogic;
234 int_o : out std_ulogic;
235 stx_pad_o : out std_ulogic;
236 srx_pad_i : in std_ulogic;
237 rts_pad_o : out std_ulogic;
238 cts_pad_i : in std_ulogic;
239 dtr_pad_o : out std_ulogic;
240 dsr_pad_i : in std_ulogic;
241 ri_pad_i : in std_ulogic;
242 dcd_pad_i : in std_ulogic
243 );
244 end component;
245 begin
246
247 resets: process(system_clk)
248 begin
249 if rising_edge(system_clk) then
250 rst_core <= rst or do_core_reset;
251 rst_uart <= rst;
252 rst_spi <= rst;
253 rst_xics <= rst;
254 rst_bram <= rst;
255 rst_dtm <= rst;
256 rst_wbar <= rst;
257 rst_wbdb <= rst;
258 alt_reset_d <= alt_reset;
259 end if;
260 end process;
261
262 -- Processor core
263 processor: entity work.core
264 generic map(
265 SIM => SIM,
266 HAS_FPU => HAS_FPU,
267 HAS_BTC => HAS_BTC,
268 DISABLE_FLATTEN => DISABLE_FLATTEN_CORE,
269 ALT_RESET_ADDRESS => (23 downto 0 => '0', others => '1'),
270 LOG_LENGTH => LOG_LENGTH,
271 ICACHE_NUM_LINES => ICACHE_NUM_LINES,
272 ICACHE_NUM_WAYS => ICACHE_NUM_WAYS,
273 ICACHE_TLB_SIZE => ICACHE_TLB_SIZE,
274 DCACHE_NUM_LINES => DCACHE_NUM_LINES,
275 DCACHE_NUM_WAYS => DCACHE_NUM_WAYS,
276 DCACHE_TLB_SET_SIZE => DCACHE_TLB_SET_SIZE,
277 DCACHE_TLB_NUM_WAYS => DCACHE_TLB_NUM_WAYS
278 )
279 port map(
280 clk => system_clk,
281 rst => rst_core,
282 alt_reset => alt_reset_d,
283 wishbone_insn_in => wishbone_icore_in,
284 wishbone_insn_out => wishbone_icore_out,
285 wishbone_data_in => wishbone_dcore_in,
286 wishbone_data_out => wishbone_dcore_out,
287 dmi_addr => dmi_addr(3 downto 0),
288 dmi_dout => dmi_core_dout,
289 dmi_din => dmi_dout,
290 dmi_wr => dmi_wr,
291 dmi_ack => dmi_core_ack,
292 dmi_req => dmi_core_req,
293 ext_irq => core_ext_irq
294 );
295
296 -- Wishbone bus master arbiter & mux
297 wb_masters_out <= (0 => wishbone_dcore_out,
298 1 => wishbone_icore_out,
299 2 => wishbone_debug_out,
300 3 => wishbone_lpc_out);
301 wishbone_dcore_in <= wb_masters_in(0);
302 wishbone_icore_in <= wb_masters_in(1);
303 wishbone_debug_in <= wb_masters_in(2);
304 wishbone_lpc_in <= wb_masters_in(3);
305 wishbone_arbiter_0: entity work.wishbone_arbiter
306 generic map(
307 NUM_MASTERS => NUM_WB_MASTERS
308 )
309 port map(
310 clk => system_clk,
311 rst => rst_wbar,
312 wb_masters_in => wb_masters_out,
313 wb_masters_out => wb_masters_in,
314 wb_slave_out => wb_master_out,
315 wb_slave_in => wb_master_in
316 );
317
318 -- Top level Wishbone slaves address decoder & mux
319 --
320 -- From CPU to BRAM, DRAM, IO, selected on top 3 bits and dram_at_0
321 -- 0000 - BRAM
322 -- 0001 - DRAM
323 -- 01xx - DRAM
324 -- 10xx - BRAM
325 -- 11xx - IO
326 --
327 slave_top_intercon: process(wb_master_out, wb_bram_out, wb_dram_out, wb_io_out, dram_at_0)
328 type slave_top_type is (SLAVE_TOP_BRAM,
329 SLAVE_TOP_DRAM,
330 SLAVE_TOP_IO);
331 variable slave_top : slave_top_type;
332 variable top_decode : std_ulogic_vector(3 downto 0);
333 begin
334 -- Top-level address decoder
335 top_decode := wb_master_out.adr(31 downto 29) & dram_at_0;
336 slave_top := SLAVE_TOP_BRAM;
337 if std_match(top_decode, "0000") then
338 slave_top := SLAVE_TOP_BRAM;
339 elsif std_match(top_decode, "0001") then
340 slave_top := SLAVE_TOP_DRAM;
341 elsif std_match(top_decode, "01--") then
342 slave_top := SLAVE_TOP_DRAM;
343 elsif std_match(top_decode, "10--") then
344 slave_top := SLAVE_TOP_BRAM;
345 elsif std_match(top_decode, "11--") then
346 slave_top := SLAVE_TOP_IO;
347 end if;
348
349 -- Top level wishbone muxing.
350 wb_bram_in <= wb_master_out;
351 wb_bram_in.cyc <= '0';
352 wb_dram_in <= wb_master_out;
353 wb_dram_in.cyc <= '0';
354 wb_io_in <= wb_master_out;
355 wb_io_in.cyc <= '0';
356 case slave_top is
357 when SLAVE_TOP_BRAM =>
358 wb_bram_in.cyc <= wb_master_out.cyc;
359 wb_master_in <= wb_bram_out;
360 when SLAVE_TOP_DRAM =>
361 if HAS_DRAM then
362 wb_dram_in.cyc <= wb_master_out.cyc;
363 wb_master_in <= wb_dram_out;
364 else
365 wb_master_in.ack <= wb_master_out.cyc and wb_master_out.stb;
366 wb_master_in.dat <= (others => '1');
367 wb_master_in.stall <= '0';
368 end if;
369 when SLAVE_TOP_IO =>
370 wb_io_in.cyc <= wb_master_out.cyc;
371 wb_master_in <= wb_io_out;
372 end case;
373
374 end process slave_top_intercon;
375
376 -- IO wishbone slave 64->32 bits converter
377 --
378 -- For timing reasons, this adds a one cycle latch on the way both
379 -- in and out. This relaxes timing and routing pressure on the "main"
380 -- memory bus by moving all simple IOs to a slower 32-bit bus.
381 --
382 -- This implementation is rather dumb at the moment, no stash buffer,
383 -- so we stall whenever that latch is busy. This can be improved.
384 --
385 slave_io_latch: process(system_clk)
386 -- State
387 type state_t is (IDLE, WAIT_ACK_BOT, WAIT_ACK_TOP);
388 variable state : state_t;
389
390 -- Misc
391 variable has_top : boolean;
392 variable has_bot : boolean;
393 begin
394 if rising_edge(system_clk) then
395 if (rst) then
396 state := IDLE;
397 wb_io_out.ack <= '0';
398 wb_io_out.stall <= '0';
399 wb_sio_out.cyc <= '0';
400 wb_sio_out.stb <= '0';
401 has_top := false;
402 has_bot := false;
403 else
404 case state is
405 when IDLE =>
406 -- Clear ACK in case it was set
407 wb_io_out.ack <= '0';
408
409 -- Do we have a cycle ?
410 if wb_io_in.cyc = '1' and wb_io_in.stb = '1' then
411 -- Stall master until we are done, we are't (yet) pipelining
412 -- this, it's all slow IOs.
413 wb_io_out.stall <= '1';
414
415 -- Start cycle downstream
416 wb_sio_out.cyc <= '1';
417 wb_sio_out.stb <= '1';
418
419 -- Copy write enable to IO out, copy address as well
420 wb_sio_out.we <= wb_io_in.we;
421 wb_sio_out.adr <= wb_io_in.adr(wb_sio_out.adr'left downto 3) & "000";
422
423 -- Do we have a top word and/or a bottom word ?
424 has_top := wb_io_in.sel(7 downto 4) /= "0000";
425 has_bot := wb_io_in.sel(3 downto 0) /= "0000";
426
427 -- If we have a bottom word, handle it first, otherwise
428 -- send the top word down. XXX Split the actual mux out
429 -- and only generate a control signal.
430 if has_bot then
431 if wb_io_in.we = '1' then
432 wb_sio_out.dat <= wb_io_in.dat(31 downto 0);
433 end if;
434 wb_sio_out.sel <= wb_io_in.sel(3 downto 0);
435
436 -- Wait for ack
437 state := WAIT_ACK_BOT;
438 else
439 if wb_io_in.we = '1' then
440 wb_sio_out.dat <= wb_io_in.dat(63 downto 32);
441 end if;
442 wb_sio_out.sel <= wb_io_in.sel(7 downto 4);
443
444 -- Bump address
445 wb_sio_out.adr(2) <= '1';
446
447 -- Wait for ack
448 state := WAIT_ACK_TOP;
449 end if;
450 end if;
451 when WAIT_ACK_BOT =>
452 -- If we aren't stalled by the device, clear stb
453 if wb_sio_in.stall = '0' then
454 wb_sio_out.stb <= '0';
455 end if;
456
457 -- Handle ack
458 if wb_sio_in.ack = '1' then
459 -- If it's a read, latch the data
460 if wb_sio_out.we = '0' then
461 wb_io_out.dat(31 downto 0) <= wb_sio_in.dat;
462 end if;
463
464 -- Do we have a "top" part as well ?
465 if has_top then
466 -- Latch data & sel
467 if wb_io_in.we = '1' then
468 wb_sio_out.dat <= wb_io_in.dat(63 downto 32);
469 end if;
470 wb_sio_out.sel <= wb_io_in.sel(7 downto 4);
471
472 -- Bump address and set STB
473 wb_sio_out.adr(2) <= '1';
474 wb_sio_out.stb <= '1';
475
476 -- Wait for new ack
477 state := WAIT_ACK_TOP;
478 else
479 -- We are done, ack up, clear cyc downstram
480 wb_sio_out.cyc <= '0';
481
482 -- And ack & unstall upstream
483 wb_io_out.ack <= '1';
484 wb_io_out.stall <= '0';
485
486 -- Wait for next one
487 state := IDLE;
488 end if;
489 end if;
490 when WAIT_ACK_TOP =>
491 -- If we aren't stalled by the device, clear stb
492 if wb_sio_in.stall = '0' then
493 wb_sio_out.stb <= '0';
494 end if;
495
496 -- Handle ack
497 if wb_sio_in.ack = '1' then
498 -- If it's a read, latch the data
499 if wb_sio_out.we = '0' then
500 wb_io_out.dat(63 downto 32) <= wb_sio_in.dat;
501 end if;
502
503 -- We are done, ack up, clear cyc downstram
504 wb_sio_out.cyc <= '0';
505
506 -- And ack & unstall upstream
507 wb_io_out.ack <= '1';
508 wb_io_out.stall <= '0';
509
510 -- Wait for next one
511 state := IDLE;
512 end if;
513 end case;
514 end if;
515 end if;
516 end process;
517
518 -- IO wishbone slave intercon.
519 --
520 slave_io_intercon: process(wb_sio_out, wb_syscon_out, wb_uart0_out, wb_uart1_out,
521 wb_ext_io_out, wb_xics_icp_out, wb_xics_ics_out,
522 wb_spiflash_out)
523 variable slave_io : slave_io_type;
524
525 variable match : std_ulogic_vector(31 downto 12);
526 variable ext_valid : boolean;
527 begin
528
529 -- Simple address decoder.
530 slave_io := SLAVE_IO_NONE;
531 match := "11" & wb_sio_out.adr(29 downto 12);
532 if std_match(match, x"FF---") and HAS_DRAM then
533 slave_io := SLAVE_IO_EXTERNAL;
534 elsif std_match(match, x"F----") then
535 slave_io := SLAVE_IO_SPI_FLASH_MAP;
536 elsif std_match(match, x"C0000") then
537 slave_io := SLAVE_IO_SYSCON;
538 elsif std_match(match, x"C0002") then
539 slave_io := SLAVE_IO_UART;
540 elsif std_match(match, x"C0003") then
541 slave_io := SLAVE_IO_UART1;
542 elsif std_match(match, x"C8---") then
543 slave_io := SLAVE_IO_EXTERNAL;
544 elsif std_match(match, x"C0004") then
545 slave_io := SLAVE_IO_ICP;
546 elsif std_match(match, x"C0005") then
547 slave_io := SLAVE_IO_ICS;
548 end if;
549 slave_io_dbg <= slave_io;
550 wb_uart0_in <= wb_sio_out;
551 wb_uart0_in.cyc <= '0';
552 wb_uart1_in <= wb_sio_out;
553 wb_uart1_in.cyc <= '0';
554 wb_spiflash_in <= wb_sio_out;
555 wb_spiflash_in.cyc <= '0';
556
557 -- Only give xics 8 bits of wb addr (for now...)
558 wb_xics_icp_in <= wb_sio_out;
559 wb_xics_icp_in.adr <= (others => '0');
560 wb_xics_icp_in.adr(7 downto 0) <= wb_sio_out.adr(7 downto 0);
561 wb_xics_icp_in.cyc <= '0';
562 wb_xics_ics_in <= wb_sio_out;
563 wb_xics_ics_in.adr <= (others => '0');
564 wb_xics_ics_in.adr(11 downto 0) <= wb_sio_out.adr(11 downto 0);
565 wb_xics_ics_in.cyc <= '0';
566
567 wb_ext_io_in <= wb_sio_out;
568 wb_ext_io_in.cyc <= '0';
569
570 wb_syscon_in <= wb_sio_out;
571 wb_syscon_in.cyc <= '0';
572
573 wb_ext_is_dram_csr <= '0';
574 wb_ext_is_dram_init <= '0';
575 wb_ext_is_eth <= '0';
576
577 -- Default response, ack & return all 1's
578 wb_sio_in.dat <= (others => '1');
579 wb_sio_in.ack <= wb_sio_out.stb and wb_sio_out.cyc;
580 wb_sio_in.stall <= '0';
581
582 case slave_io is
583 when SLAVE_IO_EXTERNAL =>
584 -- Ext IO "chip selects"
585 --
586 -- DRAM init is special at 0xFF* so we just test the top
587 -- bit. Everything else is at 0xC8* so we test only bits
588 -- 23 downto 16.
589 --
590 ext_valid := false;
591 if wb_sio_out.adr(29) = '1' and HAS_DRAM then -- DRAM init is special
592 wb_ext_is_dram_init <= '1';
593 ext_valid := true;
594 elsif wb_sio_out.adr(23 downto 16) = x"00" and HAS_DRAM then
595 wb_ext_is_dram_csr <= '1';
596 ext_valid := true;
597 elsif wb_sio_out.adr(23 downto 16) = x"02" and HAS_LITEETH then
598 wb_ext_is_eth <= '1';
599 ext_valid := true;
600 elsif wb_sio_out.adr(23 downto 16) = x"03" and HAS_LITEETH then
601 wb_ext_is_eth <= '1';
602 ext_valid := true;
603 elsif wb_sio_out.adr(21 downto 14) = x"04" and HAS_LPC_SLAVE then
604 wb_ext_is_lpc_slave <= '1';
605 ext_valid := true;
606 elsif wb_sio_out.adr(21 downto 14) = x"05" and HAS_TERCEL then
607 wb_ext_is_tercel <= '1';
608 ext_valid := true;
609 end if;
610 if ext_valid then
611 wb_ext_io_in.cyc <= wb_sio_out.cyc;
612 wb_sio_in <= wb_ext_io_out;
613 end if;
614
615 when SLAVE_IO_SYSCON =>
616 wb_syscon_in.cyc <= wb_sio_out.cyc;
617 wb_sio_in <= wb_syscon_out;
618 when SLAVE_IO_UART =>
619 wb_uart0_in.cyc <= wb_sio_out.cyc;
620 wb_sio_in <= wb_uart0_out;
621 when SLAVE_IO_ICP =>
622 wb_xics_icp_in.cyc <= wb_sio_out.cyc;
623 wb_sio_in <= wb_xics_icp_out;
624 when SLAVE_IO_ICS =>
625 wb_xics_ics_in.cyc <= wb_sio_out.cyc;
626 wb_sio_in <= wb_xics_ics_out;
627 when SLAVE_IO_UART1 =>
628 wb_uart1_in.cyc <= wb_sio_out.cyc;
629 wb_sio_in <= wb_uart1_out;
630 when SLAVE_IO_SPI_FLASH_MAP =>
631 -- Clear top bits so they don't make their way to the
632 -- fash chip.
633 wb_spiflash_in.adr(29 downto 28) <= "00";
634 wb_spiflash_in.cyc <= wb_sio_out.cyc;
635 wb_sio_in <= wb_spiflash_out;
636 when others =>
637 end case;
638
639 end process;
640
641 -- Syscon slave
642 syscon0: entity work.syscon
643 generic map(
644 HAS_UART => true,
645 HAS_DRAM => HAS_DRAM,
646 BRAM_SIZE => MEMORY_SIZE,
647 DRAM_SIZE => DRAM_SIZE,
648 DRAM_INIT_SIZE => DRAM_INIT_SIZE,
649 CLK_FREQ => CLK_FREQ,
650 HAS_SPI_FLASH => HAS_SPI_FLASH,
651 SPI_FLASH_OFFSET => SPI_FLASH_OFFSET,
652 HAS_LITEETH => HAS_LITEETH,
653 UART0_IS_16550 => UART0_IS_16550,
654 HAS_UART1 => HAS_UART1
655 )
656 port map(
657 clk => system_clk,
658 rst => rst,
659 wishbone_in => wb_syscon_in,
660 wishbone_out => wb_syscon_out,
661 dram_at_0 => dram_at_0,
662 core_reset => do_core_reset,
663 soc_reset => open -- XXX TODO
664 );
665
666 --
667 -- UART0
668 --
669 -- Either potato (legacy) or 16550
670 --
671 uart0_pp: if not UART0_IS_16550 generate
672 uart0: entity work.pp_soc_uart
673 generic map(
674 FIFO_DEPTH => 32
675 )
676 port map(
677 clk => system_clk,
678 reset => rst_uart,
679 txd => uart0_txd,
680 rxd => uart0_rxd,
681 irq => uart0_irq,
682 wb_adr_in => wb_uart0_in.adr(11 downto 0),
683 wb_dat_in => wb_uart0_in.dat(7 downto 0),
684 wb_dat_out => uart0_dat8,
685 wb_cyc_in => wb_uart0_in.cyc,
686 wb_stb_in => wb_uart0_in.stb,
687 wb_we_in => wb_uart0_in.we,
688 wb_ack_out => wb_uart0_out.ack
689 );
690 end generate;
691
692 uart0_16550 : if UART0_IS_16550 generate
693 signal irq_l : std_ulogic;
694 begin
695 uart0: uart_top
696 port map (
697 wb_clk_i => system_clk,
698 wb_rst_i => rst_uart,
699 wb_adr_i => wb_uart0_in.adr(4 downto 2),
700 wb_dat_i => wb_uart0_in.dat(7 downto 0),
701 wb_dat_o => uart0_dat8,
702 wb_we_i => wb_uart0_in.we,
703 wb_stb_i => wb_uart0_in.stb,
704 wb_cyc_i => wb_uart0_in.cyc,
705 wb_ack_o => wb_uart0_out.ack,
706 int_o => irq_l,
707 stx_pad_o => uart0_txd,
708 srx_pad_i => uart0_rxd,
709 rts_pad_o => open,
710 cts_pad_i => '1',
711 dtr_pad_o => open,
712 dsr_pad_i => '1',
713 ri_pad_i => '0',
714 dcd_pad_i => '1'
715 );
716
717 -- Add a register on the irq out, helps timing
718 uart0_irq_latch: process(system_clk)
719 begin
720 if rising_edge(system_clk) then
721 uart0_irq <= irq_l;
722 end if;
723 end process;
724 end generate;
725
726 wb_uart0_out.dat <= x"000000" & uart0_dat8;
727 wb_uart0_out.stall <= not wb_uart0_out.ack;
728
729 --
730 -- UART1
731 --
732 -- Always 16550 if it exists
733 --
734 uart1: if HAS_UART1 generate
735 signal irq_l : std_ulogic;
736 begin
737 uart1: uart_top
738 port map (
739 wb_clk_i => system_clk,
740 wb_rst_i => rst_uart,
741 wb_adr_i => wb_uart1_in.adr(4 downto 2),
742 wb_dat_i => wb_uart1_in.dat(7 downto 0),
743 wb_dat_o => uart1_dat8,
744 wb_we_i => wb_uart1_in.we,
745 wb_stb_i => wb_uart1_in.stb,
746 wb_cyc_i => wb_uart1_in.cyc,
747 wb_ack_o => wb_uart1_out.ack,
748 int_o => irq_l,
749 stx_pad_o => uart1_txd,
750 srx_pad_i => uart1_rxd,
751 rts_pad_o => open,
752 cts_pad_i => '1',
753 dtr_pad_o => open,
754 dsr_pad_i => '1',
755 ri_pad_i => '0',
756 dcd_pad_i => '1'
757 );
758 -- Add a register on the irq out, helps timing
759 uart0_irq_latch: process(system_clk)
760 begin
761 if rising_edge(system_clk) then
762 uart1_irq <= irq_l;
763 end if;
764 end process;
765 wb_uart1_out.dat <= x"000000" & uart1_dat8;
766 wb_uart1_out.stall <= not wb_uart1_out.ack;
767 end generate;
768
769 no_uart1 : if not HAS_UART1 generate
770 wb_uart1_out.dat <= x"00000000";
771 wb_uart1_out.ack <= wb_uart1_in.cyc and wb_uart1_in.stb;
772 wb_uart1_out.stall <= '0';
773 uart1_irq <= '0';
774 end generate;
775
776 xics_icp: entity work.xics_icp
777 port map(
778 clk => system_clk,
779 rst => rst_xics,
780 wb_in => wb_xics_icp_in,
781 wb_out => wb_xics_icp_out,
782 ics_in => ics_to_icp,
783 core_irq_out => core_ext_irq
784 );
785
786 xics_ics: entity work.xics_ics
787 generic map(
788 SRC_NUM => 16,
789 PRIO_BITS => 3
790 )
791 port map(
792 clk => system_clk,
793 rst => rst_xics,
794 wb_in => wb_xics_ics_in,
795 wb_out => wb_xics_ics_out,
796 int_level_in => int_level_in,
797 icp_out => ics_to_icp
798 );
799
800 -- Assign external interrupts
801 interrupts: process(all)
802 begin
803 int_level_in <= (others => '0');
804 int_level_in(0) <= uart0_irq;
805 int_level_in(1) <= ext_irq_eth;
806 int_level_in(2) <= uart1_irq;
807 end process;
808
809 -- BRAM Memory slave
810 bram: if MEMORY_SIZE /= 0 generate
811 bram0: entity work.wishbone_bram_wrapper
812 generic map(
813 MEMORY_SIZE => MEMORY_SIZE,
814 RAM_INIT_FILE => RAM_INIT_FILE
815 )
816 port map(
817 clk => system_clk,
818 rst => rst_bram,
819 wishbone_in => wb_bram_in,
820 wishbone_out => wb_bram_out
821 );
822 end generate;
823
824 no_bram: if MEMORY_SIZE = 0 generate
825 wb_bram_out.ack <= wb_bram_in.cyc and wb_bram_in.stb;
826 wb_bram_out.dat <= x"FFFFFFFFFFFFFFFF";
827 wb_bram_out.stall <= not wb_bram_out.ack;
828 end generate;
829
830 -- DMI(debug bus) <-> JTAG bridge
831 dtm: entity work.dmi_dtm
832 generic map(
833 ABITS => 8,
834 DBITS => 64
835 )
836 port map(
837 sys_clk => system_clk,
838 sys_reset => rst_dtm,
839 dmi_addr => dmi_addr,
840 dmi_din => dmi_din,
841 dmi_dout => dmi_dout,
842 dmi_req => dmi_req,
843 dmi_wr => dmi_wr,
844 dmi_ack => dmi_ack
845 );
846
847 -- DMI interconnect
848 dmi_intercon: process(dmi_addr, dmi_req,
849 dmi_wb_ack, dmi_wb_dout,
850 dmi_core_ack, dmi_core_dout)
851
852 -- DMI address map (each address is a full 64-bit register)
853 --
854 -- Offset: Size: Slave:
855 -- 0 4 Wishbone
856 -- 10 16 Core
857
858 type slave_type is (SLAVE_WB,
859 SLAVE_CORE,
860 SLAVE_NONE);
861 variable slave : slave_type;
862 begin
863 -- Simple address decoder
864 slave := SLAVE_NONE;
865 if std_match(dmi_addr, "000000--") then
866 slave := SLAVE_WB;
867 elsif std_match(dmi_addr, "0001----") then
868 slave := SLAVE_CORE;
869 end if;
870
871 -- DMI muxing
872 dmi_wb_req <= '0';
873 dmi_core_req <= '0';
874 case slave is
875 when SLAVE_WB =>
876 dmi_wb_req <= dmi_req;
877 dmi_ack <= dmi_wb_ack;
878 dmi_din <= dmi_wb_dout;
879 when SLAVE_CORE =>
880 dmi_core_req <= dmi_req;
881 dmi_ack <= dmi_core_ack;
882 dmi_din <= dmi_core_dout;
883 when others =>
884 dmi_ack <= dmi_req;
885 dmi_din <= (others => '1');
886 end case;
887
888 -- SIM magic exit
889 if SIM and dmi_req = '1' and dmi_addr = "11111111" and dmi_wr = '1' then
890 stop;
891 end if;
892 end process;
893
894 -- Wishbone debug master (TODO: Add a DMI address decoder)
895 wishbone_debug: entity work.wishbone_debug_master
896 port map(clk => system_clk,
897 rst => rst_wbdb,
898 dmi_addr => dmi_addr(1 downto 0),
899 dmi_dout => dmi_wb_dout,
900 dmi_din => dmi_dout,
901 dmi_wr => dmi_wr,
902 dmi_ack => dmi_wb_ack,
903 dmi_req => dmi_wb_req,
904 wb_in => wishbone_debug_in,
905 wb_out => wishbone_debug_out);
906
907 --pragma synthesis_off
908 wb_x_state: process(system_clk)
909 begin
910 if rising_edge(system_clk) then
911 if not rst then
912 -- Wishbone arbiter
913 assert not(is_x(wb_masters_out(0).cyc)) and not(is_x(wb_masters_out(0).stb)) severity failure;
914 assert not(is_x(wb_masters_out(1).cyc)) and not(is_x(wb_masters_out(1).stb)) severity failure;
915 assert not(is_x(wb_masters_out(2).cyc)) and not(is_x(wb_masters_out(2).stb)) severity failure;
916 assert not(is_x(wb_masters_out(3).cyc)) and not(is_x(wb_masters_out(3).stb)) severity failure;
917 assert not(is_x(wb_masters_in(0).ack)) severity failure;
918 assert not(is_x(wb_masters_in(1).ack)) severity failure;
919 assert not(is_x(wb_masters_in(2).ack)) severity failure;
920 assert not(is_x(wb_masters_in(3).ack)) severity failure;
921
922 -- Main memory wishbones
923 assert not(is_x(wb_bram_in.cyc)) and not (is_x(wb_bram_in.stb)) severity failure;
924 assert not(is_x(wb_dram_in.cyc)) and not (is_x(wb_dram_in.stb)) severity failure;
925 assert not(is_x(wb_io_in.cyc)) and not (is_x(wb_io_in.stb)) severity failure;
926 assert not(is_x(wb_bram_out.ack)) severity failure;
927 assert not(is_x(wb_dram_out.ack)) severity failure;
928 assert not(is_x(wb_io_out.ack)) severity failure;
929
930 -- I/O wishbones
931 assert not(is_x(wb_uart0_in.cyc)) and not(is_x(wb_uart0_in.stb)) severity failure;
932 assert not(is_x(wb_uart1_in.cyc)) and not(is_x(wb_uart1_in.stb)) severity failure;
933 assert not(is_x(wb_spiflash_in.cyc)) and not(is_x(wb_spiflash_in.stb)) severity failure;
934 assert not(is_x(wb_xics_icp_in.cyc)) and not(is_x(wb_xics_icp_in.stb)) severity failure;
935 assert not(is_x(wb_xics_ics_in.cyc)) and not(is_x(wb_xics_ics_in.stb)) severity failure;
936 assert not(is_x(wb_ext_io_in.cyc)) and not(is_x(wb_ext_io_in.stb)) severity failure;
937 assert not(is_x(wb_syscon_in.cyc)) and not(is_x(wb_syscon_in.stb)) severity failure;
938 assert not(is_x(wb_uart0_out.ack)) severity failure;
939 assert not(is_x(wb_uart1_out.ack)) severity failure;
940 assert not(is_x(wb_spiflash_out.ack)) severity failure;
941 assert not(is_x(wb_xics_icp_out.ack)) severity failure;
942 assert not(is_x(wb_xics_ics_out.ack)) severity failure;
943 assert not(is_x(wb_ext_io_out.ack)) severity failure;
944 assert not(is_x(wb_syscon_out.ack)) severity failure;
945 end if;
946 end if;
947 end process;
948 --pragma synthesis_on
949
950 -- LPC slave DMA
951 wb_lpc_slave_in <= wishbone_lpc_in;
952 wishbone_lpc_out <= wb_lpc_slave_out;
953
954 end architecture behaviour;