wishbone_bram_tb.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4
   5 library work;
   6 use work.wishbone_types.all;
   7
   8 entity wishbone_bram_tb is
   9 end wishbone_bram_tb;
  10
  11 architecture behave of wishbone_bram_tb is
  12     signal clk          : std_ulogic;
  13     signal rst          : std_ulogic := '1';
  14
  15     constant clk_period : time := 10 ns;
  16
  17     signal w_in         : wishbone_slave_out;
  18     signal w_out        : wishbone_master_out;
  19
  20     impure function to_adr(a: integer) return std_ulogic_vector is
  21     begin
  22         return std_ulogic_vector(to_unsigned(a, w_out.adr'length));
  23     end;
  24 begin
  25     simple_ram_0: entity work.wishbone_bram_wrapper
  26         generic map (
  27             RAM_INIT_FILE => "wishbone_bram_tb.bin",
  28             MEMORY_SIZE => 16
  29             )
  30         port map (
  31             clk => clk,
  32             rst => rst,
  33             wishbone_out => w_in,
  34             wishbone_in => w_out
  35             );
  36
  37     clock: process
  38     begin
  39         clk <= '1';
  40         wait for clk_period / 2;
  41         clk <= '0';
  42         wait for clk_period / 2;
  43     end process clock;
  44
  45     stim: process
  46     begin
  47         w_out.adr <= (others => '0');
  48         w_out.dat <= (others => '0');
  49         w_out.cyc <= '0';
  50         w_out.stb <= '0';
  51         w_out.sel <= (others => '0');
  52         w_out.we  <= '0';
  53
  54         wait until rising_edge(clk);
  55         rst <= '0';
  56         wait until rising_edge(clk);
  57
  58         w_out.cyc <= '1';
  59
  60         -- Test read 0
  61         w_out.stb <= '1';
  62         w_out.sel <= "11111111";
  63         w_out.adr <= to_adr(0);
  64         assert w_in.ack = '0';
  65         wait until rising_edge(clk);
  66         w_out.stb <= '0';
  67         wait until rising_edge(clk);
  68         wait until rising_edge(clk);
  69         assert w_in.ack = '1';
  70         assert w_in.dat(63 downto 0) = x"0706050403020100" report to_hstring(w_in.dat);
  71         wait until rising_edge(clk);
  72         assert w_in.ack = '0';
  73
  74         -- Test read 8
  75         w_out.stb <= '1';
  76         w_out.sel <= "11111111";
  77         w_out.adr <= to_adr(8);
  78         assert w_in.ack = '0';
  79         wait until rising_edge(clk);
  80         w_out.stb <= '0';
  81         wait until rising_edge(clk);
  82         wait until rising_edge(clk);
  83         assert w_in.ack = '1';
  84         assert w_in.dat(63 downto 0) = x"0F0E0D0C0B0A0908" report to_hstring(w_in.dat);
  85         wait until rising_edge(clk);
  86         assert w_in.ack = '0';
  87
  88         -- Test write byte at 0
  89         w_out.stb <= '1';
  90         w_out.sel <= "00000001";
  91         w_out.adr <= to_adr(0);
  92         w_out.we <= '1';
  93         w_out.dat(7 downto 0) <= x"0F";
  94         assert w_in.ack = '0';
  95         wait until rising_edge(clk);
  96         w_out.stb <= '0';
  97         wait until rising_edge(clk) and w_in.ack = '1';
  98         wait until rising_edge(clk);
  99         assert w_in.ack = '0';
 100
 101         -- Test read back
 102         w_out.stb <= '1';
 103         w_out.sel <= "11111111";
 104         w_out.adr <= to_adr(0);
 105         w_out.we <= '0';
 106         assert w_in.ack = '0';
 107         wait until rising_edge(clk);
 108         w_out.stb <= '0';
 109         wait until rising_edge(clk);
 110         wait until rising_edge(clk);
 111         assert w_in.ack = '1';
 112         assert w_in.dat(63 downto 0) = x"070605040302010F" report to_hstring(w_in.dat);
 113         wait until rising_edge(clk);
 114         assert w_in.ack = '0';
 115
 116         -- Test write dword at 4
 117         w_out.stb <= '1';
 118         w_out.sel <= "11110000";
 119         w_out.adr <= to_adr(0);
 120         w_out.we <= '1';
 121         w_out.dat(63 downto 32) <= x"BAADFEED";
 122         assert w_in.ack = '0';
 123         wait until rising_edge(clk);
 124         w_out.stb <= '0';
 125         wait until rising_edge(clk) and w_in.ack = '1';
 126         wait until rising_edge(clk);
 127         assert w_in.ack = '0';
 128
 129         -- Test read back
 130         w_out.stb <= '1';
 131         w_out.sel <= "11111111";
 132         w_out.adr <= to_adr(0);
 133         w_out.we <= '0';
 134         assert w_in.ack = '0';
 135         wait until rising_edge(clk);
 136         w_out.stb <= '0';
 137         wait until rising_edge(clk);
 138         wait until rising_edge(clk);
 139         assert w_in.ack = '1';
 140         assert w_in.dat(63 downto 0) = x"BAADFEED0302010F" report to_hstring(w_in.dat);
 141         wait until rising_edge(clk);
 142         assert w_in.ack = '0';
 143
 144         -- Test write qword at 8
 145         w_out.stb <= '1';
 146         w_out.sel <= "11111111";
 147         w_out.adr <= to_adr(8);
 148         w_out.we <= '1';
 149         w_out.dat(63 downto 0) <= x"0001020304050607";
 150         assert w_in.ack = '0';
 151         wait until rising_edge(clk);
 152         w_out.stb <= '0';
 153         wait until rising_edge(clk) and w_in.ack = '1';
 154         wait until rising_edge(clk);
 155         assert w_in.ack = '0';
 156
 157         -- Test read back
 158         w_out.stb <= '1';
 159         w_out.sel <= "11111111";
 160         w_out.adr <= to_adr(8);
 161         w_out.we <= '0';
 162         assert w_in.ack = '0';
 163         wait until rising_edge(clk);
 164         w_out.stb <= '0';
 165         wait until rising_edge(clk);
 166         wait until rising_edge(clk);
 167         assert w_in.ack = '1';
 168         assert w_in.dat(63 downto 0) = x"0001020304050607" report to_hstring(w_in.dat);
 169         wait until rising_edge(clk);
 170         assert w_in.ack = '0';
 171
 172         std.env.finish;
 173     end process;
 174 end behave;