wishbone_bram_wrapper.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4 use std.textio.all;
   5
   6 library work;
   7 use work.utils.all;
   8 use work.wishbone_types.all;
   9
  10 --! @brief Simple memory module for use in Wishbone-based systems.
  11 entity wishbone_bram_wrapper is
  12     generic(
  13         MEMORY_SIZE   : natural := 4096; --! Memory size in bytes.
  14         RAM_INIT_FILE : string
  15         );
  16     port(
  17         clk : in std_logic;
  18         rst : in std_logic;
  19
  20         -- Wishbone interface:
  21         wishbone_in  : in wishbone_master_out;
  22         wishbone_out : out wishbone_slave_out
  23         );
  24 end entity wishbone_bram_wrapper;
  25
  26 architecture behaviour of wishbone_bram_wrapper is
  27     constant ram_addr_bits : integer := log2ceil(MEMORY_SIZE) - 3;
  28
  29     -- RAM interface
  30     signal ram_addr : std_logic_vector(ram_addr_bits - 1 downto 0);
  31     signal ram_we   : std_ulogic;
  32     signal ram_re   : std_ulogic;
  33
  34     -- Others
  35     signal ack, ack_buf : std_ulogic;
  36 begin
  37
  38     -- Actual RAM template
  39     ram_0: entity work.main_bram
  40         generic map(
  41             WIDTH => 64,
  42             HEIGHT_BITS => ram_addr_bits,
  43             MEMORY_SIZE => MEMORY_SIZE,
  44             RAM_INIT_FILE => RAM_INIT_FILE
  45             )
  46         port map(
  47             clk => clk,
  48             addr => ram_addr,
  49             di => wishbone_in.dat,
  50             do => wishbone_out.dat,
  51             sel => wishbone_in.sel,
  52             re => ram_re,
  53             we => ram_we
  54             );
  55
  56     -- Wishbone interface
  57     ram_addr <= wishbone_in.adr(ram_addr_bits + 2 downto 3);
  58     ram_we <= wishbone_in.stb and wishbone_in.cyc and wishbone_in.we;
  59     ram_re <= wishbone_in.stb and wishbone_in.cyc and not wishbone_in.we;
  60     wishbone_out.stall <= '0';
  61     wishbone_out.ack <= ack_buf;
  62
  63     wb_0: process(clk)
  64     begin
  65         if rising_edge(clk) then
  66             if rst = '1' or wishbone_in.cyc = '0' then
  67                 ack_buf <= '0';
  68                 ack <= '0';
  69             else
  70                 -- On loads, we have a delay cycle due to BRAM bufferring
  71                 -- but not on stores. So try to send an early ack on a
  72                 -- store if we aren't behind an existing load ack.
  73                 --
  74                 if ram_we = '1' and ack = '0' then
  75                     ack_buf <= '1';
  76                 else
  77                     ack <= wishbone_in.stb;
  78                     ack_buf <= ack;
  79                 end if;
  80             end if;
  81         end if;
  82     end process;
  83
  84 end architecture behaviour;