wishbone_debug_master.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4
   5 library work;
   6 use work.wishbone_types.all;
   7
   8 entity wishbone_debug_master is
   9     port(clk    : in std_ulogic;
  10          rst    : in std_ulogic;
  11
  12          -- Debug bus interface
  13          dmi_addr       : in std_ulogic_vector(1 downto 0);
  14          dmi_din        : in std_ulogic_vector(63 downto 0);
  15          dmi_dout       : out std_ulogic_vector(63 downto 0);
  16          dmi_req        : in std_ulogic;
  17          dmi_wr         : in std_ulogic;
  18          dmi_ack        : out std_ulogic;
  19
  20          -- Wishbone master interface
  21          wb_out  : out wishbone_master_out;
  22          wb_in   : in wishbone_slave_out
  23          );
  24 end entity wishbone_debug_master;
  25
  26 architecture behaviour of wishbone_debug_master is
  27
  28     -- ** Register offsets definitions. All registers are 64-bit
  29     constant DBG_WB_ADDR        : std_ulogic_vector(1 downto 0) := "00";
  30     constant DBG_WB_DATA        : std_ulogic_vector(1 downto 0) := "01";
  31     constant DBG_WB_CTRL        : std_ulogic_vector(1 downto 0) := "10";
  32     constant DBG_WB_RSVD        : std_ulogic_vector(1 downto 0) := "11";
  33
  34     -- CTRL register:
  35     --
  36     -- bit  0..7 : SEL bits (byte enables)
  37     -- bit     8 : address auto-increment
  38     -- bit 10..9 : auto-increment value:
  39     --                00 - +1
  40     --                01 - +2
  41     --                10 - +4
  42     --                11 - +8
  43
  44     -- ** Address and control registers and read data
  45     signal reg_addr             : std_ulogic_vector(63 downto 0);
  46     signal reg_ctrl_out         : std_ulogic_vector(63 downto 0);
  47     signal reg_ctrl             : std_ulogic_vector(10 downto 0);
  48     signal data_latch           : std_ulogic_vector(63 downto 0);
  49
  50     type state_t is (IDLE, WB_CYCLE, DMI_WAIT);
  51     signal state : state_t;
  52     signal do_inc : std_ulogic;
  53
  54 begin
  55
  56     -- Hard wire unused bits to 0
  57     reg_ctrl_out <= (63 downto 11 => '0',
  58                      10 downto  0 => reg_ctrl);
  59
  60     -- DMI read data mux
  61     with dmi_addr select dmi_dout <=
  62         reg_addr        when DBG_WB_ADDR,
  63         data_latch      when DBG_WB_DATA,
  64         reg_ctrl_out    when DBG_WB_CTRL,
  65         (others => '0') when others;
  66
  67     -- ADDR and CTRL register writes
  68     reg_write : process(clk)
  69         subtype autoinc_inc_t is integer range 1 to 8;
  70         function decode_autoinc(c : std_ulogic_vector(1 downto 0))
  71             return autoinc_inc_t is
  72         begin
  73             case c is
  74             when "00" => return 1;
  75             when "01" => return 2;
  76             when "10" => return 4;
  77             when "11" => return 8;
  78             -- Below shouldn't be necessary but GHDL complains
  79             when others => return 8;
  80             end case;
  81         end function decode_autoinc;
  82     begin
  83         if rising_edge(clk) then
  84             if (rst) then
  85                 reg_addr <= (others => '0');
  86                 reg_ctrl <= (others => '0');
  87             else            -- Standard register writes
  88                 if do_inc = '1' then
  89                     -- Address register auto-increment
  90                     reg_addr <= std_ulogic_vector(unsigned(reg_addr) +
  91                                                   decode_autoinc(reg_ctrl(10 downto 9)));
  92                 elsif dmi_req and dmi_wr then
  93                     if dmi_addr = DBG_WB_ADDR then
  94                         reg_addr <= dmi_din;
  95                     elsif dmi_addr = DBG_WB_CTRL then
  96                         reg_ctrl <= dmi_din(10 downto 0);
  97                     end if;
  98                 end if;
  99             end if;
 100         end if;
 101     end process;
 102
 103     -- ACK is hard wired to req for register writes. For data read/writes
 104     -- (aka commands), it's sent when the state machine got the WB ack.
 105     --
 106     -- Note: We never set it to 1, we just pass dmi_req back when acking.
 107     --       This fullfills two purposes:
 108     --
 109     --        * Avoids polluting the ack signal when another DMI slave is
 110     --          selected. This allows the decoder to just OR all the acks
 111     --          together rather than mux them.
 112     --
 113     --        * Makes ack go down on the same cycle as req goes down, thus
 114     --          saving a clock cycle. This is safe because we know that
 115     --          the state machine will no longer be in DMI_WAIT state on
 116     --          the next cycle, so we won't be bouncing the signal back up.
 117     --
 118     dmi_ack <= dmi_req when (dmi_addr /= DBG_WB_DATA or state = DMI_WAIT) else '0';
 119
 120         -- Some WB signals are direct wires from registers or DMI
 121     wb_out.adr <= reg_addr(wb_out.adr'left downto 0);
 122     wb_out.dat <= dmi_din;
 123     wb_out.sel <= reg_ctrl(7 downto 0);
 124     wb_out.we  <= dmi_wr;
 125
 126     -- We always move WB cyc and stb simultaneously (no pipelining yet...)
 127     wb_out.cyc <= '1' when state = WB_CYCLE else '0';
 128
 129     -- Data latch. WB will take the read data away as soon as the cycle
 130     -- terminates but we must maintain it on DMI until req goes down, so
 131     -- we latch it. (Q: Should we move that latch to dmi_dtm itself ?)
 132     --
 133     latch_reads : process(clk)
 134     begin
 135         if rising_edge(clk) then
 136             if state = WB_CYCLE and wb_in.ack = '1' and dmi_wr = '0' then
 137                 data_latch <= wb_in.dat;
 138             end if;
 139         end if;
 140     end process;
 141
 142     -- Command state machine (generate wb_cyc)
 143     wb_trigger : process(clk)
 144     begin
 145         if rising_edge(clk) then
 146             if (rst) then
 147                 state <= IDLE;
 148                 wb_out.stb <= '0';
 149                 do_inc <= '0';
 150             else
 151                 case state is
 152                 when IDLE =>
 153                     if dmi_req = '1' and dmi_addr = DBG_WB_DATA then
 154                         state <= WB_CYCLE;
 155                         wb_out.stb <= '1';
 156                     end if;
 157                 when WB_CYCLE =>
 158                     if wb_in.stall = '0' then
 159                         wb_out.stb <= '0';
 160                     end if;
 161                     if wb_in.ack then
 162                         -- We shouldn't get the ack if we hadn't already cleared
 163                         -- stb above but if this happen, don't leave it dangling.
 164                         --
 165                         wb_out.stb <= '0';
 166                         state <= DMI_WAIT;
 167                         do_inc <= reg_ctrl(8);
 168                     end if;
 169                 when DMI_WAIT =>
 170                     if dmi_req = '0' then
 171                         state <= IDLE;
 172                     end if;
 173                     do_inc <= '0';
 174                 end case;
 175             end if;
 176         end if;
 177     end process;
 178 end architecture behaviour;