wishbone_types.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3
   4 package wishbone_types is
   5     --
   6     -- Main CPU bus. 32-bit address, 64-bit data
   7     --
   8     constant wishbone_addr_bits : integer := 32;
   9     constant wishbone_data_bits : integer := 64;
  10     constant wishbone_sel_bits : integer := wishbone_data_bits/8;
  11
  12     subtype wishbone_addr_type is std_ulogic_vector(wishbone_addr_bits-1 downto 0);
  13     subtype wishbone_data_type is std_ulogic_vector(wishbone_data_bits-1 downto 0);
  14     subtype wishbone_sel_type  is std_ulogic_vector(wishbone_sel_bits-1  downto 0);
  15
  16     type wishbone_master_out is record
  17         adr : wishbone_addr_type;
  18         dat : wishbone_data_type;
  19         sel : wishbone_sel_type;
  20         cyc : std_ulogic;
  21         stb : std_ulogic;
  22         we  : std_ulogic;
  23     end record;
  24     constant wishbone_master_out_init : wishbone_master_out := (adr => (others => '0'), dat => (others => '0'), cyc => '0', stb => '0', sel => (others => '0'), we => '0');
  25
  26     type wishbone_slave_out is record
  27         dat   : wishbone_data_type;
  28         ack   : std_ulogic;
  29         stall : std_ulogic;
  30     end record;
  31     constant wishbone_slave_out_init : wishbone_slave_out := (ack => '0', stall => '0', others => (others => '0'));
  32
  33     type wishbone_master_out_vector is array (natural range <>) of wishbone_master_out;
  34     type wishbone_slave_out_vector is array (natural range <>) of wishbone_slave_out;
  35
  36     --
  37     -- IO Bus to a device, 30-bit address, 32-bits data
  38     --
  39     type wb_io_master_out is record
  40         adr : std_ulogic_vector(29 downto 0);
  41         dat : std_ulogic_vector(31 downto 0);
  42         sel : std_ulogic_vector(3 downto 0);
  43         cyc : std_ulogic;
  44         stb : std_ulogic;
  45         we  : std_ulogic;
  46     end record;
  47
  48     type wb_io_slave_out is record
  49         dat   : std_ulogic_vector(31 downto 0);
  50         ack   : std_ulogic;
  51         stall : std_ulogic;
  52     end record;
  53     constant wb_io_slave_out_init : wb_io_slave_out := (ack => '0', stall => '0', others => (others => '0'));
  54 end package wishbone_types;