xilinx-mult.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4
   5 library work;
   6 use work.common.all;
   7
   8 library unisim;
   9 use unisim.vcomponents.all;
  10
  11 entity multiply is
  12     port (
  13         clk   : in std_logic;
  14
  15         m_in  : in MultiplyInputType;
  16         m_out : out MultiplyOutputType
  17         );
  18 end entity multiply;
  19
  20 architecture behaviour of multiply is
  21     signal m00_p, m01_p, m02_p, m03_p : std_ulogic_vector(47 downto 0);
  22     signal m00_pc : std_ulogic_vector(47 downto 0);
  23     signal m10_p, m11_p, m12_p, m13_p : std_ulogic_vector(47 downto 0);
  24     signal m11_pc, m12_pc, m13_pc : std_ulogic_vector(47 downto 0);
  25     signal m20_p, m21_p, m22_p, m23_p : std_ulogic_vector(47 downto 0);
  26     signal s0_pc, s1_pc : std_ulogic_vector(47 downto 0);
  27     signal product_lo : std_ulogic_vector(31 downto 0);
  28     signal product : std_ulogic_vector(127 downto 0);
  29     signal addend : std_ulogic_vector(127 downto 0);
  30     signal s0_carry, p0_carry : std_ulogic_vector(3 downto 0);
  31     signal p0_mask : std_ulogic_vector(47 downto 0);
  32     signal p0_pat, p0_patb : std_ulogic;
  33     signal p1_pat, p1_patb : std_ulogic;
  34
  35     signal req_32bit, r32_1 : std_ulogic;
  36     signal req_not, rnot_1 : std_ulogic;
  37     signal valid_1 : std_ulogic;
  38     signal overflow, ovf_in : std_ulogic;
  39
  40 begin
  41     addend <= m_in.addend;
  42
  43     m00: DSP48E1
  44         generic map (
  45             ACASCREG => 0,
  46             ALUMODEREG => 0,
  47             AREG => 0,
  48             BCASCREG => 0,
  49             BREG => 0,
  50             CARRYINREG => 0,
  51             CARRYINSELREG => 0,
  52             INMODEREG => 0,
  53             OPMODEREG => 0,
  54             PREG => 0
  55             )
  56         port map (
  57             A => "0000000" & m_in.data1(22 downto 0),
  58             ACIN => (others => '0'),
  59             ALUMODE => "0000",
  60             B => '0' & m_in.data2(16 downto 0),
  61             BCIN => (others => '0'),
  62             C => "00000000000000" & addend(33 downto 0),
  63             CARRYCASCIN => '0',
  64             CARRYIN => '0',
  65             CARRYINSEL => "000",
  66             CEA1 => '0',
  67             CEA2 => '0',
  68             CEAD => '0',
  69             CEALUMODE => '0',
  70             CEB1 => '0',
  71             CEB2 => '0',
  72             CEC => '1',
  73             CECARRYIN => '0',
  74             CECTRL => '0',
  75             CED => '0',
  76             CEINMODE => '0',
  77             CEM => m_in.valid,
  78             CEP => '0',
  79             CLK => clk,
  80             D => (others => '0'),
  81             INMODE => "00000",
  82             MULTSIGNIN => '0',
  83             OPMODE => "0110101",
  84             P => m00_p,
  85             PCIN => (others => '0'),
  86             PCOUT => m00_pc,
  87             RSTA => '0',
  88             RSTALLCARRYIN => '0',
  89             RSTALUMODE => '0',
  90             RSTB => '0',
  91             RSTC => '0',
  92             RSTCTRL => '0',
  93             RSTD => '0',
  94             RSTINMODE => '0',
  95             RSTM => '0',
  96             RSTP => '0'
  97             );
  98
  99     m01: DSP48E1
 100         generic map (
 101             ACASCREG => 0,
 102             ALUMODEREG => 0,
 103             AREG => 0,
 104             BCASCREG => 0,
 105             BREG => 0,
 106             CARRYINREG => 0,
 107             CARRYINSELREG => 0,
 108             INMODEREG => 0,
 109             OPMODEREG => 0,
 110             PREG => 0
 111             )
 112         port map (
 113             A => "0000000" & m_in.data1(22 downto 0),
 114             ACIN => (others => '0'),
 115             ALUMODE => "0000",
 116             B => '0' & m_in.data2(33 downto 17),
 117             BCIN => (others => '0'),
 118             C => (others => '0'),
 119             CARRYCASCIN => '0',
 120             CARRYIN => '0',
 121             CARRYINSEL => "000",
 122             CEA1 => '0',
 123             CEA2 => '0',
 124             CEAD => '0',
 125             CEALUMODE => '0',
 126             CEB1 => '0',
 127             CEB2 => '0',
 128             CEC => '1',
 129             CECARRYIN => '0',
 130             CECTRL => '0',
 131             CED => '0',
 132             CEINMODE => '0',
 133             CEM => m_in.valid,
 134             CEP => '0',
 135             CLK => clk,
 136             D => (others => '0'),
 137             INMODE => "00000",
 138             MULTSIGNIN => '0',
 139             OPMODE => "1010101",
 140             P => m01_p,
 141             PCIN => m00_pc,
 142             RSTA => '0',
 143             RSTALLCARRYIN => '0',
 144             RSTALUMODE => '0',
 145             RSTB => '0',
 146             RSTC => '0',
 147             RSTCTRL => '0',
 148             RSTD => '0',
 149             RSTINMODE => '0',
 150             RSTM => '0',
 151             RSTP => '0'
 152             );
 153
 154     m02: DSP48E1
 155         generic map (
 156             ACASCREG => 0,
 157             ALUMODEREG => 0,
 158             AREG => 0,
 159             BCASCREG => 0,
 160             BREG => 0,
 161             CARRYINREG => 0,
 162             CARRYINSELREG => 0,
 163             INMODEREG => 0,
 164             OPMODEREG => 0,
 165             PREG => 0
 166             )
 167         port map (
 168             A => "0000000" & m_in.data1(22 downto 0),
 169             ACIN => (others => '0'),
 170             ALUMODE => "0000",
 171             B => '0' & m_in.data2(50 downto 34),
 172             BCIN => (others => '0'),
 173             C => x"0000000" & "000" & addend(50 downto 34),
 174             CARRYCASCIN => '0',
 175             CARRYIN => '0',
 176             CARRYINSEL => "000",
 177             CEA1 => '0',
 178             CEA2 => '0',
 179             CEAD => '0',
 180             CEALUMODE => '0',
 181             CEB1 => '0',
 182             CEB2 => '0',
 183             CEC => '1',
 184             CECARRYIN => '0',
 185             CECTRL => '0',
 186             CED => '0',
 187             CEINMODE => '0',
 188             CEM => m_in.valid,
 189             CEP => '0',
 190             CLK => clk,
 191             D => (others => '0'),
 192             INMODE => "00000",
 193             MULTSIGNIN => '0',
 194             OPMODE => "0110101",
 195             P => m02_p,
 196             PCIN => (others => '0'),
 197             RSTA => '0',
 198             RSTALLCARRYIN => '0',
 199             RSTALUMODE => '0',
 200             RSTB => '0',
 201             RSTC => '0',
 202             RSTCTRL => '0',
 203             RSTD => '0',
 204             RSTINMODE => '0',
 205             RSTM => '0',
 206             RSTP => '0'
 207             );
 208
 209     m03: DSP48E1
 210         generic map (
 211             ACASCREG => 0,
 212             ALUMODEREG => 0,
 213             AREG => 0,
 214             BCASCREG => 0,
 215             BREG => 0,
 216             CARRYINREG => 0,
 217             CARRYINSELREG => 0,
 218             INMODEREG => 0,
 219             OPMODEREG => 0,
 220             PREG => 0
 221             )
 222         port map (
 223             A => "0000000" & m_in.data1(22 downto 0),
 224             ACIN => (others => '0'),
 225             ALUMODE => "0000",
 226             B => "00000" & m_in.data2(63 downto 51),
 227             BCIN => (others => '0'),
 228             C => x"000000" & '0' & addend(73 downto 51),
 229             CARRYCASCIN => '0',
 230             CARRYIN => '0',
 231             CARRYINSEL => "000",
 232             CEA1 => '0',
 233             CEA2 => '0',
 234             CEAD => '0',
 235             CEALUMODE => '0',
 236             CEB1 => '0',
 237             CEB2 => '0',
 238             CEC => '1',
 239             CECARRYIN => '0',
 240             CECTRL => '0',
 241             CED => '0',
 242             CEINMODE => '0',
 243             CEM => m_in.valid,
 244             CEP => '0',
 245             CLK => clk,
 246             D => (others => '0'),
 247             INMODE => "00000",
 248             MULTSIGNIN => '0',
 249             OPMODE => "0110101",
 250             P => m03_p,
 251             PCIN => (others => '0'),
 252             RSTA => '0',
 253             RSTALLCARRYIN => '0',
 254             RSTALUMODE => '0',
 255             RSTB => '0',
 256             RSTC => '0',
 257             RSTCTRL => '0',
 258             RSTD => '0',
 259             RSTINMODE => '0',
 260             RSTM => '0',
 261             RSTP => '0'
 262             );
 263
 264     m10: DSP48E1
 265         generic map (
 266             ACASCREG => 0,
 267             ALUMODEREG => 0,
 268             AREG => 0,
 269             BCASCREG => 0,
 270             BREG => 0,
 271             CARRYINREG => 0,
 272             CARRYINSELREG => 0,
 273             CREG => 0,
 274             INMODEREG => 0,
 275             OPMODEREG => 0,
 276             PREG => 0
 277             )
 278         port map (
 279             A => "0000000000000" & m_in.data1(39 downto 23),
 280             ACIN => (others => '0'),
 281             ALUMODE => "0000",
 282             B => '0' & m_in.data2(16 downto 0),
 283             BCIN => (others => '0'),
 284             C => x"000" & "00" & m01_p(39 downto 6),
 285             CARRYCASCIN => '0',
 286             CARRYIN => '0',
 287             CARRYINSEL => "000",
 288             CEA1 => '0',
 289             CEA2 => '0',
 290             CEAD => '0',
 291             CEALUMODE => '0',
 292             CEB1 => '0',
 293             CEB2 => '0',
 294             CEC => '0',
 295             CECARRYIN => '0',
 296             CECTRL => '0',
 297             CED => '0',
 298             CEINMODE => '0',
 299             CEM => m_in.valid,
 300             CEP => '0',
 301             CLK => clk,
 302             D => (others => '0'),
 303             INMODE => "00000",
 304             MULTSIGNIN => '0',
 305             OPMODE => "0110101",
 306             P => m10_p,
 307             PCIN => (others => '0'),
 308             RSTA => '0',
 309             RSTALLCARRYIN => '0',
 310             RSTALUMODE => '0',
 311             RSTB => '0',
 312             RSTC => '0',
 313             RSTCTRL => '0',
 314             RSTD => '0',
 315             RSTINMODE => '0',
 316             RSTM => '0',
 317             RSTP => '0'
 318             );
 319
 320     m11: DSP48E1
 321         generic map (
 322             ACASCREG => 0,
 323             ALUMODEREG => 0,
 324             AREG => 0,
 325             BCASCREG => 0,
 326             BREG => 0,
 327             CARRYINREG => 0,
 328             CARRYINSELREG => 0,
 329             CREG => 0,
 330             INMODEREG => 0,
 331             OPMODEREG => 0,
 332             PREG => 0
 333             )
 334         port map (
 335             A => "0000000000000" & m_in.data1(39 downto 23),
 336             ACIN => (others => '0'),
 337             ALUMODE => "0000",
 338             B => '0' & m_in.data2(33 downto 17),
 339             BCIN => (others => '0'),
 340             C => x"000" & "00" & m02_p(39 downto 6),
 341             CARRYCASCIN => '0',
 342             CARRYIN => '0',
 343             CARRYINSEL => "000",
 344             CEA1 => '0',
 345             CEA2 => '0',
 346             CEAD => '0',
 347             CEALUMODE => '0',
 348             CEB1 => '0',
 349             CEB2 => '0',
 350             CEC => '0',
 351             CECARRYIN => '0',
 352             CECTRL => '0',
 353             CED => '0',
 354             CEINMODE => '0',
 355             CEM => m_in.valid,
 356             CEP => '0',
 357             CLK => clk,
 358             D => (others => '0'),
 359             INMODE => "00000",
 360             MULTSIGNIN => '0',
 361             OPMODE => "0110101",
 362             P => m11_p,
 363             PCIN => (others => '0'),
 364             PCOUT => m11_pc,
 365             RSTA => '0',
 366             RSTALLCARRYIN => '0',
 367             RSTALUMODE => '0',
 368             RSTB => '0',
 369             RSTC => '0',
 370             RSTCTRL => '0',
 371             RSTD => '0',
 372             RSTINMODE => '0',
 373             RSTM => '0',
 374             RSTP => '0'
 375             );
 376
 377     m12: DSP48E1
 378         generic map (
 379             ACASCREG => 0,
 380             ALUMODEREG => 0,
 381             AREG => 0,
 382             BCASCREG => 0,
 383             BREG => 0,
 384             CARRYINREG => 0,
 385             CARRYINSELREG => 0,
 386             CREG => 0,
 387             INMODEREG => 0,
 388             OPMODEREG => 0,
 389             PREG => 0
 390             )
 391         port map (
 392             A => "0000000000000" & m_in.data1(39 downto 23),
 393             ACIN => (others => '0'),
 394             ALUMODE => "0000",
 395             B => '0' & m_in.data2(50 downto 34),
 396             BCIN => (others => '0'),
 397             C => x"0000" & '0' & m03_p(36 downto 6),
 398             CARRYCASCIN => '0',
 399             CARRYIN => '0',
 400             CARRYINSEL => "000",
 401             CEA1 => '0',
 402             CEA2 => '0',
 403             CEAD => '0',
 404             CEALUMODE => '0',
 405             CEB1 => '0',
 406             CEB2 => '0',
 407             CEC => '0',
 408             CECARRYIN => '0',
 409             CECTRL => '0',
 410             CED => '0',
 411             CEINMODE => '0',
 412             CEM => m_in.valid,
 413             CEP => '0',
 414             CLK => clk,
 415             D => (others => '0'),
 416             INMODE => "00000",
 417             MULTSIGNIN => '0',
 418             OPMODE => "0110101",
 419             P => m12_p,
 420             PCIN => (others => '0'),
 421             PCOUT => m12_pc,
 422             RSTA => '0',
 423             RSTALLCARRYIN => '0',
 424             RSTALUMODE => '0',
 425             RSTB => '0',
 426             RSTC => '0',
 427             RSTCTRL => '0',
 428             RSTD => '0',
 429             RSTINMODE => '0',
 430             RSTM => '0',
 431             RSTP => '0'
 432             );
 433
 434     m13: DSP48E1
 435         generic map (
 436             ACASCREG => 0,
 437             ALUMODEREG => 0,
 438             AREG => 0,
 439             BCASCREG => 0,
 440             BREG => 0,
 441             CARRYINREG => 0,
 442             CARRYINSELREG => 0,
 443             INMODEREG => 0,
 444             OPMODEREG => 0,
 445             PREG => 0
 446             )
 447         port map (
 448             A => "0000000000000" & m_in.data1(39 downto 23),
 449             ACIN => (others => '0'),
 450             ALUMODE => "0000",
 451             B => "00000" & m_in.data2(63 downto 51),
 452             BCIN => (others => '0'),
 453             C => x"0000000" & "000" & addend(90 downto 74),
 454             CARRYCASCIN => '0',
 455             CARRYIN => '0',
 456             CARRYINSEL => "000",
 457             CEA1 => '0',
 458             CEA2 => '0',
 459             CEAD => '0',
 460             CEALUMODE => '0',
 461             CEB1 => '0',
 462             CEB2 => '0',
 463             CEC => '1',
 464             CECARRYIN => '0',
 465             CECTRL => '0',
 466             CED => '0',
 467             CEINMODE => '0',
 468             CEM => m_in.valid,
 469             CEP => '0',
 470             CLK => clk,
 471             D => (others => '0'),
 472             INMODE => "00000",
 473             MULTSIGNIN => '0',
 474             OPMODE => "0110101",
 475             P => m13_p,
 476             PCIN => (others => '0'),
 477             PCOUT => m13_pc,
 478             RSTA => '0',
 479             RSTALLCARRYIN => '0',
 480             RSTALUMODE => '0',
 481             RSTB => '0',
 482             RSTC => '0',
 483             RSTCTRL => '0',
 484             RSTD => '0',
 485             RSTINMODE => '0',
 486             RSTM => '0',
 487             RSTP => '0'
 488             );
 489
 490     m20: DSP48E1
 491         generic map (
 492             ACASCREG => 0,
 493             ALUMODEREG => 0,
 494             AREG => 0,
 495             BCASCREG => 0,
 496             BREG => 0,
 497             CARRYINREG => 0,
 498             CARRYINSELREG => 0,
 499             INMODEREG => 0,
 500             OPMODEREG => 0,
 501             PREG => 0
 502             )
 503         port map (
 504             A => "000000" & m_in.data1(63 downto 40),
 505             ACIN => (others => '0'),
 506             ALUMODE => "0000",
 507             B => '0' & m_in.data2(16 downto 0),
 508             BCIN => (others => '0'),
 509             C => (others => '0'),
 510             CARRYCASCIN => '0',
 511             CARRYIN => '0',
 512             CARRYINSEL => "000",
 513             CEA1 => '0',
 514             CEA2 => '0',
 515             CEAD => '0',
 516             CEALUMODE => '0',
 517             CEB1 => '0',
 518             CEB2 => '0',
 519             CEC => '1',
 520             CECARRYIN => '0',
 521             CECTRL => '0',
 522             CED => '0',
 523             CEINMODE => '0',
 524             CEM => m_in.valid,
 525             CEP => '0',
 526             CLK => clk,
 527             D => (others => '0'),
 528             INMODE => "00000",
 529             MULTSIGNIN => '0',
 530             OPMODE => "0010101",
 531             P => m20_p,
 532             PCIN => m11_pc,
 533             RSTA => '0',
 534             RSTALLCARRYIN => '0',
 535             RSTALUMODE => '0',
 536             RSTB => '0',
 537             RSTC => '0',
 538             RSTCTRL => '0',
 539             RSTD => '0',
 540             RSTINMODE => '0',
 541             RSTM => '0',
 542             RSTP => '0'
 543             );
 544
 545     m21: DSP48E1
 546         generic map (
 547             ACASCREG => 0,
 548             ALUMODEREG => 0,
 549             AREG => 0,
 550             BCASCREG => 0,
 551             BREG => 0,
 552             CARRYINREG => 0,
 553             CARRYINSELREG => 0,
 554             INMODEREG => 0,
 555             OPMODEREG => 0,
 556             PREG => 0
 557             )
 558         port map (
 559             A => "000000" & m_in.data1(63 downto 40),
 560             ACIN => (others => '0'),
 561             ALUMODE => "0000",
 562             B => '0' & m_in.data2(33 downto 17),
 563             BCIN => (others => '0'),
 564             C => (others => '0'),
 565             CARRYCASCIN => '0',
 566             CARRYIN => '0',
 567             CARRYINSEL => "000",
 568             CEA1 => '0',
 569             CEA2 => '0',
 570             CEAD => '0',
 571             CEALUMODE => '0',
 572             CEB1 => '0',
 573             CEB2 => '0',
 574             CEC => '1',
 575             CECARRYIN => '0',
 576             CECTRL => '0',
 577             CED => '0',
 578             CEINMODE => '0',
 579             CEM => m_in.valid,
 580             CEP => '0',
 581             CLK => clk,
 582             D => (others => '0'),
 583             INMODE => "00000",
 584             MULTSIGNIN => '0',
 585             OPMODE => "0010101",
 586             P => m21_p,
 587             PCIN => m12_pc,
 588             RSTA => '0',
 589             RSTALLCARRYIN => '0',
 590             RSTALUMODE => '0',
 591             RSTB => '0',
 592             RSTC => '0',
 593             RSTCTRL => '0',
 594             RSTD => '0',
 595             RSTINMODE => '0',
 596             RSTM => '0',
 597             RSTP => '0'
 598             );
 599
 600     m22: DSP48E1
 601         generic map (
 602             ACASCREG => 0,
 603             ALUMODEREG => 0,
 604             AREG => 0,
 605             BCASCREG => 0,
 606             BREG => 0,
 607             CARRYINREG => 0,
 608             CARRYINSELREG => 0,
 609             INMODEREG => 0,
 610             OPMODEREG => 0,
 611             PREG => 0
 612             )
 613         port map (
 614             A => "000000" & m_in.data1(63 downto 40),
 615             ACIN => (others => '0'),
 616             ALUMODE => "0000",
 617             B => '0' & m_in.data2(50 downto 34),
 618             BCIN => (others => '0'),
 619             C => (others => '0'),
 620             CARRYCASCIN => '0',
 621             CARRYIN => '0',
 622             CARRYINSEL => "000",
 623             CEA1 => '0',
 624             CEA2 => '0',
 625             CEAD => '0',
 626             CEALUMODE => '0',
 627             CEB1 => '0',
 628             CEB2 => '0',
 629             CEC => '1',
 630             CECARRYIN => '0',
 631             CECTRL => '0',
 632             CED => '0',
 633             CEINMODE => '0',
 634             CEM => m_in.valid,
 635             CEP => '0',
 636             CLK => clk,
 637             D => (others => '0'),
 638             INMODE => "00000",
 639             MULTSIGNIN => '0',
 640             OPMODE => "0010101",
 641             P => m22_p,
 642             PCIN => m13_pc,
 643             RSTA => '0',
 644             RSTALLCARRYIN => '0',
 645             RSTALUMODE => '0',
 646             RSTB => '0',
 647             RSTC => '0',
 648             RSTCTRL => '0',
 649             RSTD => '0',
 650             RSTINMODE => '0',
 651             RSTM => '0',
 652             RSTP => '0'
 653             );
 654
 655     m23: DSP48E1
 656         generic map (
 657             ACASCREG => 0,
 658             ALUMODEREG => 0,
 659             AREG => 0,
 660             BCASCREG => 0,
 661             BREG => 0,
 662             CARRYINREG => 0,
 663             CARRYINSELREG => 0,
 664             INMODEREG => 0,
 665             OPMODEREG => 0,
 666             PREG => 0
 667             )
 668         port map (
 669             A => "000000" & m_in.data1(63 downto 40),
 670             ACIN => (others => '0'),
 671             ALUMODE => "0000",
 672             B => "00000" & m_in.data2(63 downto 51),
 673             BCIN => (others => '0'),
 674             C => x"00" & "000" & addend(127 downto 91),
 675             CARRYCASCIN => '0',
 676             CARRYIN => '0',
 677             CARRYINSEL => "000",
 678             CEA1 => '0',
 679             CEA2 => '0',
 680             CEAD => '0',
 681             CEALUMODE => '0',
 682             CEB1 => '0',
 683             CEB2 => '0',
 684             CEC => '1',
 685             CECARRYIN => '0',
 686             CECTRL => '0',
 687             CED => '0',
 688             CEINMODE => '0',
 689             CEM => m_in.valid,
 690             CEP => '0',
 691             CLK => clk,
 692             D => (others => '0'),
 693             INMODE => "00000",
 694             MULTSIGNIN => '0',
 695             OPMODE => "0110101",
 696             P => m23_p,
 697             PCIN => (others => '0'),
 698             RSTA => '0',
 699             RSTALLCARRYIN => '0',
 700             RSTALUMODE => '0',
 701             RSTB => '0',
 702             RSTC => '0',
 703             RSTCTRL => '0',
 704             RSTD => '0',
 705             RSTINMODE => '0',
 706             RSTM => '0',
 707             RSTP => '0'
 708             );
 709
 710     s0: DSP48E1
 711         generic map (
 712             ACASCREG => 1,
 713             ALUMODEREG => 0,
 714             AREG => 1,
 715             BCASCREG => 1,
 716             BREG => 1,
 717             CARRYINREG => 0,
 718             CARRYINSELREG => 0,
 719             CREG => 1,
 720             INMODEREG => 0,
 721             MREG => 0,
 722             OPMODEREG => 0,
 723             PREG => 0,
 724             USE_MULT => "none"
 725             )
 726         port map (
 727             A => m22_p(5 downto 0) & x"0000" & m10_p(34 downto 27),
 728             ACIN => (others => '0'),
 729             ALUMODE => "0000",
 730             B => m10_p(26 downto 9),
 731             BCIN => (others => '0'),
 732             C => m20_p(39 downto 0) & m02_p(5 downto 0) & "00",
 733             CARRYCASCIN => '0',
 734             CARRYIN => '0',
 735             CARRYINSEL => "000",
 736             CARRYOUT => s0_carry,
 737             CEA1 => '0',
 738             CEA2 => valid_1,
 739             CEAD => '0',
 740             CEALUMODE => '0',
 741             CEB1 => '0',
 742             CEB2 => valid_1,
 743             CEC => valid_1,
 744             CECARRYIN => '0',
 745             CECTRL => '0',
 746             CED => '0',
 747             CEINMODE => '0',
 748             CEM => '0',
 749             CEP => '0',
 750             CLK => clk,
 751             D => (others => '0'),
 752             INMODE => "00000",
 753             MULTSIGNIN => '0',
 754             OPMODE => "0001111",
 755             PCIN => (others => '0'),
 756             PCOUT => s0_pc,
 757             RSTA => '0',
 758             RSTALLCARRYIN => '0',
 759             RSTALUMODE => '0',
 760             RSTB => '0',
 761             RSTC => '0',
 762             RSTCTRL => '0',
 763             RSTD => '0',
 764             RSTINMODE => '0',
 765             RSTM => '0',
 766             RSTP => '0'
 767             );
 768
 769     s1: DSP48E1
 770         generic map (
 771             ACASCREG => 1,
 772             ALUMODEREG => 0,
 773             AREG => 1,
 774             BCASCREG => 1,
 775             BREG => 1,
 776             CARRYINREG => 0,
 777             CARRYINSELREG => 0,
 778             CREG => 1,
 779             INMODEREG => 0,
 780             MREG => 0,
 781             OPMODEREG => 0,
 782             PREG => 0,
 783             USE_MULT => "none"
 784             )
 785         port map (
 786             A => x"000" & m22_p(41 downto 24),
 787             ACIN => (others => '0'),
 788             ALUMODE => "0000",
 789             B => m22_p(23 downto 6),
 790             BCIN => (others => '0'),
 791             C => m23_p(36 downto 0) & x"00" & "0" & m20_p(41 downto 40),
 792             CARRYCASCIN => '0',
 793             CARRYIN => s0_carry(3),
 794             CARRYINSEL => "000",
 795             CEA1 => '0',
 796             CEA2 => valid_1,
 797             CEAD => '0',
 798             CEALUMODE => '0',
 799             CEB1 => '0',
 800             CEB2 => valid_1,
 801             CEC => valid_1,
 802             CECARRYIN => '0',
 803             CECTRL => '0',
 804             CED => '0',
 805             CEINMODE => '0',
 806             CEM => '0',
 807             CEP => '0',
 808             CLK => clk,
 809             D => (others => '0'),
 810             INMODE => "00000",
 811             MULTSIGNIN => '0',
 812             OPMODE => "0001111",
 813             PCIN => (others => '0'),
 814             PCOUT => s1_pc,
 815             RSTA => '0',
 816             RSTALLCARRYIN => '0',
 817             RSTALUMODE => '0',
 818             RSTB => '0',
 819             RSTC => '0',
 820             RSTCTRL => '0',
 821             RSTD => '0',
 822             RSTINMODE => '0',
 823             RSTM => '0',
 824             RSTP => '0'
 825             );
 826
 827     -- mask is 0 for 32-bit ops, 0x0000ffffffff for 64-bit
 828     p0_mask(47 downto 31) <= (others => '0');
 829     p0_mask(30 downto 0) <= (others => not r32_1);
 830
 831     p0: DSP48E1
 832         generic map (
 833             ACASCREG => 1,
 834             ALUMODEREG => 1,
 835             AREG => 1,
 836             BCASCREG => 1,
 837             BREG => 1,
 838             CARRYINREG => 0,
 839             CARRYINSELREG => 0,
 840             CREG => 1,
 841             INMODEREG => 0,
 842             MREG => 0,
 843             OPMODEREG => 0,
 844             PREG => 0,
 845             SEL_MASK => "C",
 846             USE_MULT => "none",
 847             USE_PATTERN_DETECT => "PATDET"
 848             )
 849         port map (
 850             A => m21_p(22 downto 0) & m03_p(5 downto 0) & '0',
 851             ACIN => (others => '0'),
 852             ALUMODE => "00" & rnot_1 & '0',
 853             B => (others => '0'),
 854             BCIN => (others => '0'),
 855             C => p0_mask,
 856             CARRYCASCIN => '0',
 857             CARRYIN => '0',
 858             CARRYINSEL => "000",
 859             CARRYOUT => p0_carry,
 860             CEA1 => '0',
 861             CEA2 => valid_1,
 862             CEAD => '0',
 863             CEALUMODE => valid_1,
 864             CEB1 => '0',
 865             CEB2 => valid_1,
 866             CEC => valid_1,
 867             CECARRYIN => '0',
 868             CECTRL => '0',
 869             CED => '0',
 870             CEINMODE => '0',
 871             CEM => '0',
 872             CEP => '0',
 873             CLK => clk,
 874             D => (others => '0'),
 875             INMODE => "00000",
 876             MULTSIGNIN => '0',
 877             OPMODE => "0010011",
 878             P => product(79 downto 32),
 879             PATTERNDETECT => p0_pat,
 880             PATTERNBDETECT => p0_patb,
 881             PCIN => s0_pc,
 882             RSTA => '0',
 883             RSTALLCARRYIN => '0',
 884             RSTALUMODE => '0',
 885             RSTB => '0',
 886             RSTC => '0',
 887             RSTCTRL => '0',
 888             RSTD => '0',
 889             RSTINMODE => '0',
 890             RSTM => '0',
 891             RSTP => '0'
 892             );
 893
 894     p1: DSP48E1
 895         generic map (
 896             ACASCREG => 1,
 897             ALUMODEREG => 1,
 898             AREG => 1,
 899             BCASCREG => 1,
 900             BREG => 1,
 901             CARRYINREG => 0,
 902             CARRYINSELREG => 0,
 903             CREG => 0,
 904             INMODEREG => 0,
 905             MASK => x"000000000000",
 906             MREG => 0,
 907             OPMODEREG => 0,
 908             PREG => 0,
 909             USE_MULT => "none",
 910             USE_PATTERN_DETECT => "PATDET"
 911             )
 912         port map (
 913             A => x"0000000" & '0' & m21_p(41),
 914             ACIN => (others => '0'),
 915             ALUMODE => "00" & rnot_1 & '0',
 916             B => m21_p(40 downto 23),
 917             BCIN => (others => '0'),
 918             C => (others => '0'),
 919             CARRYCASCIN => '0',
 920             CARRYIN => p0_carry(3),
 921             CARRYINSEL => "000",
 922             CEA1 => '0',
 923             CEA2 => valid_1,
 924             CEAD => '0',
 925             CEALUMODE => valid_1,
 926             CEB1 => '0',
 927             CEB2 => valid_1,
 928             CEC => '0',
 929             CECARRYIN => '0',
 930             CECTRL => '0',
 931             CED => '0',
 932             CEINMODE => '0',
 933             CEM => '0',
 934             CEP => '0',
 935             CLK => clk,
 936             D => (others => '0'),
 937             INMODE => "00000",
 938             MULTSIGNIN => '0',
 939             OPMODE => "0010011",
 940             P => product(127 downto 80),
 941             PATTERNDETECT => p1_pat,
 942             PATTERNBDETECT => p1_patb,
 943             PCIN => s1_pc,
 944             RSTA => '0',
 945             RSTALLCARRYIN => '0',
 946             RSTALUMODE => '0',
 947             RSTB => '0',
 948             RSTC => '0',
 949             RSTCTRL => '0',
 950             RSTD => '0',
 951             RSTINMODE => '0',
 952             RSTM => '0',
 953             RSTP => '0'
 954             );
 955
 956     product(31 downto 0) <= product_lo xor (31 downto 0 => req_not);
 957
 958     mult_out: process(all)
 959         variable ov : std_ulogic;
 960     begin
 961         -- set overflow if the high bits are neither all zeroes nor all ones
 962         if req_32bit = '0' then
 963             ov := not ((p1_pat and p0_pat) or (p1_patb and p0_patb));
 964         else
 965             ov := not ((p1_pat and p0_pat and not product(31)) or
 966                        (p1_patb and p0_patb and product(31)));
 967         end if;
 968         ovf_in <= ov;
 969
 970         m_out.result <= product;
 971         m_out.overflow <= overflow;
 972     end process;
 973
 974     process(clk)
 975     begin
 976         if rising_edge(clk) then
 977             product_lo <= m10_p(8 downto 0) & m01_p(5 downto 0) & m00_p(16 downto 0);
 978             m_out.valid <= valid_1;
 979             valid_1 <= m_in.valid;
 980             req_32bit <= r32_1;
 981             r32_1 <= m_in.is_32bit;
 982             req_not <= rnot_1;
 983             rnot_1 <= m_in.not_result;
 984             overflow <= ovf_in;
 985         end if;
 986     end process;
 987
 988 end architecture behaviour;