--- /dev/null
+// -----------------------------------------------------------------------------
+// Auto-Generated by: __ _ __ _ __
+// / / (_) /____ | |/_/
+// / /__/ / __/ -_)> <
+// /____/_/\__/\__/_/|_|
+// Build your hardware, easily!
+// https://github.com/enjoy-digital/litex
+//
+// Filename : litedram_core.v
+// Device : LFE5U-85F-8CABGA381
+// LiteX sha1 : 1b62f142
+// Date : 2022-02-21 23:17:57
+//------------------------------------------------------------------------------
+
+
+//------------------------------------------------------------------------------
+// Module
+//------------------------------------------------------------------------------
+
+module litedram_core (
+ input wire clk,
+ input wire rst,
+ output wire pll_locked,
+ output wire [14:0] ddram_a,
+ output wire [2:0] ddram_ba,
+ output wire ddram_ras_n,
+ output wire ddram_cas_n,
+ output wire ddram_we_n,
+ output wire ddram_cs_n,
+ output wire [3:0] ddram_dm,
+ input wire [31:0] ddram_dq,
+ input wire [3:0] ddram_dqs_p,
+ input wire [3:0] ddram_dqs_n,
+ output wire [1:0] ddram_clk_p,
+ input wire ddram_clk_n,
+ output wire ddram_cke,
+ output wire ddram_odt,
+ output wire ddram_reset_n,
+ output wire init_done,
+ output wire init_error,
+ input wire [29:0] wb_ctrl_adr,
+ input wire [31:0] wb_ctrl_dat_w,
+ output wire [31:0] wb_ctrl_dat_r,
+ input wire [3:0] wb_ctrl_sel,
+ input wire wb_ctrl_cyc,
+ input wire wb_ctrl_stb,
+ output wire wb_ctrl_ack,
+ input wire wb_ctrl_we,
+ input wire [2:0] wb_ctrl_cti,
+ input wire [1:0] wb_ctrl_bte,
+ output wire wb_ctrl_err,
+ output wire user_clk,
+ output wire user_rst,
+ input wire user_port_native_0_cmd_valid,
+ output wire user_port_native_0_cmd_ready,
+ input wire user_port_native_0_cmd_we,
+ input wire [24:0] user_port_native_0_cmd_addr,
+ input wire user_port_native_0_wdata_valid,
+ output wire user_port_native_0_wdata_ready,
+ input wire [31:0] user_port_native_0_wdata_we,
+ input wire [255:0] user_port_native_0_wdata_data,
+ output wire user_port_native_0_rdata_valid,
+ input wire user_port_native_0_rdata_ready,
+ output wire [255:0] user_port_native_0_rdata_data
+);
+
+
+//------------------------------------------------------------------------------
+// Signals
+//------------------------------------------------------------------------------
+
+reg crg_rst = 1'd0;
+wire init_clk;
+wire init_rst;
+wire por_clk;
+wire sys_clk;
+wire sys_rst;
+wire sys2x_clk;
+wire sys2x_rst;
+wire sys2x_i_clk;
+wire crg_stop;
+wire crg_reset0;
+reg [15:0] crg_por_count = 16'd65535;
+wire crg_por_done;
+wire crg_sys2x_clk_ecsout;
+wire crg_reset1;
+wire crg_locked;
+reg crg_stdby = 1'd0;
+wire crg_clkin;
+wire crg_clkout0;
+wire crg_clkout1;
+wire ddrphy_pause0;
+wire ddrphy_stop0;
+wire ddrphy_delay0;
+wire ddrphy_reset0;
+wire ddrphy_new_lock;
+reg ddrphy_update = 1'd0;
+reg ddrphy_stop1 = 1'd0;
+reg ddrphy_freeze = 1'd0;
+reg ddrphy_pause1 = 1'd0;
+reg ddrphy_reset1 = 1'd0;
+wire ddrphy_lock0;
+wire ddrphy_delay1;
+wire ddrphy_lock1;
+reg ddrphy_lock_d = 1'd0;
+reg [6:0] ddrphy_counter = 7'd0;
+reg [3:0] ddrphy_dly_sel_storage = 4'd0;
+reg ddrphy_dly_sel_re = 1'd0;
+reg ddrphy_rdly_dq_rst_re = 1'd0;
+wire ddrphy_rdly_dq_rst_r;
+reg ddrphy_rdly_dq_rst_we = 1'd0;
+reg ddrphy_rdly_dq_rst_w = 1'd0;
+reg ddrphy_rdly_dq_inc_re = 1'd0;
+wire ddrphy_rdly_dq_inc_r;
+reg ddrphy_rdly_dq_inc_we = 1'd0;
+reg ddrphy_rdly_dq_inc_w = 1'd0;
+reg ddrphy_rdly_dq_bitslip_rst_re = 1'd0;
+wire ddrphy_rdly_dq_bitslip_rst_r;
+reg ddrphy_rdly_dq_bitslip_rst_we = 1'd0;
+reg ddrphy_rdly_dq_bitslip_rst_w = 1'd0;
+reg ddrphy_rdly_dq_bitslip_re = 1'd0;
+wire ddrphy_rdly_dq_bitslip_r;
+reg ddrphy_rdly_dq_bitslip_we = 1'd0;
+reg ddrphy_rdly_dq_bitslip_w = 1'd0;
+reg ddrphy_burstdet_clr_re = 1'd0;
+wire ddrphy_burstdet_clr_r;
+reg ddrphy_burstdet_clr_we = 1'd0;
+reg ddrphy_burstdet_clr_w = 1'd0;
+reg [3:0] ddrphy_burstdet_seen_status = 4'd0;
+wire ddrphy_burstdet_seen_we;
+reg ddrphy_burstdet_seen_re = 1'd0;
+wire [3:0] ddrphy_datavalid;
+wire [14:0] ddrphy_dfi_p0_address;
+wire [2:0] ddrphy_dfi_p0_bank;
+wire ddrphy_dfi_p0_cas_n;
+wire ddrphy_dfi_p0_cs_n;
+wire ddrphy_dfi_p0_ras_n;
+wire ddrphy_dfi_p0_we_n;
+wire ddrphy_dfi_p0_cke;
+wire ddrphy_dfi_p0_odt;
+wire ddrphy_dfi_p0_reset_n;
+wire ddrphy_dfi_p0_act_n;
+wire [127:0] ddrphy_dfi_p0_wrdata;
+wire ddrphy_dfi_p0_wrdata_en;
+wire [15:0] ddrphy_dfi_p0_wrdata_mask;
+wire ddrphy_dfi_p0_rddata_en;
+reg [127:0] ddrphy_dfi_p0_rddata = 128'd0;
+wire ddrphy_dfi_p0_rddata_valid;
+wire [14:0] ddrphy_dfi_p1_address;
+wire [2:0] ddrphy_dfi_p1_bank;
+wire ddrphy_dfi_p1_cas_n;
+wire ddrphy_dfi_p1_cs_n;
+wire ddrphy_dfi_p1_ras_n;
+wire ddrphy_dfi_p1_we_n;
+wire ddrphy_dfi_p1_cke;
+wire ddrphy_dfi_p1_odt;
+wire ddrphy_dfi_p1_reset_n;
+wire ddrphy_dfi_p1_act_n;
+wire [127:0] ddrphy_dfi_p1_wrdata;
+wire ddrphy_dfi_p1_wrdata_en;
+wire [15:0] ddrphy_dfi_p1_wrdata_mask;
+wire ddrphy_dfi_p1_rddata_en;
+reg [127:0] ddrphy_dfi_p1_rddata = 128'd0;
+wire ddrphy_dfi_p1_rddata_valid;
+wire ddrphy_bl8_chunk;
+wire ddrphy_pad_oddrx2f0;
+wire ddrphy_pad_oddrx2f1;
+wire ddrphy_pad_oddrx2f2;
+wire ddrphy_pad_oddrx2f3;
+wire ddrphy_pad_oddrx2f4;
+wire ddrphy_pad_oddrx2f5;
+wire ddrphy_pad_oddrx2f6;
+wire ddrphy_pad_oddrx2f7;
+wire ddrphy_pad_oddrx2f8;
+wire ddrphy_pad_oddrx2f9;
+wire ddrphy_pad_oddrx2f10;
+wire ddrphy_pad_oddrx2f11;
+wire ddrphy_pad_oddrx2f12;
+wire ddrphy_pad_oddrx2f13;
+wire ddrphy_pad_oddrx2f14;
+wire ddrphy_pad_oddrx2f15;
+wire ddrphy_pad_oddrx2f16;
+wire ddrphy_pad_oddrx2f17;
+wire ddrphy_pad_oddrx2f18;
+wire ddrphy_pad_oddrx2f19;
+wire ddrphy_pad_oddrx2f20;
+wire ddrphy_pad_oddrx2f21;
+wire ddrphy_pad_oddrx2f22;
+wire ddrphy_pad_oddrx2f23;
+wire ddrphy_pad_oddrx2f24;
+wire ddrphy_pad_oddrx2f25;
+wire ddrphy_pad_oddrx2f26;
+wire ddrphy_dq_oe;
+wire ddrphy_dqs_re;
+wire ddrphy_dqs_oe;
+wire ddrphy_dqs_postamble;
+wire ddrphy_dqs_preamble;
+wire ddrphy_dqs_i0;
+wire ddrphy_dqsr900;
+wire ddrphy_dqsw2700;
+wire ddrphy_dqsw0;
+wire [2:0] ddrphy_rdpntr0;
+wire [2:0] ddrphy_wrpntr0;
+reg [6:0] ddrphy_rdly0 = 7'd0;
+wire ddrphy_burstdet0;
+reg ddrphy_burstdet_d0 = 1'd0;
+wire ddrphy_dqs0;
+wire ddrphy_dqs_oe_n0;
+reg [7:0] ddrphy_dm_o_data0 = 8'd0;
+reg [7:0] ddrphy_dm_o_data_d0 = 8'd0;
+reg [3:0] ddrphy_dm_o_data_muxed0 = 4'd0;
+wire ddrphy_dq_o0;
+wire ddrphy_dq_i0;
+wire ddrphy_dq_oe_n0;
+wire ddrphy_dq_i_delayed0;
+wire [7:0] ddrphy_dq_i_data0;
+reg [7:0] ddrphy_dq_o_data0 = 8'd0;
+reg [7:0] ddrphy_dq_o_data_d0 = 8'd0;
+reg [3:0] ddrphy_dq_o_data_muxed0 = 4'd0;
+wire [3:0] ddrphy_bitslip0_i;
+reg [3:0] ddrphy_bitslip0_o = 4'd0;
+reg [1:0] ddrphy_bitslip0_value = 2'd0;
+reg [7:0] ddrphy_bitslip0_r = 8'd0;
+reg [3:0] ddrphy_dq_i_bitslip_o_d0 = 4'd0;
+wire ddrphy_dq_o1;
+wire ddrphy_dq_i1;
+wire ddrphy_dq_oe_n1;
+wire ddrphy_dq_i_delayed1;
+wire [7:0] ddrphy_dq_i_data1;
+reg [7:0] ddrphy_dq_o_data1 = 8'd0;
+reg [7:0] ddrphy_dq_o_data_d1 = 8'd0;
+reg [3:0] ddrphy_dq_o_data_muxed1 = 4'd0;
+wire [3:0] ddrphy_bitslip1_i;
+reg [3:0] ddrphy_bitslip1_o = 4'd0;
+reg [1:0] ddrphy_bitslip1_value = 2'd0;
+reg [7:0] ddrphy_bitslip1_r = 8'd0;
+reg [3:0] ddrphy_dq_i_bitslip_o_d1 = 4'd0;
+wire ddrphy_dq_o2;
+wire ddrphy_dq_i2;
+wire ddrphy_dq_oe_n2;
+wire ddrphy_dq_i_delayed2;
+wire [7:0] ddrphy_dq_i_data2;
+reg [7:0] ddrphy_dq_o_data2 = 8'd0;
+reg [7:0] ddrphy_dq_o_data_d2 = 8'd0;
+reg [3:0] ddrphy_dq_o_data_muxed2 = 4'd0;
+wire [3:0] ddrphy_bitslip2_i;
+reg [3:0] ddrphy_bitslip2_o = 4'd0;
+reg [1:0] ddrphy_bitslip2_value = 2'd0;
+reg [7:0] ddrphy_bitslip2_r = 8'd0;
+reg [3:0] ddrphy_dq_i_bitslip_o_d2 = 4'd0;
+wire ddrphy_dq_o3;
+wire ddrphy_dq_i3;
+wire ddrphy_dq_oe_n3;
+wire ddrphy_dq_i_delayed3;
+wire [7:0] ddrphy_dq_i_data3;
+reg [7:0] ddrphy_dq_o_data3 = 8'd0;
+reg [7:0] ddrphy_dq_o_data_d3 = 8'd0;
+reg [3:0] ddrphy_dq_o_data_muxed3 = 4'd0;
+wire [3:0] ddrphy_bitslip3_i;
+reg [3:0] ddrphy_bitslip3_o = 4'd0;
+reg [1:0] ddrphy_bitslip3_value = 2'd0;
+reg [7:0] ddrphy_bitslip3_r = 8'd0;
+reg [3:0] ddrphy_dq_i_bitslip_o_d3 = 4'd0;
+wire ddrphy_dq_o4;
+wire ddrphy_dq_i4;
+wire ddrphy_dq_oe_n4;
+wire ddrphy_dq_i_delayed4;
+wire [7:0] ddrphy_dq_i_data4;
+reg [7:0] ddrphy_dq_o_data4 = 8'd0;
+reg [7:0] ddrphy_dq_o_data_d4 = 8'd0;
+reg [3:0] ddrphy_dq_o_data_muxed4 = 4'd0;
+wire [3:0] ddrphy_bitslip4_i;
+reg [3:0] ddrphy_bitslip4_o = 4'd0;
+reg [1:0] ddrphy_bitslip4_value = 2'd0;
+reg [7:0] ddrphy_bitslip4_r = 8'd0;
+reg [3:0] ddrphy_dq_i_bitslip_o_d4 = 4'd0;
+wire ddrphy_dq_o5;
+wire ddrphy_dq_i5;
+wire ddrphy_dq_oe_n5;
+wire ddrphy_dq_i_delayed5;
+wire [7:0] ddrphy_dq_i_data5;
+reg [7:0] ddrphy_dq_o_data5 = 8'd0;
+reg [7:0] ddrphy_dq_o_data_d5 = 8'd0;
+reg [3:0] ddrphy_dq_o_data_muxed5 = 4'd0;
+wire [3:0] ddrphy_bitslip5_i;
+reg [3:0] ddrphy_bitslip5_o = 4'd0;
+reg [1:0] ddrphy_bitslip5_value = 2'd0;
+reg [7:0] ddrphy_bitslip5_r = 8'd0;
+reg [3:0] ddrphy_dq_i_bitslip_o_d5 = 4'd0;
+wire ddrphy_dq_o6;
+wire ddrphy_dq_i6;
+wire ddrphy_dq_oe_n6;
+wire ddrphy_dq_i_delayed6;
+wire [7:0] ddrphy_dq_i_data6;
+reg [7:0] ddrphy_dq_o_data6 = 8'd0;
+reg [7:0] ddrphy_dq_o_data_d6 = 8'd0;
+reg [3:0] ddrphy_dq_o_data_muxed6 = 4'd0;
+wire [3:0] ddrphy_bitslip6_i;
+reg [3:0] ddrphy_bitslip6_o = 4'd0;
+reg [1:0] ddrphy_bitslip6_value = 2'd0;
+reg [7:0] ddrphy_bitslip6_r = 8'd0;
+reg [3:0] ddrphy_dq_i_bitslip_o_d6 = 4'd0;
+wire ddrphy_dq_o7;
+wire ddrphy_dq_i7;
+wire ddrphy_dq_oe_n7;
+wire ddrphy_dq_i_delayed7;
+wire [7:0] ddrphy_dq_i_data7;
+reg [7:0] ddrphy_dq_o_data7 = 8'd0;
+reg [7:0] ddrphy_dq_o_data_d7 = 8'd0;
+reg [3:0] ddrphy_dq_o_data_muxed7 = 4'd0;
+wire [3:0] ddrphy_bitslip7_i;
+reg [3:0] ddrphy_bitslip7_o = 4'd0;
+reg [1:0] ddrphy_bitslip7_value = 2'd0;
+reg [7:0] ddrphy_bitslip7_r = 8'd0;
+reg [3:0] ddrphy_dq_i_bitslip_o_d7 = 4'd0;
+wire ddrphy_dqs_i1;
+wire ddrphy_dqsr901;
+wire ddrphy_dqsw2701;
+wire ddrphy_dqsw1;
+wire [2:0] ddrphy_rdpntr1;
+wire [2:0] ddrphy_wrpntr1;
+reg [6:0] ddrphy_rdly1 = 7'd0;
+wire ddrphy_burstdet1;
+reg ddrphy_burstdet_d1 = 1'd0;
+wire ddrphy_dqs1;
+wire ddrphy_dqs_oe_n1;
+reg [7:0] ddrphy_dm_o_data1 = 8'd0;
+reg [7:0] ddrphy_dm_o_data_d1 = 8'd0;
+reg [3:0] ddrphy_dm_o_data_muxed1 = 4'd0;
+wire ddrphy_dq_o8;
+wire ddrphy_dq_i8;
+wire ddrphy_dq_oe_n8;
+wire ddrphy_dq_i_delayed8;
+wire [7:0] ddrphy_dq_i_data8;
+reg [7:0] ddrphy_dq_o_data8 = 8'd0;
+reg [7:0] ddrphy_dq_o_data_d8 = 8'd0;
+reg [3:0] ddrphy_dq_o_data_muxed8 = 4'd0;
+wire [3:0] ddrphy_bitslip8_i;
+reg [3:0] ddrphy_bitslip8_o = 4'd0;
+reg [1:0] ddrphy_bitslip8_value = 2'd0;
+reg [7:0] ddrphy_bitslip8_r = 8'd0;
+reg [3:0] ddrphy_dq_i_bitslip_o_d8 = 4'd0;
+wire ddrphy_dq_o9;
+wire ddrphy_dq_i9;
+wire ddrphy_dq_oe_n9;
+wire ddrphy_dq_i_delayed9;
+wire [7:0] ddrphy_dq_i_data9;
+reg [7:0] ddrphy_dq_o_data9 = 8'd0;
+reg [7:0] ddrphy_dq_o_data_d9 = 8'd0;
+reg [3:0] ddrphy_dq_o_data_muxed9 = 4'd0;
+wire [3:0] ddrphy_bitslip9_i;
+reg [3:0] ddrphy_bitslip9_o = 4'd0;
+reg [1:0] ddrphy_bitslip9_value = 2'd0;
+reg [7:0] ddrphy_bitslip9_r = 8'd0;
+reg [3:0] ddrphy_dq_i_bitslip_o_d9 = 4'd0;
+wire ddrphy_dq_o10;
+wire ddrphy_dq_i10;
+wire ddrphy_dq_oe_n10;
+wire ddrphy_dq_i_delayed10;
+wire [7:0] ddrphy_dq_i_data10;
+reg [7:0] ddrphy_dq_o_data10 = 8'd0;
+reg [7:0] ddrphy_dq_o_data_d10 = 8'd0;
+reg [3:0] ddrphy_dq_o_data_muxed10 = 4'd0;
+wire [3:0] ddrphy_bitslip10_i;
+reg [3:0] ddrphy_bitslip10_o = 4'd0;
+reg [1:0] ddrphy_bitslip10_value = 2'd0;
+reg [7:0] ddrphy_bitslip10_r = 8'd0;
+reg [3:0] ddrphy_dq_i_bitslip_o_d10 = 4'd0;
+wire ddrphy_dq_o11;
+wire ddrphy_dq_i11;
+wire ddrphy_dq_oe_n11;
+wire ddrphy_dq_i_delayed11;
+wire [7:0] ddrphy_dq_i_data11;
+reg [7:0] ddrphy_dq_o_data11 = 8'd0;
+reg [7:0] ddrphy_dq_o_data_d11 = 8'd0;
+reg [3:0] ddrphy_dq_o_data_muxed11 = 4'd0;
+wire [3:0] ddrphy_bitslip11_i;
+reg [3:0] ddrphy_bitslip11_o = 4'd0;
+reg [1:0] ddrphy_bitslip11_value = 2'd0;
+reg [7:0] ddrphy_bitslip11_r = 8'd0;
+reg [3:0] ddrphy_dq_i_bitslip_o_d11 = 4'd0;
+wire ddrphy_dq_o12;
+wire ddrphy_dq_i12;
+wire ddrphy_dq_oe_n12;
+wire ddrphy_dq_i_delayed12;
+wire [7:0] ddrphy_dq_i_data12;
+reg [7:0] ddrphy_dq_o_data12 = 8'd0;
+reg [7:0] ddrphy_dq_o_data_d12 = 8'd0;
+reg [3:0] ddrphy_dq_o_data_muxed12 = 4'd0;
+wire [3:0] ddrphy_bitslip12_i;
+reg [3:0] ddrphy_bitslip12_o = 4'd0;
+reg [1:0] ddrphy_bitslip12_value = 2'd0;
+reg [7:0] ddrphy_bitslip12_r = 8'd0;
+reg [3:0] ddrphy_dq_i_bitslip_o_d12 = 4'd0;
+wire ddrphy_dq_o13;
+wire ddrphy_dq_i13;
+wire ddrphy_dq_oe_n13;
+wire ddrphy_dq_i_delayed13;
+wire [7:0] ddrphy_dq_i_data13;
+reg [7:0] ddrphy_dq_o_data13 = 8'd0;
+reg [7:0] ddrphy_dq_o_data_d13 = 8'd0;
+reg [3:0] ddrphy_dq_o_data_muxed13 = 4'd0;
+wire [3:0] ddrphy_bitslip13_i;
+reg [3:0] ddrphy_bitslip13_o = 4'd0;
+reg [1:0] ddrphy_bitslip13_value = 2'd0;
+reg [7:0] ddrphy_bitslip13_r = 8'd0;
+reg [3:0] ddrphy_dq_i_bitslip_o_d13 = 4'd0;
+wire ddrphy_dq_o14;
+wire ddrphy_dq_i14;
+wire ddrphy_dq_oe_n14;
+wire ddrphy_dq_i_delayed14;
+wire [7:0] ddrphy_dq_i_data14;
+reg [7:0] ddrphy_dq_o_data14 = 8'd0;
+reg [7:0] ddrphy_dq_o_data_d14 = 8'd0;
+reg [3:0] ddrphy_dq_o_data_muxed14 = 4'd0;
+wire [3:0] ddrphy_bitslip14_i;
+reg [3:0] ddrphy_bitslip14_o = 4'd0;
+reg [1:0] ddrphy_bitslip14_value = 2'd0;
+reg [7:0] ddrphy_bitslip14_r = 8'd0;
+reg [3:0] ddrphy_dq_i_bitslip_o_d14 = 4'd0;
+wire ddrphy_dq_o15;
+wire ddrphy_dq_i15;
+wire ddrphy_dq_oe_n15;
+wire ddrphy_dq_i_delayed15;
+wire [7:0] ddrphy_dq_i_data15;
+reg [7:0] ddrphy_dq_o_data15 = 8'd0;
+reg [7:0] ddrphy_dq_o_data_d15 = 8'd0;
+reg [3:0] ddrphy_dq_o_data_muxed15 = 4'd0;
+wire [3:0] ddrphy_bitslip15_i;
+reg [3:0] ddrphy_bitslip15_o = 4'd0;
+reg [1:0] ddrphy_bitslip15_value = 2'd0;
+reg [7:0] ddrphy_bitslip15_r = 8'd0;
+reg [3:0] ddrphy_dq_i_bitslip_o_d15 = 4'd0;
+wire ddrphy_dqs_i2;
+wire ddrphy_dqsr902;
+wire ddrphy_dqsw2702;
+wire ddrphy_dqsw2;
+wire [2:0] ddrphy_rdpntr2;
+wire [2:0] ddrphy_wrpntr2;
+reg [6:0] ddrphy_rdly2 = 7'd0;
+wire ddrphy_burstdet2;
+reg ddrphy_burstdet_d2 = 1'd0;
+wire ddrphy_dqs2;
+wire ddrphy_dqs_oe_n2;
+reg [7:0] ddrphy_dm_o_data2 = 8'd0;
+reg [7:0] ddrphy_dm_o_data_d2 = 8'd0;
+reg [3:0] ddrphy_dm_o_data_muxed2 = 4'd0;
+wire ddrphy_dq_o16;
+wire ddrphy_dq_i16;
+wire ddrphy_dq_oe_n16;
+wire ddrphy_dq_i_delayed16;
+wire [7:0] ddrphy_dq_i_data16;
+reg [7:0] ddrphy_dq_o_data16 = 8'd0;
+reg [7:0] ddrphy_dq_o_data_d16 = 8'd0;
+reg [3:0] ddrphy_dq_o_data_muxed16 = 4'd0;
+wire [3:0] ddrphy_bitslip16_i;
+reg [3:0] ddrphy_bitslip16_o = 4'd0;
+reg [1:0] ddrphy_bitslip16_value = 2'd0;
+reg [7:0] ddrphy_bitslip16_r = 8'd0;
+reg [3:0] ddrphy_dq_i_bitslip_o_d16 = 4'd0;
+wire ddrphy_dq_o17;
+wire ddrphy_dq_i17;
+wire ddrphy_dq_oe_n17;
+wire ddrphy_dq_i_delayed17;
+wire [7:0] ddrphy_dq_i_data17;
+reg [7:0] ddrphy_dq_o_data17 = 8'd0;
+reg [7:0] ddrphy_dq_o_data_d17 = 8'd0;
+reg [3:0] ddrphy_dq_o_data_muxed17 = 4'd0;
+wire [3:0] ddrphy_bitslip17_i;
+reg [3:0] ddrphy_bitslip17_o = 4'd0;
+reg [1:0] ddrphy_bitslip17_value = 2'd0;
+reg [7:0] ddrphy_bitslip17_r = 8'd0;
+reg [3:0] ddrphy_dq_i_bitslip_o_d17 = 4'd0;
+wire ddrphy_dq_o18;
+wire ddrphy_dq_i18;
+wire ddrphy_dq_oe_n18;
+wire ddrphy_dq_i_delayed18;
+wire [7:0] ddrphy_dq_i_data18;
+reg [7:0] ddrphy_dq_o_data18 = 8'd0;
+reg [7:0] ddrphy_dq_o_data_d18 = 8'd0;
+reg [3:0] ddrphy_dq_o_data_muxed18 = 4'd0;
+wire [3:0] ddrphy_bitslip18_i;
+reg [3:0] ddrphy_bitslip18_o = 4'd0;
+reg [1:0] ddrphy_bitslip18_value = 2'd0;
+reg [7:0] ddrphy_bitslip18_r = 8'd0;
+reg [3:0] ddrphy_dq_i_bitslip_o_d18 = 4'd0;
+wire ddrphy_dq_o19;
+wire ddrphy_dq_i19;
+wire ddrphy_dq_oe_n19;
+wire ddrphy_dq_i_delayed19;
+wire [7:0] ddrphy_dq_i_data19;
+reg [7:0] ddrphy_dq_o_data19 = 8'd0;
+reg [7:0] ddrphy_dq_o_data_d19 = 8'd0;
+reg [3:0] ddrphy_dq_o_data_muxed19 = 4'd0;
+wire [3:0] ddrphy_bitslip19_i;
+reg [3:0] ddrphy_bitslip19_o = 4'd0;
+reg [1:0] ddrphy_bitslip19_value = 2'd0;
+reg [7:0] ddrphy_bitslip19_r = 8'd0;
+reg [3:0] ddrphy_dq_i_bitslip_o_d19 = 4'd0;
+wire ddrphy_dq_o20;
+wire ddrphy_dq_i20;
+wire ddrphy_dq_oe_n20;
+wire ddrphy_dq_i_delayed20;
+wire [7:0] ddrphy_dq_i_data20;
+reg [7:0] ddrphy_dq_o_data20 = 8'd0;
+reg [7:0] ddrphy_dq_o_data_d20 = 8'd0;
+reg [3:0] ddrphy_dq_o_data_muxed20 = 4'd0;
+wire [3:0] ddrphy_bitslip20_i;
+reg [3:0] ddrphy_bitslip20_o = 4'd0;
+reg [1:0] ddrphy_bitslip20_value = 2'd0;
+reg [7:0] ddrphy_bitslip20_r = 8'd0;
+reg [3:0] ddrphy_dq_i_bitslip_o_d20 = 4'd0;
+wire ddrphy_dq_o21;
+wire ddrphy_dq_i21;
+wire ddrphy_dq_oe_n21;
+wire ddrphy_dq_i_delayed21;
+wire [7:0] ddrphy_dq_i_data21;
+reg [7:0] ddrphy_dq_o_data21 = 8'd0;
+reg [7:0] ddrphy_dq_o_data_d21 = 8'd0;
+reg [3:0] ddrphy_dq_o_data_muxed21 = 4'd0;
+wire [3:0] ddrphy_bitslip21_i;
+reg [3:0] ddrphy_bitslip21_o = 4'd0;
+reg [1:0] ddrphy_bitslip21_value = 2'd0;
+reg [7:0] ddrphy_bitslip21_r = 8'd0;
+reg [3:0] ddrphy_dq_i_bitslip_o_d21 = 4'd0;
+wire ddrphy_dq_o22;
+wire ddrphy_dq_i22;
+wire ddrphy_dq_oe_n22;
+wire ddrphy_dq_i_delayed22;
+wire [7:0] ddrphy_dq_i_data22;
+reg [7:0] ddrphy_dq_o_data22 = 8'd0;
+reg [7:0] ddrphy_dq_o_data_d22 = 8'd0;
+reg [3:0] ddrphy_dq_o_data_muxed22 = 4'd0;
+wire [3:0] ddrphy_bitslip22_i;
+reg [3:0] ddrphy_bitslip22_o = 4'd0;
+reg [1:0] ddrphy_bitslip22_value = 2'd0;
+reg [7:0] ddrphy_bitslip22_r = 8'd0;
+reg [3:0] ddrphy_dq_i_bitslip_o_d22 = 4'd0;
+wire ddrphy_dq_o23;
+wire ddrphy_dq_i23;
+wire ddrphy_dq_oe_n23;
+wire ddrphy_dq_i_delayed23;
+wire [7:0] ddrphy_dq_i_data23;
+reg [7:0] ddrphy_dq_o_data23 = 8'd0;
+reg [7:0] ddrphy_dq_o_data_d23 = 8'd0;
+reg [3:0] ddrphy_dq_o_data_muxed23 = 4'd0;
+wire [3:0] ddrphy_bitslip23_i;
+reg [3:0] ddrphy_bitslip23_o = 4'd0;
+reg [1:0] ddrphy_bitslip23_value = 2'd0;
+reg [7:0] ddrphy_bitslip23_r = 8'd0;
+reg [3:0] ddrphy_dq_i_bitslip_o_d23 = 4'd0;
+wire ddrphy_dqs_i3;
+wire ddrphy_dqsr903;
+wire ddrphy_dqsw2703;
+wire ddrphy_dqsw3;
+wire [2:0] ddrphy_rdpntr3;
+wire [2:0] ddrphy_wrpntr3;
+reg [6:0] ddrphy_rdly3 = 7'd0;
+wire ddrphy_burstdet3;
+reg ddrphy_burstdet_d3 = 1'd0;
+wire ddrphy_dqs3;
+wire ddrphy_dqs_oe_n3;
+reg [7:0] ddrphy_dm_o_data3 = 8'd0;
+reg [7:0] ddrphy_dm_o_data_d3 = 8'd0;
+reg [3:0] ddrphy_dm_o_data_muxed3 = 4'd0;
+wire ddrphy_dq_o24;
+wire ddrphy_dq_i24;
+wire ddrphy_dq_oe_n24;
+wire ddrphy_dq_i_delayed24;
+wire [7:0] ddrphy_dq_i_data24;
+reg [7:0] ddrphy_dq_o_data24 = 8'd0;
+reg [7:0] ddrphy_dq_o_data_d24 = 8'd0;
+reg [3:0] ddrphy_dq_o_data_muxed24 = 4'd0;
+wire [3:0] ddrphy_bitslip24_i;
+reg [3:0] ddrphy_bitslip24_o = 4'd0;
+reg [1:0] ddrphy_bitslip24_value = 2'd0;
+reg [7:0] ddrphy_bitslip24_r = 8'd0;
+reg [3:0] ddrphy_dq_i_bitslip_o_d24 = 4'd0;
+wire ddrphy_dq_o25;
+wire ddrphy_dq_i25;
+wire ddrphy_dq_oe_n25;
+wire ddrphy_dq_i_delayed25;
+wire [7:0] ddrphy_dq_i_data25;
+reg [7:0] ddrphy_dq_o_data25 = 8'd0;
+reg [7:0] ddrphy_dq_o_data_d25 = 8'd0;
+reg [3:0] ddrphy_dq_o_data_muxed25 = 4'd0;
+wire [3:0] ddrphy_bitslip25_i;
+reg [3:0] ddrphy_bitslip25_o = 4'd0;
+reg [1:0] ddrphy_bitslip25_value = 2'd0;
+reg [7:0] ddrphy_bitslip25_r = 8'd0;
+reg [3:0] ddrphy_dq_i_bitslip_o_d25 = 4'd0;
+wire ddrphy_dq_o26;
+wire ddrphy_dq_i26;
+wire ddrphy_dq_oe_n26;
+wire ddrphy_dq_i_delayed26;
+wire [7:0] ddrphy_dq_i_data26;
+reg [7:0] ddrphy_dq_o_data26 = 8'd0;
+reg [7:0] ddrphy_dq_o_data_d26 = 8'd0;
+reg [3:0] ddrphy_dq_o_data_muxed26 = 4'd0;
+wire [3:0] ddrphy_bitslip26_i;
+reg [3:0] ddrphy_bitslip26_o = 4'd0;
+reg [1:0] ddrphy_bitslip26_value = 2'd0;
+reg [7:0] ddrphy_bitslip26_r = 8'd0;
+reg [3:0] ddrphy_dq_i_bitslip_o_d26 = 4'd0;
+wire ddrphy_dq_o27;
+wire ddrphy_dq_i27;
+wire ddrphy_dq_oe_n27;
+wire ddrphy_dq_i_delayed27;
+wire [7:0] ddrphy_dq_i_data27;
+reg [7:0] ddrphy_dq_o_data27 = 8'd0;
+reg [7:0] ddrphy_dq_o_data_d27 = 8'd0;
+reg [3:0] ddrphy_dq_o_data_muxed27 = 4'd0;
+wire [3:0] ddrphy_bitslip27_i;
+reg [3:0] ddrphy_bitslip27_o = 4'd0;
+reg [1:0] ddrphy_bitslip27_value = 2'd0;
+reg [7:0] ddrphy_bitslip27_r = 8'd0;
+reg [3:0] ddrphy_dq_i_bitslip_o_d27 = 4'd0;
+wire ddrphy_dq_o28;
+wire ddrphy_dq_i28;
+wire ddrphy_dq_oe_n28;
+wire ddrphy_dq_i_delayed28;
+wire [7:0] ddrphy_dq_i_data28;
+reg [7:0] ddrphy_dq_o_data28 = 8'd0;
+reg [7:0] ddrphy_dq_o_data_d28 = 8'd0;
+reg [3:0] ddrphy_dq_o_data_muxed28 = 4'd0;
+wire [3:0] ddrphy_bitslip28_i;
+reg [3:0] ddrphy_bitslip28_o = 4'd0;
+reg [1:0] ddrphy_bitslip28_value = 2'd0;
+reg [7:0] ddrphy_bitslip28_r = 8'd0;
+reg [3:0] ddrphy_dq_i_bitslip_o_d28 = 4'd0;
+wire ddrphy_dq_o29;
+wire ddrphy_dq_i29;
+wire ddrphy_dq_oe_n29;
+wire ddrphy_dq_i_delayed29;
+wire [7:0] ddrphy_dq_i_data29;
+reg [7:0] ddrphy_dq_o_data29 = 8'd0;
+reg [7:0] ddrphy_dq_o_data_d29 = 8'd0;
+reg [3:0] ddrphy_dq_o_data_muxed29 = 4'd0;
+wire [3:0] ddrphy_bitslip29_i;
+reg [3:0] ddrphy_bitslip29_o = 4'd0;
+reg [1:0] ddrphy_bitslip29_value = 2'd0;
+reg [7:0] ddrphy_bitslip29_r = 8'd0;
+reg [3:0] ddrphy_dq_i_bitslip_o_d29 = 4'd0;
+wire ddrphy_dq_o30;
+wire ddrphy_dq_i30;
+wire ddrphy_dq_oe_n30;
+wire ddrphy_dq_i_delayed30;
+wire [7:0] ddrphy_dq_i_data30;
+reg [7:0] ddrphy_dq_o_data30 = 8'd0;
+reg [7:0] ddrphy_dq_o_data_d30 = 8'd0;
+reg [3:0] ddrphy_dq_o_data_muxed30 = 4'd0;
+wire [3:0] ddrphy_bitslip30_i;
+reg [3:0] ddrphy_bitslip30_o = 4'd0;
+reg [1:0] ddrphy_bitslip30_value = 2'd0;
+reg [7:0] ddrphy_bitslip30_r = 8'd0;
+reg [3:0] ddrphy_dq_i_bitslip_o_d30 = 4'd0;
+wire ddrphy_dq_o31;
+wire ddrphy_dq_i31;
+wire ddrphy_dq_oe_n31;
+wire ddrphy_dq_i_delayed31;
+wire [7:0] ddrphy_dq_i_data31;
+reg [7:0] ddrphy_dq_o_data31 = 8'd0;
+reg [7:0] ddrphy_dq_o_data_d31 = 8'd0;
+reg [3:0] ddrphy_dq_o_data_muxed31 = 4'd0;
+wire [3:0] ddrphy_bitslip31_i;
+reg [3:0] ddrphy_bitslip31_o = 4'd0;
+reg [1:0] ddrphy_bitslip31_value = 2'd0;
+reg [7:0] ddrphy_bitslip31_r = 8'd0;
+reg [3:0] ddrphy_dq_i_bitslip_o_d31 = 4'd0;
+reg ddrphy_rddata_en_tappeddelayline0 = 1'd0;
+reg ddrphy_rddata_en_tappeddelayline1 = 1'd0;
+reg ddrphy_rddata_en_tappeddelayline2 = 1'd0;
+reg ddrphy_rddata_en_tappeddelayline3 = 1'd0;
+reg ddrphy_rddata_en_tappeddelayline4 = 1'd0;
+reg ddrphy_rddata_en_tappeddelayline5 = 1'd0;
+reg ddrphy_rddata_en_tappeddelayline6 = 1'd0;
+reg ddrphy_rddata_en_tappeddelayline7 = 1'd0;
+reg ddrphy_rddata_en_tappeddelayline8 = 1'd0;
+reg ddrphy_rddata_en_tappeddelayline9 = 1'd0;
+reg ddrphy_rddata_en_tappeddelayline10 = 1'd0;
+reg ddrphy_rddata_en_tappeddelayline11 = 1'd0;
+reg ddrphy_rddata_en_tappeddelayline12 = 1'd0;
+reg ddrphy_wrdata_en_tappeddelayline0 = 1'd0;
+reg ddrphy_wrdata_en_tappeddelayline1 = 1'd0;
+reg ddrphy_wrdata_en_tappeddelayline2 = 1'd0;
+reg ddrphy_wrdata_en_tappeddelayline3 = 1'd0;
+reg ddrphy_wrdata_en_tappeddelayline4 = 1'd0;
+reg ddrphy_wrdata_en_tappeddelayline5 = 1'd0;
+reg ddrphy_wrdata_en_tappeddelayline6 = 1'd0;
+wire [14:0] litedramcore_inti_p0_address;
+wire [2:0] litedramcore_inti_p0_bank;
+reg litedramcore_inti_p0_cas_n = 1'd1;
+reg litedramcore_inti_p0_cs_n = 1'd1;
+reg litedramcore_inti_p0_ras_n = 1'd1;
+reg litedramcore_inti_p0_we_n = 1'd1;
+wire litedramcore_inti_p0_cke;
+wire litedramcore_inti_p0_odt;
+wire litedramcore_inti_p0_reset_n;
+reg litedramcore_inti_p0_act_n = 1'd1;
+wire [127:0] litedramcore_inti_p0_wrdata;
+wire litedramcore_inti_p0_wrdata_en;
+wire [15:0] litedramcore_inti_p0_wrdata_mask;
+wire litedramcore_inti_p0_rddata_en;
+reg [127:0] litedramcore_inti_p0_rddata = 128'd0;
+reg litedramcore_inti_p0_rddata_valid = 1'd0;
+wire [14:0] litedramcore_inti_p1_address;
+wire [2:0] litedramcore_inti_p1_bank;
+reg litedramcore_inti_p1_cas_n = 1'd1;
+reg litedramcore_inti_p1_cs_n = 1'd1;
+reg litedramcore_inti_p1_ras_n = 1'd1;
+reg litedramcore_inti_p1_we_n = 1'd1;
+wire litedramcore_inti_p1_cke;
+wire litedramcore_inti_p1_odt;
+wire litedramcore_inti_p1_reset_n;
+reg litedramcore_inti_p1_act_n = 1'd1;
+wire [127:0] litedramcore_inti_p1_wrdata;
+wire litedramcore_inti_p1_wrdata_en;
+wire [15:0] litedramcore_inti_p1_wrdata_mask;
+wire litedramcore_inti_p1_rddata_en;
+reg [127:0] litedramcore_inti_p1_rddata = 128'd0;
+reg litedramcore_inti_p1_rddata_valid = 1'd0;
+wire [14:0] litedramcore_slave_p0_address;
+wire [2:0] litedramcore_slave_p0_bank;
+wire litedramcore_slave_p0_cas_n;
+wire litedramcore_slave_p0_cs_n;
+wire litedramcore_slave_p0_ras_n;
+wire litedramcore_slave_p0_we_n;
+wire litedramcore_slave_p0_cke;
+wire litedramcore_slave_p0_odt;
+wire litedramcore_slave_p0_reset_n;
+wire litedramcore_slave_p0_act_n;
+wire [127:0] litedramcore_slave_p0_wrdata;
+wire litedramcore_slave_p0_wrdata_en;
+wire [15:0] litedramcore_slave_p0_wrdata_mask;
+wire litedramcore_slave_p0_rddata_en;
+reg [127:0] litedramcore_slave_p0_rddata = 128'd0;
+reg litedramcore_slave_p0_rddata_valid = 1'd0;
+wire [14:0] litedramcore_slave_p1_address;
+wire [2:0] litedramcore_slave_p1_bank;
+wire litedramcore_slave_p1_cas_n;
+wire litedramcore_slave_p1_cs_n;
+wire litedramcore_slave_p1_ras_n;
+wire litedramcore_slave_p1_we_n;
+wire litedramcore_slave_p1_cke;
+wire litedramcore_slave_p1_odt;
+wire litedramcore_slave_p1_reset_n;
+wire litedramcore_slave_p1_act_n;
+wire [127:0] litedramcore_slave_p1_wrdata;
+wire litedramcore_slave_p1_wrdata_en;
+wire [15:0] litedramcore_slave_p1_wrdata_mask;
+wire litedramcore_slave_p1_rddata_en;
+reg [127:0] litedramcore_slave_p1_rddata = 128'd0;
+reg litedramcore_slave_p1_rddata_valid = 1'd0;
+reg [14:0] litedramcore_master_p0_address = 15'd0;
+reg [2:0] litedramcore_master_p0_bank = 3'd0;
+reg litedramcore_master_p0_cas_n = 1'd1;
+reg litedramcore_master_p0_cs_n = 1'd1;
+reg litedramcore_master_p0_ras_n = 1'd1;
+reg litedramcore_master_p0_we_n = 1'd1;
+reg litedramcore_master_p0_cke = 1'd0;
+reg litedramcore_master_p0_odt = 1'd0;
+reg litedramcore_master_p0_reset_n = 1'd0;
+reg litedramcore_master_p0_act_n = 1'd1;
+reg [127:0] litedramcore_master_p0_wrdata = 128'd0;
+reg litedramcore_master_p0_wrdata_en = 1'd0;
+reg [15:0] litedramcore_master_p0_wrdata_mask = 16'd0;
+reg litedramcore_master_p0_rddata_en = 1'd0;
+wire [127:0] litedramcore_master_p0_rddata;
+wire litedramcore_master_p0_rddata_valid;
+reg [14:0] litedramcore_master_p1_address = 15'd0;
+reg [2:0] litedramcore_master_p1_bank = 3'd0;
+reg litedramcore_master_p1_cas_n = 1'd1;
+reg litedramcore_master_p1_cs_n = 1'd1;
+reg litedramcore_master_p1_ras_n = 1'd1;
+reg litedramcore_master_p1_we_n = 1'd1;
+reg litedramcore_master_p1_cke = 1'd0;
+reg litedramcore_master_p1_odt = 1'd0;
+reg litedramcore_master_p1_reset_n = 1'd0;
+reg litedramcore_master_p1_act_n = 1'd1;
+reg [127:0] litedramcore_master_p1_wrdata = 128'd0;
+reg litedramcore_master_p1_wrdata_en = 1'd0;
+reg [15:0] litedramcore_master_p1_wrdata_mask = 16'd0;
+reg litedramcore_master_p1_rddata_en = 1'd0;
+wire [127:0] litedramcore_master_p1_rddata;
+wire litedramcore_master_p1_rddata_valid;
+wire litedramcore_sel;
+wire litedramcore_cke;
+wire litedramcore_odt;
+wire litedramcore_reset_n;
+reg [3:0] litedramcore_storage = 4'd1;
+reg litedramcore_re = 1'd0;
+reg [5:0] litedramcore_phaseinjector0_command_storage = 6'd0;
+reg litedramcore_phaseinjector0_command_re = 1'd0;
+reg litedramcore_phaseinjector0_command_issue_re = 1'd0;
+wire litedramcore_phaseinjector0_command_issue_r;
+reg litedramcore_phaseinjector0_command_issue_we = 1'd0;
+reg litedramcore_phaseinjector0_command_issue_w = 1'd0;
+reg [14:0] litedramcore_phaseinjector0_address_storage = 15'd0;
+reg litedramcore_phaseinjector0_address_re = 1'd0;
+reg [2:0] litedramcore_phaseinjector0_baddress_storage = 3'd0;
+reg litedramcore_phaseinjector0_baddress_re = 1'd0;
+reg [127:0] litedramcore_phaseinjector0_wrdata_storage = 128'd0;
+reg litedramcore_phaseinjector0_wrdata_re = 1'd0;
+reg [127:0] litedramcore_phaseinjector0_rddata_status = 128'd0;
+wire litedramcore_phaseinjector0_rddata_we;
+reg litedramcore_phaseinjector0_rddata_re = 1'd0;
+reg [5:0] litedramcore_phaseinjector1_command_storage = 6'd0;
+reg litedramcore_phaseinjector1_command_re = 1'd0;
+reg litedramcore_phaseinjector1_command_issue_re = 1'd0;
+wire litedramcore_phaseinjector1_command_issue_r;
+reg litedramcore_phaseinjector1_command_issue_we = 1'd0;
+reg litedramcore_phaseinjector1_command_issue_w = 1'd0;
+reg [14:0] litedramcore_phaseinjector1_address_storage = 15'd0;
+reg litedramcore_phaseinjector1_address_re = 1'd0;
+reg [2:0] litedramcore_phaseinjector1_baddress_storage = 3'd0;
+reg litedramcore_phaseinjector1_baddress_re = 1'd0;
+reg [127:0] litedramcore_phaseinjector1_wrdata_storage = 128'd0;
+reg litedramcore_phaseinjector1_wrdata_re = 1'd0;
+reg [127:0] litedramcore_phaseinjector1_rddata_status = 128'd0;
+wire litedramcore_phaseinjector1_rddata_we;
+reg litedramcore_phaseinjector1_rddata_re = 1'd0;
+wire litedramcore_interface_bank0_valid;
+wire litedramcore_interface_bank0_ready;
+wire litedramcore_interface_bank0_we;
+wire [21:0] litedramcore_interface_bank0_addr;
+wire litedramcore_interface_bank0_lock;
+wire litedramcore_interface_bank0_wdata_ready;
+wire litedramcore_interface_bank0_rdata_valid;
+wire litedramcore_interface_bank1_valid;
+wire litedramcore_interface_bank1_ready;
+wire litedramcore_interface_bank1_we;
+wire [21:0] litedramcore_interface_bank1_addr;
+wire litedramcore_interface_bank1_lock;
+wire litedramcore_interface_bank1_wdata_ready;
+wire litedramcore_interface_bank1_rdata_valid;
+wire litedramcore_interface_bank2_valid;
+wire litedramcore_interface_bank2_ready;
+wire litedramcore_interface_bank2_we;
+wire [21:0] litedramcore_interface_bank2_addr;
+wire litedramcore_interface_bank2_lock;
+wire litedramcore_interface_bank2_wdata_ready;
+wire litedramcore_interface_bank2_rdata_valid;
+wire litedramcore_interface_bank3_valid;
+wire litedramcore_interface_bank3_ready;
+wire litedramcore_interface_bank3_we;
+wire [21:0] litedramcore_interface_bank3_addr;
+wire litedramcore_interface_bank3_lock;
+wire litedramcore_interface_bank3_wdata_ready;
+wire litedramcore_interface_bank3_rdata_valid;
+wire litedramcore_interface_bank4_valid;
+wire litedramcore_interface_bank4_ready;
+wire litedramcore_interface_bank4_we;
+wire [21:0] litedramcore_interface_bank4_addr;
+wire litedramcore_interface_bank4_lock;
+wire litedramcore_interface_bank4_wdata_ready;
+wire litedramcore_interface_bank4_rdata_valid;
+wire litedramcore_interface_bank5_valid;
+wire litedramcore_interface_bank5_ready;
+wire litedramcore_interface_bank5_we;
+wire [21:0] litedramcore_interface_bank5_addr;
+wire litedramcore_interface_bank5_lock;
+wire litedramcore_interface_bank5_wdata_ready;
+wire litedramcore_interface_bank5_rdata_valid;
+wire litedramcore_interface_bank6_valid;
+wire litedramcore_interface_bank6_ready;
+wire litedramcore_interface_bank6_we;
+wire [21:0] litedramcore_interface_bank6_addr;
+wire litedramcore_interface_bank6_lock;
+wire litedramcore_interface_bank6_wdata_ready;
+wire litedramcore_interface_bank6_rdata_valid;
+wire litedramcore_interface_bank7_valid;
+wire litedramcore_interface_bank7_ready;
+wire litedramcore_interface_bank7_we;
+wire [21:0] litedramcore_interface_bank7_addr;
+wire litedramcore_interface_bank7_lock;
+wire litedramcore_interface_bank7_wdata_ready;
+wire litedramcore_interface_bank7_rdata_valid;
+reg [255:0] litedramcore_interface_wdata = 256'd0;
+reg [31:0] litedramcore_interface_wdata_we = 32'd0;
+wire [255:0] litedramcore_interface_rdata;
+reg [14:0] litedramcore_dfi_p0_address = 15'd0;
+reg [2:0] litedramcore_dfi_p0_bank = 3'd0;
+reg litedramcore_dfi_p0_cas_n = 1'd1;
+reg litedramcore_dfi_p0_cs_n = 1'd1;
+reg litedramcore_dfi_p0_ras_n = 1'd1;
+reg litedramcore_dfi_p0_we_n = 1'd1;
+wire litedramcore_dfi_p0_cke;
+wire litedramcore_dfi_p0_odt;
+wire litedramcore_dfi_p0_reset_n;
+reg litedramcore_dfi_p0_act_n = 1'd1;
+wire [127:0] litedramcore_dfi_p0_wrdata;
+reg litedramcore_dfi_p0_wrdata_en = 1'd0;
+wire [15:0] litedramcore_dfi_p0_wrdata_mask;
+reg litedramcore_dfi_p0_rddata_en = 1'd0;
+wire [127:0] litedramcore_dfi_p0_rddata;
+wire litedramcore_dfi_p0_rddata_valid;
+reg [14:0] litedramcore_dfi_p1_address = 15'd0;
+reg [2:0] litedramcore_dfi_p1_bank = 3'd0;
+reg litedramcore_dfi_p1_cas_n = 1'd1;
+reg litedramcore_dfi_p1_cs_n = 1'd1;
+reg litedramcore_dfi_p1_ras_n = 1'd1;
+reg litedramcore_dfi_p1_we_n = 1'd1;
+wire litedramcore_dfi_p1_cke;
+wire litedramcore_dfi_p1_odt;
+wire litedramcore_dfi_p1_reset_n;
+reg litedramcore_dfi_p1_act_n = 1'd1;
+wire [127:0] litedramcore_dfi_p1_wrdata;
+reg litedramcore_dfi_p1_wrdata_en = 1'd0;
+wire [15:0] litedramcore_dfi_p1_wrdata_mask;
+reg litedramcore_dfi_p1_rddata_en = 1'd0;
+wire [127:0] litedramcore_dfi_p1_rddata;
+wire litedramcore_dfi_p1_rddata_valid;
+reg litedramcore_cmd_valid = 1'd0;
+reg litedramcore_cmd_ready = 1'd0;
+reg litedramcore_cmd_last = 1'd0;
+reg [14:0] litedramcore_cmd_payload_a = 15'd0;
+reg [2:0] litedramcore_cmd_payload_ba = 3'd0;
+reg litedramcore_cmd_payload_cas = 1'd0;
+reg litedramcore_cmd_payload_ras = 1'd0;
+reg litedramcore_cmd_payload_we = 1'd0;
+reg litedramcore_cmd_payload_is_read = 1'd0;
+reg litedramcore_cmd_payload_is_write = 1'd0;
+wire litedramcore_wants_refresh;
+wire litedramcore_wants_zqcs;
+wire litedramcore_timer_wait;
+wire litedramcore_timer_done0;
+wire [8:0] litedramcore_timer_count0;
+wire litedramcore_timer_done1;
+reg [8:0] litedramcore_timer_count1 = 9'd374;
+wire litedramcore_postponer_req_i;
+reg litedramcore_postponer_req_o = 1'd0;
+reg litedramcore_postponer_count = 1'd0;
+reg litedramcore_sequencer_start0 = 1'd0;
+wire litedramcore_sequencer_done0;
+wire litedramcore_sequencer_start1;
+reg litedramcore_sequencer_done1 = 1'd0;
+reg [6:0] litedramcore_sequencer_counter = 7'd0;
+reg litedramcore_sequencer_count = 1'd0;
+wire litedramcore_zqcs_timer_wait;
+wire litedramcore_zqcs_timer_done0;
+wire [25:0] litedramcore_zqcs_timer_count0;
+wire litedramcore_zqcs_timer_done1;
+reg [25:0] litedramcore_zqcs_timer_count1 = 26'd47999999;
+reg litedramcore_zqcs_executer_start = 1'd0;
+reg litedramcore_zqcs_executer_done = 1'd0;
+reg [5:0] litedramcore_zqcs_executer_counter = 6'd0;
+wire litedramcore_bankmachine0_req_valid;
+wire litedramcore_bankmachine0_req_ready;
+wire litedramcore_bankmachine0_req_we;
+wire [21:0] litedramcore_bankmachine0_req_addr;
+wire litedramcore_bankmachine0_req_lock;
+reg litedramcore_bankmachine0_req_wdata_ready = 1'd0;
+reg litedramcore_bankmachine0_req_rdata_valid = 1'd0;
+wire litedramcore_bankmachine0_refresh_req;
+reg litedramcore_bankmachine0_refresh_gnt = 1'd0;
+reg litedramcore_bankmachine0_cmd_valid = 1'd0;
+reg litedramcore_bankmachine0_cmd_ready = 1'd0;
+reg [14:0] litedramcore_bankmachine0_cmd_payload_a = 15'd0;
+wire [2:0] litedramcore_bankmachine0_cmd_payload_ba;
+reg litedramcore_bankmachine0_cmd_payload_cas = 1'd0;
+reg litedramcore_bankmachine0_cmd_payload_ras = 1'd0;
+reg litedramcore_bankmachine0_cmd_payload_we = 1'd0;
+reg litedramcore_bankmachine0_cmd_payload_is_cmd = 1'd0;
+reg litedramcore_bankmachine0_cmd_payload_is_read = 1'd0;
+reg litedramcore_bankmachine0_cmd_payload_is_write = 1'd0;
+reg litedramcore_bankmachine0_auto_precharge = 1'd0;
+wire litedramcore_bankmachine0_cmd_buffer_lookahead_sink_valid;
+wire litedramcore_bankmachine0_cmd_buffer_lookahead_sink_ready;
+reg litedramcore_bankmachine0_cmd_buffer_lookahead_sink_first = 1'd0;
+reg litedramcore_bankmachine0_cmd_buffer_lookahead_sink_last = 1'd0;
+wire litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_we;
+wire [21:0] litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_addr;
+wire litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid;
+wire litedramcore_bankmachine0_cmd_buffer_lookahead_source_ready;
+wire litedramcore_bankmachine0_cmd_buffer_lookahead_source_first;
+wire litedramcore_bankmachine0_cmd_buffer_lookahead_source_last;
+wire litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_we;
+wire [21:0] litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr;
+wire litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we;
+wire litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable;
+wire litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_re;
+wire litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable;
+wire [24:0] litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din;
+wire [24:0] litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
+reg [4:0] litedramcore_bankmachine0_cmd_buffer_lookahead_level = 5'd0;
+reg litedramcore_bankmachine0_cmd_buffer_lookahead_replace = 1'd0;
+reg [3:0] litedramcore_bankmachine0_cmd_buffer_lookahead_produce = 4'd0;
+reg [3:0] litedramcore_bankmachine0_cmd_buffer_lookahead_consume = 4'd0;
+reg [3:0] litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr = 4'd0;
+wire [24:0] litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_r;
+wire litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we;
+wire [24:0] litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w;
+wire litedramcore_bankmachine0_cmd_buffer_lookahead_do_read;
+wire [3:0] litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_adr;
+wire [24:0] litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_dat_r;
+wire litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we;
+wire [21:0] litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr;
+wire litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_first;
+wire litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_last;
+wire litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we;
+wire [21:0] litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr;
+wire litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first;
+wire litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last;
+wire litedramcore_bankmachine0_cmd_buffer_sink_valid;
+wire litedramcore_bankmachine0_cmd_buffer_sink_ready;
+wire litedramcore_bankmachine0_cmd_buffer_sink_first;
+wire litedramcore_bankmachine0_cmd_buffer_sink_last;
+wire litedramcore_bankmachine0_cmd_buffer_sink_payload_we;
+wire [21:0] litedramcore_bankmachine0_cmd_buffer_sink_payload_addr;
+reg litedramcore_bankmachine0_cmd_buffer_source_valid = 1'd0;
+wire litedramcore_bankmachine0_cmd_buffer_source_ready;
+reg litedramcore_bankmachine0_cmd_buffer_source_first = 1'd0;
+reg litedramcore_bankmachine0_cmd_buffer_source_last = 1'd0;
+reg litedramcore_bankmachine0_cmd_buffer_source_payload_we = 1'd0;
+reg [21:0] litedramcore_bankmachine0_cmd_buffer_source_payload_addr = 22'd0;
+reg [14:0] litedramcore_bankmachine0_row = 15'd0;
+reg litedramcore_bankmachine0_row_opened = 1'd0;
+wire litedramcore_bankmachine0_row_hit;
+reg litedramcore_bankmachine0_row_open = 1'd0;
+reg litedramcore_bankmachine0_row_close = 1'd0;
+reg litedramcore_bankmachine0_row_col_n_addr_sel = 1'd0;
+wire litedramcore_bankmachine0_twtpcon_valid;
+reg litedramcore_bankmachine0_twtpcon_ready = 1'd0;
+reg [2:0] litedramcore_bankmachine0_twtpcon_count = 3'd0;
+wire litedramcore_bankmachine0_trccon_valid;
+reg litedramcore_bankmachine0_trccon_ready = 1'd0;
+reg [1:0] litedramcore_bankmachine0_trccon_count = 2'd0;
+wire litedramcore_bankmachine0_trascon_valid;
+reg litedramcore_bankmachine0_trascon_ready = 1'd0;
+reg [1:0] litedramcore_bankmachine0_trascon_count = 2'd0;
+wire litedramcore_bankmachine1_req_valid;
+wire litedramcore_bankmachine1_req_ready;
+wire litedramcore_bankmachine1_req_we;
+wire [21:0] litedramcore_bankmachine1_req_addr;
+wire litedramcore_bankmachine1_req_lock;
+reg litedramcore_bankmachine1_req_wdata_ready = 1'd0;
+reg litedramcore_bankmachine1_req_rdata_valid = 1'd0;
+wire litedramcore_bankmachine1_refresh_req;
+reg litedramcore_bankmachine1_refresh_gnt = 1'd0;
+reg litedramcore_bankmachine1_cmd_valid = 1'd0;
+reg litedramcore_bankmachine1_cmd_ready = 1'd0;
+reg [14:0] litedramcore_bankmachine1_cmd_payload_a = 15'd0;
+wire [2:0] litedramcore_bankmachine1_cmd_payload_ba;
+reg litedramcore_bankmachine1_cmd_payload_cas = 1'd0;
+reg litedramcore_bankmachine1_cmd_payload_ras = 1'd0;
+reg litedramcore_bankmachine1_cmd_payload_we = 1'd0;
+reg litedramcore_bankmachine1_cmd_payload_is_cmd = 1'd0;
+reg litedramcore_bankmachine1_cmd_payload_is_read = 1'd0;
+reg litedramcore_bankmachine1_cmd_payload_is_write = 1'd0;
+reg litedramcore_bankmachine1_auto_precharge = 1'd0;
+wire litedramcore_bankmachine1_cmd_buffer_lookahead_sink_valid;
+wire litedramcore_bankmachine1_cmd_buffer_lookahead_sink_ready;
+reg litedramcore_bankmachine1_cmd_buffer_lookahead_sink_first = 1'd0;
+reg litedramcore_bankmachine1_cmd_buffer_lookahead_sink_last = 1'd0;
+wire litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_we;
+wire [21:0] litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_addr;
+wire litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid;
+wire litedramcore_bankmachine1_cmd_buffer_lookahead_source_ready;
+wire litedramcore_bankmachine1_cmd_buffer_lookahead_source_first;
+wire litedramcore_bankmachine1_cmd_buffer_lookahead_source_last;
+wire litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_we;
+wire [21:0] litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr;
+wire litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we;
+wire litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable;
+wire litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_re;
+wire litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable;
+wire [24:0] litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din;
+wire [24:0] litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
+reg [4:0] litedramcore_bankmachine1_cmd_buffer_lookahead_level = 5'd0;
+reg litedramcore_bankmachine1_cmd_buffer_lookahead_replace = 1'd0;
+reg [3:0] litedramcore_bankmachine1_cmd_buffer_lookahead_produce = 4'd0;
+reg [3:0] litedramcore_bankmachine1_cmd_buffer_lookahead_consume = 4'd0;
+reg [3:0] litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr = 4'd0;
+wire [24:0] litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_r;
+wire litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we;
+wire [24:0] litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w;
+wire litedramcore_bankmachine1_cmd_buffer_lookahead_do_read;
+wire [3:0] litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_adr;
+wire [24:0] litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_dat_r;
+wire litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we;
+wire [21:0] litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr;
+wire litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_first;
+wire litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_last;
+wire litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we;
+wire [21:0] litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr;
+wire litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first;
+wire litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last;
+wire litedramcore_bankmachine1_cmd_buffer_sink_valid;
+wire litedramcore_bankmachine1_cmd_buffer_sink_ready;
+wire litedramcore_bankmachine1_cmd_buffer_sink_first;
+wire litedramcore_bankmachine1_cmd_buffer_sink_last;
+wire litedramcore_bankmachine1_cmd_buffer_sink_payload_we;
+wire [21:0] litedramcore_bankmachine1_cmd_buffer_sink_payload_addr;
+reg litedramcore_bankmachine1_cmd_buffer_source_valid = 1'd0;
+wire litedramcore_bankmachine1_cmd_buffer_source_ready;
+reg litedramcore_bankmachine1_cmd_buffer_source_first = 1'd0;
+reg litedramcore_bankmachine1_cmd_buffer_source_last = 1'd0;
+reg litedramcore_bankmachine1_cmd_buffer_source_payload_we = 1'd0;
+reg [21:0] litedramcore_bankmachine1_cmd_buffer_source_payload_addr = 22'd0;
+reg [14:0] litedramcore_bankmachine1_row = 15'd0;
+reg litedramcore_bankmachine1_row_opened = 1'd0;
+wire litedramcore_bankmachine1_row_hit;
+reg litedramcore_bankmachine1_row_open = 1'd0;
+reg litedramcore_bankmachine1_row_close = 1'd0;
+reg litedramcore_bankmachine1_row_col_n_addr_sel = 1'd0;
+wire litedramcore_bankmachine1_twtpcon_valid;
+reg litedramcore_bankmachine1_twtpcon_ready = 1'd0;
+reg [2:0] litedramcore_bankmachine1_twtpcon_count = 3'd0;
+wire litedramcore_bankmachine1_trccon_valid;
+reg litedramcore_bankmachine1_trccon_ready = 1'd0;
+reg [1:0] litedramcore_bankmachine1_trccon_count = 2'd0;
+wire litedramcore_bankmachine1_trascon_valid;
+reg litedramcore_bankmachine1_trascon_ready = 1'd0;
+reg [1:0] litedramcore_bankmachine1_trascon_count = 2'd0;
+wire litedramcore_bankmachine2_req_valid;
+wire litedramcore_bankmachine2_req_ready;
+wire litedramcore_bankmachine2_req_we;
+wire [21:0] litedramcore_bankmachine2_req_addr;
+wire litedramcore_bankmachine2_req_lock;
+reg litedramcore_bankmachine2_req_wdata_ready = 1'd0;
+reg litedramcore_bankmachine2_req_rdata_valid = 1'd0;
+wire litedramcore_bankmachine2_refresh_req;
+reg litedramcore_bankmachine2_refresh_gnt = 1'd0;
+reg litedramcore_bankmachine2_cmd_valid = 1'd0;
+reg litedramcore_bankmachine2_cmd_ready = 1'd0;
+reg [14:0] litedramcore_bankmachine2_cmd_payload_a = 15'd0;
+wire [2:0] litedramcore_bankmachine2_cmd_payload_ba;
+reg litedramcore_bankmachine2_cmd_payload_cas = 1'd0;
+reg litedramcore_bankmachine2_cmd_payload_ras = 1'd0;
+reg litedramcore_bankmachine2_cmd_payload_we = 1'd0;
+reg litedramcore_bankmachine2_cmd_payload_is_cmd = 1'd0;
+reg litedramcore_bankmachine2_cmd_payload_is_read = 1'd0;
+reg litedramcore_bankmachine2_cmd_payload_is_write = 1'd0;
+reg litedramcore_bankmachine2_auto_precharge = 1'd0;
+wire litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid;
+wire litedramcore_bankmachine2_cmd_buffer_lookahead_sink_ready;
+reg litedramcore_bankmachine2_cmd_buffer_lookahead_sink_first = 1'd0;
+reg litedramcore_bankmachine2_cmd_buffer_lookahead_sink_last = 1'd0;
+wire litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_we;
+wire [21:0] litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_addr;
+wire litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid;
+wire litedramcore_bankmachine2_cmd_buffer_lookahead_source_ready;
+wire litedramcore_bankmachine2_cmd_buffer_lookahead_source_first;
+wire litedramcore_bankmachine2_cmd_buffer_lookahead_source_last;
+wire litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_we;
+wire [21:0] litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr;
+wire litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we;
+wire litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable;
+wire litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_re;
+wire litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable;
+wire [24:0] litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din;
+wire [24:0] litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
+reg [4:0] litedramcore_bankmachine2_cmd_buffer_lookahead_level = 5'd0;
+reg litedramcore_bankmachine2_cmd_buffer_lookahead_replace = 1'd0;
+reg [3:0] litedramcore_bankmachine2_cmd_buffer_lookahead_produce = 4'd0;
+reg [3:0] litedramcore_bankmachine2_cmd_buffer_lookahead_consume = 4'd0;
+reg [3:0] litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr = 4'd0;
+wire [24:0] litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_r;
+wire litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we;
+wire [24:0] litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w;
+wire litedramcore_bankmachine2_cmd_buffer_lookahead_do_read;
+wire [3:0] litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_adr;
+wire [24:0] litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_dat_r;
+wire litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we;
+wire [21:0] litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr;
+wire litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_first;
+wire litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_last;
+wire litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we;
+wire [21:0] litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr;
+wire litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first;
+wire litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last;
+wire litedramcore_bankmachine2_cmd_buffer_sink_valid;
+wire litedramcore_bankmachine2_cmd_buffer_sink_ready;
+wire litedramcore_bankmachine2_cmd_buffer_sink_first;
+wire litedramcore_bankmachine2_cmd_buffer_sink_last;
+wire litedramcore_bankmachine2_cmd_buffer_sink_payload_we;
+wire [21:0] litedramcore_bankmachine2_cmd_buffer_sink_payload_addr;
+reg litedramcore_bankmachine2_cmd_buffer_source_valid = 1'd0;
+wire litedramcore_bankmachine2_cmd_buffer_source_ready;
+reg litedramcore_bankmachine2_cmd_buffer_source_first = 1'd0;
+reg litedramcore_bankmachine2_cmd_buffer_source_last = 1'd0;
+reg litedramcore_bankmachine2_cmd_buffer_source_payload_we = 1'd0;
+reg [21:0] litedramcore_bankmachine2_cmd_buffer_source_payload_addr = 22'd0;
+reg [14:0] litedramcore_bankmachine2_row = 15'd0;
+reg litedramcore_bankmachine2_row_opened = 1'd0;
+wire litedramcore_bankmachine2_row_hit;
+reg litedramcore_bankmachine2_row_open = 1'd0;
+reg litedramcore_bankmachine2_row_close = 1'd0;
+reg litedramcore_bankmachine2_row_col_n_addr_sel = 1'd0;
+wire litedramcore_bankmachine2_twtpcon_valid;
+reg litedramcore_bankmachine2_twtpcon_ready = 1'd0;
+reg [2:0] litedramcore_bankmachine2_twtpcon_count = 3'd0;
+wire litedramcore_bankmachine2_trccon_valid;
+reg litedramcore_bankmachine2_trccon_ready = 1'd0;
+reg [1:0] litedramcore_bankmachine2_trccon_count = 2'd0;
+wire litedramcore_bankmachine2_trascon_valid;
+reg litedramcore_bankmachine2_trascon_ready = 1'd0;
+reg [1:0] litedramcore_bankmachine2_trascon_count = 2'd0;
+wire litedramcore_bankmachine3_req_valid;
+wire litedramcore_bankmachine3_req_ready;
+wire litedramcore_bankmachine3_req_we;
+wire [21:0] litedramcore_bankmachine3_req_addr;
+wire litedramcore_bankmachine3_req_lock;
+reg litedramcore_bankmachine3_req_wdata_ready = 1'd0;
+reg litedramcore_bankmachine3_req_rdata_valid = 1'd0;
+wire litedramcore_bankmachine3_refresh_req;
+reg litedramcore_bankmachine3_refresh_gnt = 1'd0;
+reg litedramcore_bankmachine3_cmd_valid = 1'd0;
+reg litedramcore_bankmachine3_cmd_ready = 1'd0;
+reg [14:0] litedramcore_bankmachine3_cmd_payload_a = 15'd0;
+wire [2:0] litedramcore_bankmachine3_cmd_payload_ba;
+reg litedramcore_bankmachine3_cmd_payload_cas = 1'd0;
+reg litedramcore_bankmachine3_cmd_payload_ras = 1'd0;
+reg litedramcore_bankmachine3_cmd_payload_we = 1'd0;
+reg litedramcore_bankmachine3_cmd_payload_is_cmd = 1'd0;
+reg litedramcore_bankmachine3_cmd_payload_is_read = 1'd0;
+reg litedramcore_bankmachine3_cmd_payload_is_write = 1'd0;
+reg litedramcore_bankmachine3_auto_precharge = 1'd0;
+wire litedramcore_bankmachine3_cmd_buffer_lookahead_sink_valid;
+wire litedramcore_bankmachine3_cmd_buffer_lookahead_sink_ready;
+reg litedramcore_bankmachine3_cmd_buffer_lookahead_sink_first = 1'd0;
+reg litedramcore_bankmachine3_cmd_buffer_lookahead_sink_last = 1'd0;
+wire litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_we;
+wire [21:0] litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_addr;
+wire litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid;
+wire litedramcore_bankmachine3_cmd_buffer_lookahead_source_ready;
+wire litedramcore_bankmachine3_cmd_buffer_lookahead_source_first;
+wire litedramcore_bankmachine3_cmd_buffer_lookahead_source_last;
+wire litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_we;
+wire [21:0] litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr;
+wire litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we;
+wire litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable;
+wire litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_re;
+wire litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable;
+wire [24:0] litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din;
+wire [24:0] litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
+reg [4:0] litedramcore_bankmachine3_cmd_buffer_lookahead_level = 5'd0;
+reg litedramcore_bankmachine3_cmd_buffer_lookahead_replace = 1'd0;
+reg [3:0] litedramcore_bankmachine3_cmd_buffer_lookahead_produce = 4'd0;
+reg [3:0] litedramcore_bankmachine3_cmd_buffer_lookahead_consume = 4'd0;
+reg [3:0] litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr = 4'd0;
+wire [24:0] litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_r;
+wire litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we;
+wire [24:0] litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w;
+wire litedramcore_bankmachine3_cmd_buffer_lookahead_do_read;
+wire [3:0] litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_adr;
+wire [24:0] litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_dat_r;
+wire litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we;
+wire [21:0] litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr;
+wire litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_first;
+wire litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_last;
+wire litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we;
+wire [21:0] litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr;
+wire litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first;
+wire litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last;
+wire litedramcore_bankmachine3_cmd_buffer_sink_valid;
+wire litedramcore_bankmachine3_cmd_buffer_sink_ready;
+wire litedramcore_bankmachine3_cmd_buffer_sink_first;
+wire litedramcore_bankmachine3_cmd_buffer_sink_last;
+wire litedramcore_bankmachine3_cmd_buffer_sink_payload_we;
+wire [21:0] litedramcore_bankmachine3_cmd_buffer_sink_payload_addr;
+reg litedramcore_bankmachine3_cmd_buffer_source_valid = 1'd0;
+wire litedramcore_bankmachine3_cmd_buffer_source_ready;
+reg litedramcore_bankmachine3_cmd_buffer_source_first = 1'd0;
+reg litedramcore_bankmachine3_cmd_buffer_source_last = 1'd0;
+reg litedramcore_bankmachine3_cmd_buffer_source_payload_we = 1'd0;
+reg [21:0] litedramcore_bankmachine3_cmd_buffer_source_payload_addr = 22'd0;
+reg [14:0] litedramcore_bankmachine3_row = 15'd0;
+reg litedramcore_bankmachine3_row_opened = 1'd0;
+wire litedramcore_bankmachine3_row_hit;
+reg litedramcore_bankmachine3_row_open = 1'd0;
+reg litedramcore_bankmachine3_row_close = 1'd0;
+reg litedramcore_bankmachine3_row_col_n_addr_sel = 1'd0;
+wire litedramcore_bankmachine3_twtpcon_valid;
+reg litedramcore_bankmachine3_twtpcon_ready = 1'd0;
+reg [2:0] litedramcore_bankmachine3_twtpcon_count = 3'd0;
+wire litedramcore_bankmachine3_trccon_valid;
+reg litedramcore_bankmachine3_trccon_ready = 1'd0;
+reg [1:0] litedramcore_bankmachine3_trccon_count = 2'd0;
+wire litedramcore_bankmachine3_trascon_valid;
+reg litedramcore_bankmachine3_trascon_ready = 1'd0;
+reg [1:0] litedramcore_bankmachine3_trascon_count = 2'd0;
+wire litedramcore_bankmachine4_req_valid;
+wire litedramcore_bankmachine4_req_ready;
+wire litedramcore_bankmachine4_req_we;
+wire [21:0] litedramcore_bankmachine4_req_addr;
+wire litedramcore_bankmachine4_req_lock;
+reg litedramcore_bankmachine4_req_wdata_ready = 1'd0;
+reg litedramcore_bankmachine4_req_rdata_valid = 1'd0;
+wire litedramcore_bankmachine4_refresh_req;
+reg litedramcore_bankmachine4_refresh_gnt = 1'd0;
+reg litedramcore_bankmachine4_cmd_valid = 1'd0;
+reg litedramcore_bankmachine4_cmd_ready = 1'd0;
+reg [14:0] litedramcore_bankmachine4_cmd_payload_a = 15'd0;
+wire [2:0] litedramcore_bankmachine4_cmd_payload_ba;
+reg litedramcore_bankmachine4_cmd_payload_cas = 1'd0;
+reg litedramcore_bankmachine4_cmd_payload_ras = 1'd0;
+reg litedramcore_bankmachine4_cmd_payload_we = 1'd0;
+reg litedramcore_bankmachine4_cmd_payload_is_cmd = 1'd0;
+reg litedramcore_bankmachine4_cmd_payload_is_read = 1'd0;
+reg litedramcore_bankmachine4_cmd_payload_is_write = 1'd0;
+reg litedramcore_bankmachine4_auto_precharge = 1'd0;
+wire litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid;
+wire litedramcore_bankmachine4_cmd_buffer_lookahead_sink_ready;
+reg litedramcore_bankmachine4_cmd_buffer_lookahead_sink_first = 1'd0;
+reg litedramcore_bankmachine4_cmd_buffer_lookahead_sink_last = 1'd0;
+wire litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_we;
+wire [21:0] litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_addr;
+wire litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid;
+wire litedramcore_bankmachine4_cmd_buffer_lookahead_source_ready;
+wire litedramcore_bankmachine4_cmd_buffer_lookahead_source_first;
+wire litedramcore_bankmachine4_cmd_buffer_lookahead_source_last;
+wire litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_we;
+wire [21:0] litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr;
+wire litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we;
+wire litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable;
+wire litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_re;
+wire litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable;
+wire [24:0] litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din;
+wire [24:0] litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout;
+reg [4:0] litedramcore_bankmachine4_cmd_buffer_lookahead_level = 5'd0;
+reg litedramcore_bankmachine4_cmd_buffer_lookahead_replace = 1'd0;
+reg [3:0] litedramcore_bankmachine4_cmd_buffer_lookahead_produce = 4'd0;
+reg [3:0] litedramcore_bankmachine4_cmd_buffer_lookahead_consume = 4'd0;
+reg [3:0] litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr = 4'd0;
+wire [24:0] litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_r;
+wire litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we;
+wire [24:0] litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w;
+wire litedramcore_bankmachine4_cmd_buffer_lookahead_do_read;
+wire [3:0] litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_adr;
+wire [24:0] litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_dat_r;
+wire litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we;
+wire [21:0] litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr;
+wire litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_first;
+wire litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_last;
+wire litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we;
+wire [21:0] litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr;
+wire litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first;
+wire litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last;
+wire litedramcore_bankmachine4_cmd_buffer_sink_valid;
+wire litedramcore_bankmachine4_cmd_buffer_sink_ready;
+wire litedramcore_bankmachine4_cmd_buffer_sink_first;
+wire litedramcore_bankmachine4_cmd_buffer_sink_last;
+wire litedramcore_bankmachine4_cmd_buffer_sink_payload_we;
+wire [21:0] litedramcore_bankmachine4_cmd_buffer_sink_payload_addr;
+reg litedramcore_bankmachine4_cmd_buffer_source_valid = 1'd0;
+wire litedramcore_bankmachine4_cmd_buffer_source_ready;
+reg litedramcore_bankmachine4_cmd_buffer_source_first = 1'd0;
+reg litedramcore_bankmachine4_cmd_buffer_source_last = 1'd0;
+reg litedramcore_bankmachine4_cmd_buffer_source_payload_we = 1'd0;
+reg [21:0] litedramcore_bankmachine4_cmd_buffer_source_payload_addr = 22'd0;
+reg [14:0] litedramcore_bankmachine4_row = 15'd0;
+reg litedramcore_bankmachine4_row_opened = 1'd0;
+wire litedramcore_bankmachine4_row_hit;
+reg litedramcore_bankmachine4_row_open = 1'd0;
+reg litedramcore_bankmachine4_row_close = 1'd0;
+reg litedramcore_bankmachine4_row_col_n_addr_sel = 1'd0;
+wire litedramcore_bankmachine4_twtpcon_valid;
+reg litedramcore_bankmachine4_twtpcon_ready = 1'd0;
+reg [2:0] litedramcore_bankmachine4_twtpcon_count = 3'd0;
+wire litedramcore_bankmachine4_trccon_valid;
+reg litedramcore_bankmachine4_trccon_ready = 1'd0;
+reg [1:0] litedramcore_bankmachine4_trccon_count = 2'd0;
+wire litedramcore_bankmachine4_trascon_valid;
+reg litedramcore_bankmachine4_trascon_ready = 1'd0;
+reg [1:0] litedramcore_bankmachine4_trascon_count = 2'd0;
+wire litedramcore_bankmachine5_req_valid;
+wire litedramcore_bankmachine5_req_ready;
+wire litedramcore_bankmachine5_req_we;
+wire [21:0] litedramcore_bankmachine5_req_addr;
+wire litedramcore_bankmachine5_req_lock;
+reg litedramcore_bankmachine5_req_wdata_ready = 1'd0;
+reg litedramcore_bankmachine5_req_rdata_valid = 1'd0;
+wire litedramcore_bankmachine5_refresh_req;
+reg litedramcore_bankmachine5_refresh_gnt = 1'd0;
+reg litedramcore_bankmachine5_cmd_valid = 1'd0;
+reg litedramcore_bankmachine5_cmd_ready = 1'd0;
+reg [14:0] litedramcore_bankmachine5_cmd_payload_a = 15'd0;
+wire [2:0] litedramcore_bankmachine5_cmd_payload_ba;
+reg litedramcore_bankmachine5_cmd_payload_cas = 1'd0;
+reg litedramcore_bankmachine5_cmd_payload_ras = 1'd0;
+reg litedramcore_bankmachine5_cmd_payload_we = 1'd0;
+reg litedramcore_bankmachine5_cmd_payload_is_cmd = 1'd0;
+reg litedramcore_bankmachine5_cmd_payload_is_read = 1'd0;
+reg litedramcore_bankmachine5_cmd_payload_is_write = 1'd0;
+reg litedramcore_bankmachine5_auto_precharge = 1'd0;
+wire litedramcore_bankmachine5_cmd_buffer_lookahead_sink_valid;
+wire litedramcore_bankmachine5_cmd_buffer_lookahead_sink_ready;
+reg litedramcore_bankmachine5_cmd_buffer_lookahead_sink_first = 1'd0;
+reg litedramcore_bankmachine5_cmd_buffer_lookahead_sink_last = 1'd0;
+wire litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_we;
+wire [21:0] litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_addr;
+wire litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid;
+wire litedramcore_bankmachine5_cmd_buffer_lookahead_source_ready;
+wire litedramcore_bankmachine5_cmd_buffer_lookahead_source_first;
+wire litedramcore_bankmachine5_cmd_buffer_lookahead_source_last;
+wire litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_we;
+wire [21:0] litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr;
+wire litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we;
+wire litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable;
+wire litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_re;
+wire litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable;
+wire [24:0] litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din;
+wire [24:0] litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout;
+reg [4:0] litedramcore_bankmachine5_cmd_buffer_lookahead_level = 5'd0;
+reg litedramcore_bankmachine5_cmd_buffer_lookahead_replace = 1'd0;
+reg [3:0] litedramcore_bankmachine5_cmd_buffer_lookahead_produce = 4'd0;
+reg [3:0] litedramcore_bankmachine5_cmd_buffer_lookahead_consume = 4'd0;
+reg [3:0] litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr = 4'd0;
+wire [24:0] litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_r;
+wire litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we;
+wire [24:0] litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w;
+wire litedramcore_bankmachine5_cmd_buffer_lookahead_do_read;
+wire [3:0] litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_adr;
+wire [24:0] litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_dat_r;
+wire litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we;
+wire [21:0] litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr;
+wire litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_first;
+wire litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_last;
+wire litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we;
+wire [21:0] litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr;
+wire litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first;
+wire litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last;
+wire litedramcore_bankmachine5_cmd_buffer_sink_valid;
+wire litedramcore_bankmachine5_cmd_buffer_sink_ready;
+wire litedramcore_bankmachine5_cmd_buffer_sink_first;
+wire litedramcore_bankmachine5_cmd_buffer_sink_last;
+wire litedramcore_bankmachine5_cmd_buffer_sink_payload_we;
+wire [21:0] litedramcore_bankmachine5_cmd_buffer_sink_payload_addr;
+reg litedramcore_bankmachine5_cmd_buffer_source_valid = 1'd0;
+wire litedramcore_bankmachine5_cmd_buffer_source_ready;
+reg litedramcore_bankmachine5_cmd_buffer_source_first = 1'd0;
+reg litedramcore_bankmachine5_cmd_buffer_source_last = 1'd0;
+reg litedramcore_bankmachine5_cmd_buffer_source_payload_we = 1'd0;
+reg [21:0] litedramcore_bankmachine5_cmd_buffer_source_payload_addr = 22'd0;
+reg [14:0] litedramcore_bankmachine5_row = 15'd0;
+reg litedramcore_bankmachine5_row_opened = 1'd0;
+wire litedramcore_bankmachine5_row_hit;
+reg litedramcore_bankmachine5_row_open = 1'd0;
+reg litedramcore_bankmachine5_row_close = 1'd0;
+reg litedramcore_bankmachine5_row_col_n_addr_sel = 1'd0;
+wire litedramcore_bankmachine5_twtpcon_valid;
+reg litedramcore_bankmachine5_twtpcon_ready = 1'd0;
+reg [2:0] litedramcore_bankmachine5_twtpcon_count = 3'd0;
+wire litedramcore_bankmachine5_trccon_valid;
+reg litedramcore_bankmachine5_trccon_ready = 1'd0;
+reg [1:0] litedramcore_bankmachine5_trccon_count = 2'd0;
+wire litedramcore_bankmachine5_trascon_valid;
+reg litedramcore_bankmachine5_trascon_ready = 1'd0;
+reg [1:0] litedramcore_bankmachine5_trascon_count = 2'd0;
+wire litedramcore_bankmachine6_req_valid;
+wire litedramcore_bankmachine6_req_ready;
+wire litedramcore_bankmachine6_req_we;
+wire [21:0] litedramcore_bankmachine6_req_addr;
+wire litedramcore_bankmachine6_req_lock;
+reg litedramcore_bankmachine6_req_wdata_ready = 1'd0;
+reg litedramcore_bankmachine6_req_rdata_valid = 1'd0;
+wire litedramcore_bankmachine6_refresh_req;
+reg litedramcore_bankmachine6_refresh_gnt = 1'd0;
+reg litedramcore_bankmachine6_cmd_valid = 1'd0;
+reg litedramcore_bankmachine6_cmd_ready = 1'd0;
+reg [14:0] litedramcore_bankmachine6_cmd_payload_a = 15'd0;
+wire [2:0] litedramcore_bankmachine6_cmd_payload_ba;
+reg litedramcore_bankmachine6_cmd_payload_cas = 1'd0;
+reg litedramcore_bankmachine6_cmd_payload_ras = 1'd0;
+reg litedramcore_bankmachine6_cmd_payload_we = 1'd0;
+reg litedramcore_bankmachine6_cmd_payload_is_cmd = 1'd0;
+reg litedramcore_bankmachine6_cmd_payload_is_read = 1'd0;
+reg litedramcore_bankmachine6_cmd_payload_is_write = 1'd0;
+reg litedramcore_bankmachine6_auto_precharge = 1'd0;
+wire litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid;
+wire litedramcore_bankmachine6_cmd_buffer_lookahead_sink_ready;
+reg litedramcore_bankmachine6_cmd_buffer_lookahead_sink_first = 1'd0;
+reg litedramcore_bankmachine6_cmd_buffer_lookahead_sink_last = 1'd0;
+wire litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_we;
+wire [21:0] litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_addr;
+wire litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid;
+wire litedramcore_bankmachine6_cmd_buffer_lookahead_source_ready;
+wire litedramcore_bankmachine6_cmd_buffer_lookahead_source_first;
+wire litedramcore_bankmachine6_cmd_buffer_lookahead_source_last;
+wire litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_we;
+wire [21:0] litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr;
+wire litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we;
+wire litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable;
+wire litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_re;
+wire litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable;
+wire [24:0] litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din;
+wire [24:0] litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout;
+reg [4:0] litedramcore_bankmachine6_cmd_buffer_lookahead_level = 5'd0;
+reg litedramcore_bankmachine6_cmd_buffer_lookahead_replace = 1'd0;
+reg [3:0] litedramcore_bankmachine6_cmd_buffer_lookahead_produce = 4'd0;
+reg [3:0] litedramcore_bankmachine6_cmd_buffer_lookahead_consume = 4'd0;
+reg [3:0] litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr = 4'd0;
+wire [24:0] litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_r;
+wire litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we;
+wire [24:0] litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w;
+wire litedramcore_bankmachine6_cmd_buffer_lookahead_do_read;
+wire [3:0] litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_adr;
+wire [24:0] litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_dat_r;
+wire litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we;
+wire [21:0] litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr;
+wire litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_first;
+wire litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_last;
+wire litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we;
+wire [21:0] litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr;
+wire litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first;
+wire litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last;
+wire litedramcore_bankmachine6_cmd_buffer_sink_valid;
+wire litedramcore_bankmachine6_cmd_buffer_sink_ready;
+wire litedramcore_bankmachine6_cmd_buffer_sink_first;
+wire litedramcore_bankmachine6_cmd_buffer_sink_last;
+wire litedramcore_bankmachine6_cmd_buffer_sink_payload_we;
+wire [21:0] litedramcore_bankmachine6_cmd_buffer_sink_payload_addr;
+reg litedramcore_bankmachine6_cmd_buffer_source_valid = 1'd0;
+wire litedramcore_bankmachine6_cmd_buffer_source_ready;
+reg litedramcore_bankmachine6_cmd_buffer_source_first = 1'd0;
+reg litedramcore_bankmachine6_cmd_buffer_source_last = 1'd0;
+reg litedramcore_bankmachine6_cmd_buffer_source_payload_we = 1'd0;
+reg [21:0] litedramcore_bankmachine6_cmd_buffer_source_payload_addr = 22'd0;
+reg [14:0] litedramcore_bankmachine6_row = 15'd0;
+reg litedramcore_bankmachine6_row_opened = 1'd0;
+wire litedramcore_bankmachine6_row_hit;
+reg litedramcore_bankmachine6_row_open = 1'd0;
+reg litedramcore_bankmachine6_row_close = 1'd0;
+reg litedramcore_bankmachine6_row_col_n_addr_sel = 1'd0;
+wire litedramcore_bankmachine6_twtpcon_valid;
+reg litedramcore_bankmachine6_twtpcon_ready = 1'd0;
+reg [2:0] litedramcore_bankmachine6_twtpcon_count = 3'd0;
+wire litedramcore_bankmachine6_trccon_valid;
+reg litedramcore_bankmachine6_trccon_ready = 1'd0;
+reg [1:0] litedramcore_bankmachine6_trccon_count = 2'd0;
+wire litedramcore_bankmachine6_trascon_valid;
+reg litedramcore_bankmachine6_trascon_ready = 1'd0;
+reg [1:0] litedramcore_bankmachine6_trascon_count = 2'd0;
+wire litedramcore_bankmachine7_req_valid;
+wire litedramcore_bankmachine7_req_ready;
+wire litedramcore_bankmachine7_req_we;
+wire [21:0] litedramcore_bankmachine7_req_addr;
+wire litedramcore_bankmachine7_req_lock;
+reg litedramcore_bankmachine7_req_wdata_ready = 1'd0;
+reg litedramcore_bankmachine7_req_rdata_valid = 1'd0;
+wire litedramcore_bankmachine7_refresh_req;
+reg litedramcore_bankmachine7_refresh_gnt = 1'd0;
+reg litedramcore_bankmachine7_cmd_valid = 1'd0;
+reg litedramcore_bankmachine7_cmd_ready = 1'd0;
+reg [14:0] litedramcore_bankmachine7_cmd_payload_a = 15'd0;
+wire [2:0] litedramcore_bankmachine7_cmd_payload_ba;
+reg litedramcore_bankmachine7_cmd_payload_cas = 1'd0;
+reg litedramcore_bankmachine7_cmd_payload_ras = 1'd0;
+reg litedramcore_bankmachine7_cmd_payload_we = 1'd0;
+reg litedramcore_bankmachine7_cmd_payload_is_cmd = 1'd0;
+reg litedramcore_bankmachine7_cmd_payload_is_read = 1'd0;
+reg litedramcore_bankmachine7_cmd_payload_is_write = 1'd0;
+reg litedramcore_bankmachine7_auto_precharge = 1'd0;
+wire litedramcore_bankmachine7_cmd_buffer_lookahead_sink_valid;
+wire litedramcore_bankmachine7_cmd_buffer_lookahead_sink_ready;
+reg litedramcore_bankmachine7_cmd_buffer_lookahead_sink_first = 1'd0;
+reg litedramcore_bankmachine7_cmd_buffer_lookahead_sink_last = 1'd0;
+wire litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_we;
+wire [21:0] litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_addr;
+wire litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid;
+wire litedramcore_bankmachine7_cmd_buffer_lookahead_source_ready;
+wire litedramcore_bankmachine7_cmd_buffer_lookahead_source_first;
+wire litedramcore_bankmachine7_cmd_buffer_lookahead_source_last;
+wire litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_we;
+wire [21:0] litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr;
+wire litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we;
+wire litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable;
+wire litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_re;
+wire litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable;
+wire [24:0] litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din;
+wire [24:0] litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout;
+reg [4:0] litedramcore_bankmachine7_cmd_buffer_lookahead_level = 5'd0;
+reg litedramcore_bankmachine7_cmd_buffer_lookahead_replace = 1'd0;
+reg [3:0] litedramcore_bankmachine7_cmd_buffer_lookahead_produce = 4'd0;
+reg [3:0] litedramcore_bankmachine7_cmd_buffer_lookahead_consume = 4'd0;
+reg [3:0] litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr = 4'd0;
+wire [24:0] litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_r;
+wire litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we;
+wire [24:0] litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w;
+wire litedramcore_bankmachine7_cmd_buffer_lookahead_do_read;
+wire [3:0] litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_adr;
+wire [24:0] litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_dat_r;
+wire litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we;
+wire [21:0] litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr;
+wire litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_first;
+wire litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_last;
+wire litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we;
+wire [21:0] litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr;
+wire litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first;
+wire litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last;
+wire litedramcore_bankmachine7_cmd_buffer_sink_valid;
+wire litedramcore_bankmachine7_cmd_buffer_sink_ready;
+wire litedramcore_bankmachine7_cmd_buffer_sink_first;
+wire litedramcore_bankmachine7_cmd_buffer_sink_last;
+wire litedramcore_bankmachine7_cmd_buffer_sink_payload_we;
+wire [21:0] litedramcore_bankmachine7_cmd_buffer_sink_payload_addr;
+reg litedramcore_bankmachine7_cmd_buffer_source_valid = 1'd0;
+wire litedramcore_bankmachine7_cmd_buffer_source_ready;
+reg litedramcore_bankmachine7_cmd_buffer_source_first = 1'd0;
+reg litedramcore_bankmachine7_cmd_buffer_source_last = 1'd0;
+reg litedramcore_bankmachine7_cmd_buffer_source_payload_we = 1'd0;
+reg [21:0] litedramcore_bankmachine7_cmd_buffer_source_payload_addr = 22'd0;
+reg [14:0] litedramcore_bankmachine7_row = 15'd0;
+reg litedramcore_bankmachine7_row_opened = 1'd0;
+wire litedramcore_bankmachine7_row_hit;
+reg litedramcore_bankmachine7_row_open = 1'd0;
+reg litedramcore_bankmachine7_row_close = 1'd0;
+reg litedramcore_bankmachine7_row_col_n_addr_sel = 1'd0;
+wire litedramcore_bankmachine7_twtpcon_valid;
+reg litedramcore_bankmachine7_twtpcon_ready = 1'd0;
+reg [2:0] litedramcore_bankmachine7_twtpcon_count = 3'd0;
+wire litedramcore_bankmachine7_trccon_valid;
+reg litedramcore_bankmachine7_trccon_ready = 1'd0;
+reg [1:0] litedramcore_bankmachine7_trccon_count = 2'd0;
+wire litedramcore_bankmachine7_trascon_valid;
+reg litedramcore_bankmachine7_trascon_ready = 1'd0;
+reg [1:0] litedramcore_bankmachine7_trascon_count = 2'd0;
+wire litedramcore_ras_allowed;
+wire litedramcore_cas_allowed;
+reg litedramcore_choose_cmd_want_reads = 1'd0;
+reg litedramcore_choose_cmd_want_writes = 1'd0;
+reg litedramcore_choose_cmd_want_cmds = 1'd0;
+reg litedramcore_choose_cmd_want_activates = 1'd0;
+wire litedramcore_choose_cmd_cmd_valid;
+reg litedramcore_choose_cmd_cmd_ready = 1'd0;
+wire [14:0] litedramcore_choose_cmd_cmd_payload_a;
+wire [2:0] litedramcore_choose_cmd_cmd_payload_ba;
+reg litedramcore_choose_cmd_cmd_payload_cas = 1'd0;
+reg litedramcore_choose_cmd_cmd_payload_ras = 1'd0;
+reg litedramcore_choose_cmd_cmd_payload_we = 1'd0;
+wire litedramcore_choose_cmd_cmd_payload_is_cmd;
+wire litedramcore_choose_cmd_cmd_payload_is_read;
+wire litedramcore_choose_cmd_cmd_payload_is_write;
+reg [7:0] litedramcore_choose_cmd_valids = 8'd0;
+wire [7:0] litedramcore_choose_cmd_request;
+reg [2:0] litedramcore_choose_cmd_grant = 3'd0;
+wire litedramcore_choose_cmd_ce;
+reg litedramcore_choose_req_want_reads = 1'd0;
+reg litedramcore_choose_req_want_writes = 1'd0;
+reg litedramcore_choose_req_want_cmds = 1'd0;
+reg litedramcore_choose_req_want_activates = 1'd0;
+wire litedramcore_choose_req_cmd_valid;
+reg litedramcore_choose_req_cmd_ready = 1'd0;
+wire [14:0] litedramcore_choose_req_cmd_payload_a;
+wire [2:0] litedramcore_choose_req_cmd_payload_ba;
+reg litedramcore_choose_req_cmd_payload_cas = 1'd0;
+reg litedramcore_choose_req_cmd_payload_ras = 1'd0;
+reg litedramcore_choose_req_cmd_payload_we = 1'd0;
+wire litedramcore_choose_req_cmd_payload_is_cmd;
+wire litedramcore_choose_req_cmd_payload_is_read;
+wire litedramcore_choose_req_cmd_payload_is_write;
+reg [7:0] litedramcore_choose_req_valids = 8'd0;
+wire [7:0] litedramcore_choose_req_request;
+reg [2:0] litedramcore_choose_req_grant = 3'd0;
+wire litedramcore_choose_req_ce;
+reg [14:0] litedramcore_nop_a = 15'd0;
+reg [2:0] litedramcore_nop_ba = 3'd0;
+reg [1:0] litedramcore_steerer_sel0 = 2'd0;
+reg [1:0] litedramcore_steerer_sel1 = 2'd0;
+reg litedramcore_steerer0 = 1'd1;
+reg litedramcore_steerer1 = 1'd1;
+reg litedramcore_steerer2 = 1'd1;
+reg litedramcore_steerer3 = 1'd1;
+wire litedramcore_trrdcon_valid;
+reg litedramcore_trrdcon_ready = 1'd0;
+reg litedramcore_trrdcon_count = 1'd0;
+wire litedramcore_tfawcon_valid;
+reg litedramcore_tfawcon_ready = 1'd1;
+wire [1:0] litedramcore_tfawcon_count;
+reg [2:0] litedramcore_tfawcon_window = 3'd0;
+wire litedramcore_tccdcon_valid;
+reg litedramcore_tccdcon_ready = 1'd0;
+reg litedramcore_tccdcon_count = 1'd0;
+wire litedramcore_twtrcon_valid;
+reg litedramcore_twtrcon_ready = 1'd0;
+reg [2:0] litedramcore_twtrcon_count = 3'd0;
+wire litedramcore_read_available;
+wire litedramcore_write_available;
+reg litedramcore_en0 = 1'd0;
+wire litedramcore_max_time0;
+reg [4:0] litedramcore_time0 = 5'd0;
+reg litedramcore_en1 = 1'd0;
+wire litedramcore_max_time1;
+reg [3:0] litedramcore_time1 = 4'd0;
+wire litedramcore_go_to_refresh;
+reg init_done_storage = 1'd0;
+reg init_done_re = 1'd0;
+reg init_error_storage = 1'd0;
+reg init_error_re = 1'd0;
+wire [29:0] wb_bus_adr;
+wire [31:0] wb_bus_dat_w;
+wire [31:0] wb_bus_dat_r;
+wire [3:0] wb_bus_sel;
+wire wb_bus_cyc;
+wire wb_bus_stb;
+wire wb_bus_ack;
+wire wb_bus_we;
+wire [2:0] wb_bus_cti;
+wire [1:0] wb_bus_bte;
+wire wb_bus_err;
+wire user_enable;
+wire user_port_cmd_valid;
+wire user_port_cmd_ready;
+wire user_port_cmd_payload_we;
+wire [24:0] user_port_cmd_payload_addr;
+wire user_port_wdata_valid;
+wire user_port_wdata_ready;
+wire [255:0] user_port_wdata_payload_data;
+wire [31:0] user_port_wdata_payload_we;
+wire user_port_rdata_valid;
+wire user_port_rdata_ready;
+wire [255:0] user_port_rdata_payload_data;
+wire litedramecp5ddrphycrg_ecp5pll;
+wire litedramecp5ddrphycrg_locked;
+reg [1:0] litedramcore_refresher_state = 2'd0;
+reg [1:0] litedramcore_refresher_next_state = 2'd0;
+reg [2:0] litedramcore_bankmachine0_state = 3'd0;
+reg [2:0] litedramcore_bankmachine0_next_state = 3'd0;
+reg [2:0] litedramcore_bankmachine1_state = 3'd0;
+reg [2:0] litedramcore_bankmachine1_next_state = 3'd0;
+reg [2:0] litedramcore_bankmachine2_state = 3'd0;
+reg [2:0] litedramcore_bankmachine2_next_state = 3'd0;
+reg [2:0] litedramcore_bankmachine3_state = 3'd0;
+reg [2:0] litedramcore_bankmachine3_next_state = 3'd0;
+reg [2:0] litedramcore_bankmachine4_state = 3'd0;
+reg [2:0] litedramcore_bankmachine4_next_state = 3'd0;
+reg [2:0] litedramcore_bankmachine5_state = 3'd0;
+reg [2:0] litedramcore_bankmachine5_next_state = 3'd0;
+reg [2:0] litedramcore_bankmachine6_state = 3'd0;
+reg [2:0] litedramcore_bankmachine6_next_state = 3'd0;
+reg [2:0] litedramcore_bankmachine7_state = 3'd0;
+reg [2:0] litedramcore_bankmachine7_next_state = 3'd0;
+reg [3:0] litedramcore_multiplexer_state = 4'd0;
+reg [3:0] litedramcore_multiplexer_next_state = 4'd0;
+wire litedramcore_roundrobin0_request;
+wire litedramcore_roundrobin0_grant;
+wire litedramcore_roundrobin0_ce;
+wire litedramcore_roundrobin1_request;
+wire litedramcore_roundrobin1_grant;
+wire litedramcore_roundrobin1_ce;
+wire litedramcore_roundrobin2_request;
+wire litedramcore_roundrobin2_grant;
+wire litedramcore_roundrobin2_ce;
+wire litedramcore_roundrobin3_request;
+wire litedramcore_roundrobin3_grant;
+wire litedramcore_roundrobin3_ce;
+wire litedramcore_roundrobin4_request;
+wire litedramcore_roundrobin4_grant;
+wire litedramcore_roundrobin4_ce;
+wire litedramcore_roundrobin5_request;
+wire litedramcore_roundrobin5_grant;
+wire litedramcore_roundrobin5_ce;
+wire litedramcore_roundrobin6_request;
+wire litedramcore_roundrobin6_grant;
+wire litedramcore_roundrobin6_ce;
+wire litedramcore_roundrobin7_request;
+wire litedramcore_roundrobin7_grant;
+wire litedramcore_roundrobin7_ce;
+reg litedramcore_locked0 = 1'd0;
+reg litedramcore_locked1 = 1'd0;
+reg litedramcore_locked2 = 1'd0;
+reg litedramcore_locked3 = 1'd0;
+reg litedramcore_locked4 = 1'd0;
+reg litedramcore_locked5 = 1'd0;
+reg litedramcore_locked6 = 1'd0;
+reg litedramcore_locked7 = 1'd0;
+reg litedramcore_new_master_wdata_ready0 = 1'd0;
+reg litedramcore_new_master_wdata_ready1 = 1'd0;
+reg litedramcore_new_master_wdata_ready2 = 1'd0;
+reg litedramcore_new_master_wdata_ready3 = 1'd0;
+reg litedramcore_new_master_rdata_valid0 = 1'd0;
+reg litedramcore_new_master_rdata_valid1 = 1'd0;
+reg litedramcore_new_master_rdata_valid2 = 1'd0;
+reg litedramcore_new_master_rdata_valid3 = 1'd0;
+reg litedramcore_new_master_rdata_valid4 = 1'd0;
+reg litedramcore_new_master_rdata_valid5 = 1'd0;
+reg litedramcore_new_master_rdata_valid6 = 1'd0;
+reg litedramcore_new_master_rdata_valid7 = 1'd0;
+reg litedramcore_new_master_rdata_valid8 = 1'd0;
+reg litedramcore_new_master_rdata_valid9 = 1'd0;
+reg litedramcore_new_master_rdata_valid10 = 1'd0;
+reg litedramcore_new_master_rdata_valid11 = 1'd0;
+reg litedramcore_new_master_rdata_valid12 = 1'd0;
+reg litedramcore_new_master_rdata_valid13 = 1'd0;
+reg [13:0] litedramcore_adr = 14'd0;
+reg litedramcore_we = 1'd0;
+reg [31:0] litedramcore_dat_w = 32'd0;
+wire [31:0] litedramcore_dat_r;
+wire [29:0] litedramcore_wishbone_adr;
+wire [31:0] litedramcore_wishbone_dat_w;
+reg [31:0] litedramcore_wishbone_dat_r = 32'd0;
+wire [3:0] litedramcore_wishbone_sel;
+wire litedramcore_wishbone_cyc;
+wire litedramcore_wishbone_stb;
+reg litedramcore_wishbone_ack = 1'd0;
+wire litedramcore_wishbone_we;
+wire [2:0] litedramcore_wishbone_cti;
+wire [1:0] litedramcore_wishbone_bte;
+reg litedramcore_wishbone_err = 1'd0;
+wire [13:0] interface0_bank_bus_adr;
+wire interface0_bank_bus_we;
+wire [31:0] interface0_bank_bus_dat_w;
+reg [31:0] interface0_bank_bus_dat_r = 32'd0;
+reg csrbank0_init_done0_re = 1'd0;
+wire csrbank0_init_done0_r;
+reg csrbank0_init_done0_we = 1'd0;
+wire csrbank0_init_done0_w;
+reg csrbank0_init_error0_re = 1'd0;
+wire csrbank0_init_error0_r;
+reg csrbank0_init_error0_we = 1'd0;
+wire csrbank0_init_error0_w;
+wire csrbank0_sel;
+wire [13:0] interface1_bank_bus_adr;
+wire interface1_bank_bus_we;
+wire [31:0] interface1_bank_bus_dat_w;
+reg [31:0] interface1_bank_bus_dat_r = 32'd0;
+reg csrbank1_dly_sel0_re = 1'd0;
+wire [3:0] csrbank1_dly_sel0_r;
+reg csrbank1_dly_sel0_we = 1'd0;
+wire [3:0] csrbank1_dly_sel0_w;
+reg csrbank1_burstdet_seen_re = 1'd0;
+wire [3:0] csrbank1_burstdet_seen_r;
+reg csrbank1_burstdet_seen_we = 1'd0;
+wire [3:0] csrbank1_burstdet_seen_w;
+wire csrbank1_sel;
+wire [13:0] interface2_bank_bus_adr;
+wire interface2_bank_bus_we;
+wire [31:0] interface2_bank_bus_dat_w;
+reg [31:0] interface2_bank_bus_dat_r = 32'd0;
+reg csrbank2_dfii_control0_re = 1'd0;
+wire [3:0] csrbank2_dfii_control0_r;
+reg csrbank2_dfii_control0_we = 1'd0;
+wire [3:0] csrbank2_dfii_control0_w;
+reg csrbank2_dfii_pi0_command0_re = 1'd0;
+wire [5:0] csrbank2_dfii_pi0_command0_r;
+reg csrbank2_dfii_pi0_command0_we = 1'd0;
+wire [5:0] csrbank2_dfii_pi0_command0_w;
+reg csrbank2_dfii_pi0_address0_re = 1'd0;
+wire [14:0] csrbank2_dfii_pi0_address0_r;
+reg csrbank2_dfii_pi0_address0_we = 1'd0;
+wire [14:0] csrbank2_dfii_pi0_address0_w;
+reg csrbank2_dfii_pi0_baddress0_re = 1'd0;
+wire [2:0] csrbank2_dfii_pi0_baddress0_r;
+reg csrbank2_dfii_pi0_baddress0_we = 1'd0;
+wire [2:0] csrbank2_dfii_pi0_baddress0_w;
+reg csrbank2_dfii_pi0_wrdata3_re = 1'd0;
+wire [31:0] csrbank2_dfii_pi0_wrdata3_r;
+reg csrbank2_dfii_pi0_wrdata3_we = 1'd0;
+wire [31:0] csrbank2_dfii_pi0_wrdata3_w;
+reg csrbank2_dfii_pi0_wrdata2_re = 1'd0;
+wire [31:0] csrbank2_dfii_pi0_wrdata2_r;
+reg csrbank2_dfii_pi0_wrdata2_we = 1'd0;
+wire [31:0] csrbank2_dfii_pi0_wrdata2_w;
+reg csrbank2_dfii_pi0_wrdata1_re = 1'd0;
+wire [31:0] csrbank2_dfii_pi0_wrdata1_r;
+reg csrbank2_dfii_pi0_wrdata1_we = 1'd0;
+wire [31:0] csrbank2_dfii_pi0_wrdata1_w;
+reg csrbank2_dfii_pi0_wrdata0_re = 1'd0;
+wire [31:0] csrbank2_dfii_pi0_wrdata0_r;
+reg csrbank2_dfii_pi0_wrdata0_we = 1'd0;
+wire [31:0] csrbank2_dfii_pi0_wrdata0_w;
+reg csrbank2_dfii_pi0_rddata3_re = 1'd0;
+wire [31:0] csrbank2_dfii_pi0_rddata3_r;
+reg csrbank2_dfii_pi0_rddata3_we = 1'd0;
+wire [31:0] csrbank2_dfii_pi0_rddata3_w;
+reg csrbank2_dfii_pi0_rddata2_re = 1'd0;
+wire [31:0] csrbank2_dfii_pi0_rddata2_r;
+reg csrbank2_dfii_pi0_rddata2_we = 1'd0;
+wire [31:0] csrbank2_dfii_pi0_rddata2_w;
+reg csrbank2_dfii_pi0_rddata1_re = 1'd0;
+wire [31:0] csrbank2_dfii_pi0_rddata1_r;
+reg csrbank2_dfii_pi0_rddata1_we = 1'd0;
+wire [31:0] csrbank2_dfii_pi0_rddata1_w;
+reg csrbank2_dfii_pi0_rddata0_re = 1'd0;
+wire [31:0] csrbank2_dfii_pi0_rddata0_r;
+reg csrbank2_dfii_pi0_rddata0_we = 1'd0;
+wire [31:0] csrbank2_dfii_pi0_rddata0_w;
+reg csrbank2_dfii_pi1_command0_re = 1'd0;
+wire [5:0] csrbank2_dfii_pi1_command0_r;
+reg csrbank2_dfii_pi1_command0_we = 1'd0;
+wire [5:0] csrbank2_dfii_pi1_command0_w;
+reg csrbank2_dfii_pi1_address0_re = 1'd0;
+wire [14:0] csrbank2_dfii_pi1_address0_r;
+reg csrbank2_dfii_pi1_address0_we = 1'd0;
+wire [14:0] csrbank2_dfii_pi1_address0_w;
+reg csrbank2_dfii_pi1_baddress0_re = 1'd0;
+wire [2:0] csrbank2_dfii_pi1_baddress0_r;
+reg csrbank2_dfii_pi1_baddress0_we = 1'd0;
+wire [2:0] csrbank2_dfii_pi1_baddress0_w;
+reg csrbank2_dfii_pi1_wrdata3_re = 1'd0;
+wire [31:0] csrbank2_dfii_pi1_wrdata3_r;
+reg csrbank2_dfii_pi1_wrdata3_we = 1'd0;
+wire [31:0] csrbank2_dfii_pi1_wrdata3_w;
+reg csrbank2_dfii_pi1_wrdata2_re = 1'd0;
+wire [31:0] csrbank2_dfii_pi1_wrdata2_r;
+reg csrbank2_dfii_pi1_wrdata2_we = 1'd0;
+wire [31:0] csrbank2_dfii_pi1_wrdata2_w;
+reg csrbank2_dfii_pi1_wrdata1_re = 1'd0;
+wire [31:0] csrbank2_dfii_pi1_wrdata1_r;
+reg csrbank2_dfii_pi1_wrdata1_we = 1'd0;
+wire [31:0] csrbank2_dfii_pi1_wrdata1_w;
+reg csrbank2_dfii_pi1_wrdata0_re = 1'd0;
+wire [31:0] csrbank2_dfii_pi1_wrdata0_r;
+reg csrbank2_dfii_pi1_wrdata0_we = 1'd0;
+wire [31:0] csrbank2_dfii_pi1_wrdata0_w;
+reg csrbank2_dfii_pi1_rddata3_re = 1'd0;
+wire [31:0] csrbank2_dfii_pi1_rddata3_r;
+reg csrbank2_dfii_pi1_rddata3_we = 1'd0;
+wire [31:0] csrbank2_dfii_pi1_rddata3_w;
+reg csrbank2_dfii_pi1_rddata2_re = 1'd0;
+wire [31:0] csrbank2_dfii_pi1_rddata2_r;
+reg csrbank2_dfii_pi1_rddata2_we = 1'd0;
+wire [31:0] csrbank2_dfii_pi1_rddata2_w;
+reg csrbank2_dfii_pi1_rddata1_re = 1'd0;
+wire [31:0] csrbank2_dfii_pi1_rddata1_r;
+reg csrbank2_dfii_pi1_rddata1_we = 1'd0;
+wire [31:0] csrbank2_dfii_pi1_rddata1_w;
+reg csrbank2_dfii_pi1_rddata0_re = 1'd0;
+wire [31:0] csrbank2_dfii_pi1_rddata0_r;
+reg csrbank2_dfii_pi1_rddata0_we = 1'd0;
+wire [31:0] csrbank2_dfii_pi1_rddata0_w;
+wire csrbank2_sel;
+wire [13:0] csr_interconnect_adr;
+wire csr_interconnect_we;
+wire [31:0] csr_interconnect_dat_w;
+wire [31:0] csr_interconnect_dat_r;
+reg [1:0] state = 2'd0;
+reg [1:0] next_state = 2'd0;
+reg [31:0] litedramcore_dat_w_next_value0 = 32'd0;
+reg litedramcore_dat_w_next_value_ce0 = 1'd0;
+reg [13:0] litedramcore_adr_next_value1 = 14'd0;
+reg litedramcore_adr_next_value_ce1 = 1'd0;
+reg litedramcore_we_next_value2 = 1'd0;
+reg litedramcore_we_next_value_ce2 = 1'd0;
+reg rhs_array_muxed0 = 1'd0;
+reg [14:0] rhs_array_muxed1 = 15'd0;
+reg [2:0] rhs_array_muxed2 = 3'd0;
+reg rhs_array_muxed3 = 1'd0;
+reg rhs_array_muxed4 = 1'd0;
+reg rhs_array_muxed5 = 1'd0;
+reg t_array_muxed0 = 1'd0;
+reg t_array_muxed1 = 1'd0;
+reg t_array_muxed2 = 1'd0;
+reg rhs_array_muxed6 = 1'd0;
+reg [14:0] rhs_array_muxed7 = 15'd0;
+reg [2:0] rhs_array_muxed8 = 3'd0;
+reg rhs_array_muxed9 = 1'd0;
+reg rhs_array_muxed10 = 1'd0;
+reg rhs_array_muxed11 = 1'd0;
+reg t_array_muxed3 = 1'd0;
+reg t_array_muxed4 = 1'd0;
+reg t_array_muxed5 = 1'd0;
+reg [21:0] rhs_array_muxed12 = 22'd0;
+reg rhs_array_muxed13 = 1'd0;
+reg rhs_array_muxed14 = 1'd0;
+reg [21:0] rhs_array_muxed15 = 22'd0;
+reg rhs_array_muxed16 = 1'd0;
+reg rhs_array_muxed17 = 1'd0;
+reg [21:0] rhs_array_muxed18 = 22'd0;
+reg rhs_array_muxed19 = 1'd0;
+reg rhs_array_muxed20 = 1'd0;
+reg [21:0] rhs_array_muxed21 = 22'd0;
+reg rhs_array_muxed22 = 1'd0;
+reg rhs_array_muxed23 = 1'd0;
+reg [21:0] rhs_array_muxed24 = 22'd0;
+reg rhs_array_muxed25 = 1'd0;
+reg rhs_array_muxed26 = 1'd0;
+reg [21:0] rhs_array_muxed27 = 22'd0;
+reg rhs_array_muxed28 = 1'd0;
+reg rhs_array_muxed29 = 1'd0;
+reg [21:0] rhs_array_muxed30 = 22'd0;
+reg rhs_array_muxed31 = 1'd0;
+reg rhs_array_muxed32 = 1'd0;
+reg [21:0] rhs_array_muxed33 = 22'd0;
+reg rhs_array_muxed34 = 1'd0;
+reg rhs_array_muxed35 = 1'd0;
+reg [2:0] array_muxed0 = 3'd0;
+reg [14:0] array_muxed1 = 15'd0;
+reg array_muxed2 = 1'd0;
+reg array_muxed3 = 1'd0;
+reg array_muxed4 = 1'd0;
+reg array_muxed5 = 1'd0;
+reg array_muxed6 = 1'd0;
+reg [2:0] array_muxed7 = 3'd0;
+reg [14:0] array_muxed8 = 15'd0;
+reg array_muxed9 = 1'd0;
+reg array_muxed10 = 1'd0;
+reg array_muxed11 = 1'd0;
+reg array_muxed12 = 1'd0;
+reg array_muxed13 = 1'd0;
+wire latticeecp5asyncresetsynchronizerimpl0_rst1;
+wire latticeecp5asyncresetsynchronizerimpl0_expr;
+wire latticeecp5asyncresetsynchronizerimpl1_rst1;
+wire latticeecp5asyncresetsynchronizerimpl2_rst1;
+wire latticeecp5asyncresetsynchronizerimpl3_rst1;
+reg regs0 = 1'd0;
+reg regs1 = 1'd0;
+
+//------------------------------------------------------------------------------
+// Combinatorial Logic
+//------------------------------------------------------------------------------
+
+assign crg_stop = ddrphy_stop0;
+assign crg_reset0 = ddrphy_reset0;
+assign init_done = init_done_storage;
+assign init_error = init_error_storage;
+assign wb_bus_adr = wb_ctrl_adr;
+assign wb_bus_dat_w = wb_ctrl_dat_w;
+assign wb_ctrl_dat_r = wb_bus_dat_r;
+assign wb_bus_sel = wb_ctrl_sel;
+assign wb_bus_cyc = wb_ctrl_cyc;
+assign wb_bus_stb = wb_ctrl_stb;
+assign wb_ctrl_ack = wb_bus_ack;
+assign wb_bus_we = wb_ctrl_we;
+assign wb_bus_cti = wb_ctrl_cti;
+assign wb_bus_bte = wb_ctrl_bte;
+assign wb_ctrl_err = wb_bus_err;
+assign user_clk = sys_clk;
+assign user_rst = sys_rst;
+assign user_enable = 1'd1;
+assign user_port_cmd_valid = (user_port_native_0_cmd_valid & user_enable);
+assign user_port_native_0_cmd_ready = (user_port_cmd_ready & user_enable);
+assign user_port_cmd_payload_we = user_port_native_0_cmd_we;
+assign user_port_cmd_payload_addr = user_port_native_0_cmd_addr;
+assign user_port_wdata_valid = (user_port_native_0_wdata_valid & user_enable);
+assign user_port_native_0_wdata_ready = (user_port_wdata_ready & user_enable);
+assign user_port_wdata_payload_we = user_port_native_0_wdata_we;
+assign user_port_wdata_payload_data = user_port_native_0_wdata_data;
+assign user_port_native_0_rdata_valid = (user_port_rdata_valid & user_enable);
+assign user_port_rdata_ready = (user_port_native_0_rdata_ready & user_enable);
+assign user_port_native_0_rdata_data = user_port_rdata_payload_data;
+assign por_clk = clk;
+assign crg_por_done = (crg_por_count == 1'd0);
+assign crg_reset1 = (((~crg_por_done) | rst) | crg_rst);
+assign pll_locked = crg_locked;
+assign crg_clkin = clk;
+assign sys2x_i_clk = crg_clkout0;
+assign init_clk = crg_clkout1;
+assign crg_locked = (litedramecp5ddrphycrg_locked & (~crg_reset1));
+always @(*) begin
+ ddrphy_dm_o_data0 <= 8'd0;
+ ddrphy_dm_o_data0[0] <= ddrphy_dfi_p0_wrdata_mask[1];
+ ddrphy_dm_o_data0[1] <= ddrphy_dfi_p0_wrdata_mask[5];
+ ddrphy_dm_o_data0[2] <= ddrphy_dfi_p0_wrdata_mask[9];
+ ddrphy_dm_o_data0[3] <= ddrphy_dfi_p0_wrdata_mask[13];
+ ddrphy_dm_o_data0[4] <= ddrphy_dfi_p1_wrdata_mask[1];
+ ddrphy_dm_o_data0[5] <= ddrphy_dfi_p1_wrdata_mask[5];
+ ddrphy_dm_o_data0[6] <= ddrphy_dfi_p1_wrdata_mask[9];
+ ddrphy_dm_o_data0[7] <= ddrphy_dfi_p1_wrdata_mask[13];
+end
+always @(*) begin
+ ddrphy_dq_o_data0 <= 8'd0;
+ ddrphy_dq_o_data0[0] <= ddrphy_dfi_p0_wrdata[0];
+ ddrphy_dq_o_data0[1] <= ddrphy_dfi_p0_wrdata[32];
+ ddrphy_dq_o_data0[2] <= ddrphy_dfi_p0_wrdata[64];
+ ddrphy_dq_o_data0[3] <= ddrphy_dfi_p0_wrdata[96];
+ ddrphy_dq_o_data0[4] <= ddrphy_dfi_p1_wrdata[0];
+ ddrphy_dq_o_data0[5] <= ddrphy_dfi_p1_wrdata[32];
+ ddrphy_dq_o_data0[6] <= ddrphy_dfi_p1_wrdata[64];
+ ddrphy_dq_o_data0[7] <= ddrphy_dfi_p1_wrdata[96];
+end
+assign ddrphy_dq_i_data0 = {ddrphy_bitslip0_o, ddrphy_dq_i_bitslip_o_d0};
+always @(*) begin
+ ddrphy_dfi_p0_rddata <= 128'd0;
+ ddrphy_dfi_p0_rddata[0] <= ddrphy_dq_i_data0[0];
+ ddrphy_dfi_p0_rddata[32] <= ddrphy_dq_i_data0[1];
+ ddrphy_dfi_p0_rddata[64] <= ddrphy_dq_i_data0[2];
+ ddrphy_dfi_p0_rddata[96] <= ddrphy_dq_i_data0[3];
+ ddrphy_dfi_p0_rddata[1] <= ddrphy_dq_i_data1[0];
+ ddrphy_dfi_p0_rddata[33] <= ddrphy_dq_i_data1[1];
+ ddrphy_dfi_p0_rddata[65] <= ddrphy_dq_i_data1[2];
+ ddrphy_dfi_p0_rddata[97] <= ddrphy_dq_i_data1[3];
+ ddrphy_dfi_p0_rddata[2] <= ddrphy_dq_i_data2[0];
+ ddrphy_dfi_p0_rddata[34] <= ddrphy_dq_i_data2[1];
+ ddrphy_dfi_p0_rddata[66] <= ddrphy_dq_i_data2[2];
+ ddrphy_dfi_p0_rddata[98] <= ddrphy_dq_i_data2[3];
+ ddrphy_dfi_p0_rddata[3] <= ddrphy_dq_i_data3[0];
+ ddrphy_dfi_p0_rddata[35] <= ddrphy_dq_i_data3[1];
+ ddrphy_dfi_p0_rddata[67] <= ddrphy_dq_i_data3[2];
+ ddrphy_dfi_p0_rddata[99] <= ddrphy_dq_i_data3[3];
+ ddrphy_dfi_p0_rddata[4] <= ddrphy_dq_i_data4[0];
+ ddrphy_dfi_p0_rddata[36] <= ddrphy_dq_i_data4[1];
+ ddrphy_dfi_p0_rddata[68] <= ddrphy_dq_i_data4[2];
+ ddrphy_dfi_p0_rddata[100] <= ddrphy_dq_i_data4[3];
+ ddrphy_dfi_p0_rddata[5] <= ddrphy_dq_i_data5[0];
+ ddrphy_dfi_p0_rddata[37] <= ddrphy_dq_i_data5[1];
+ ddrphy_dfi_p0_rddata[69] <= ddrphy_dq_i_data5[2];
+ ddrphy_dfi_p0_rddata[101] <= ddrphy_dq_i_data5[3];
+ ddrphy_dfi_p0_rddata[6] <= ddrphy_dq_i_data6[0];
+ ddrphy_dfi_p0_rddata[38] <= ddrphy_dq_i_data6[1];
+ ddrphy_dfi_p0_rddata[70] <= ddrphy_dq_i_data6[2];
+ ddrphy_dfi_p0_rddata[102] <= ddrphy_dq_i_data6[3];
+ ddrphy_dfi_p0_rddata[7] <= ddrphy_dq_i_data7[0];
+ ddrphy_dfi_p0_rddata[39] <= ddrphy_dq_i_data7[1];
+ ddrphy_dfi_p0_rddata[71] <= ddrphy_dq_i_data7[2];
+ ddrphy_dfi_p0_rddata[103] <= ddrphy_dq_i_data7[3];
+ ddrphy_dfi_p0_rddata[8] <= ddrphy_dq_i_data8[0];
+ ddrphy_dfi_p0_rddata[40] <= ddrphy_dq_i_data8[1];
+ ddrphy_dfi_p0_rddata[72] <= ddrphy_dq_i_data8[2];
+ ddrphy_dfi_p0_rddata[104] <= ddrphy_dq_i_data8[3];
+ ddrphy_dfi_p0_rddata[9] <= ddrphy_dq_i_data9[0];
+ ddrphy_dfi_p0_rddata[41] <= ddrphy_dq_i_data9[1];
+ ddrphy_dfi_p0_rddata[73] <= ddrphy_dq_i_data9[2];
+ ddrphy_dfi_p0_rddata[105] <= ddrphy_dq_i_data9[3];
+ ddrphy_dfi_p0_rddata[10] <= ddrphy_dq_i_data10[0];
+ ddrphy_dfi_p0_rddata[42] <= ddrphy_dq_i_data10[1];
+ ddrphy_dfi_p0_rddata[74] <= ddrphy_dq_i_data10[2];
+ ddrphy_dfi_p0_rddata[106] <= ddrphy_dq_i_data10[3];
+ ddrphy_dfi_p0_rddata[11] <= ddrphy_dq_i_data11[0];
+ ddrphy_dfi_p0_rddata[43] <= ddrphy_dq_i_data11[1];
+ ddrphy_dfi_p0_rddata[75] <= ddrphy_dq_i_data11[2];
+ ddrphy_dfi_p0_rddata[107] <= ddrphy_dq_i_data11[3];
+ ddrphy_dfi_p0_rddata[12] <= ddrphy_dq_i_data12[0];
+ ddrphy_dfi_p0_rddata[44] <= ddrphy_dq_i_data12[1];
+ ddrphy_dfi_p0_rddata[76] <= ddrphy_dq_i_data12[2];
+ ddrphy_dfi_p0_rddata[108] <= ddrphy_dq_i_data12[3];
+ ddrphy_dfi_p0_rddata[13] <= ddrphy_dq_i_data13[0];
+ ddrphy_dfi_p0_rddata[45] <= ddrphy_dq_i_data13[1];
+ ddrphy_dfi_p0_rddata[77] <= ddrphy_dq_i_data13[2];
+ ddrphy_dfi_p0_rddata[109] <= ddrphy_dq_i_data13[3];
+ ddrphy_dfi_p0_rddata[14] <= ddrphy_dq_i_data14[0];
+ ddrphy_dfi_p0_rddata[46] <= ddrphy_dq_i_data14[1];
+ ddrphy_dfi_p0_rddata[78] <= ddrphy_dq_i_data14[2];
+ ddrphy_dfi_p0_rddata[110] <= ddrphy_dq_i_data14[3];
+ ddrphy_dfi_p0_rddata[15] <= ddrphy_dq_i_data15[0];
+ ddrphy_dfi_p0_rddata[47] <= ddrphy_dq_i_data15[1];
+ ddrphy_dfi_p0_rddata[79] <= ddrphy_dq_i_data15[2];
+ ddrphy_dfi_p0_rddata[111] <= ddrphy_dq_i_data15[3];
+ ddrphy_dfi_p0_rddata[16] <= ddrphy_dq_i_data16[0];
+ ddrphy_dfi_p0_rddata[48] <= ddrphy_dq_i_data16[1];
+ ddrphy_dfi_p0_rddata[80] <= ddrphy_dq_i_data16[2];
+ ddrphy_dfi_p0_rddata[112] <= ddrphy_dq_i_data16[3];
+ ddrphy_dfi_p0_rddata[17] <= ddrphy_dq_i_data17[0];
+ ddrphy_dfi_p0_rddata[49] <= ddrphy_dq_i_data17[1];
+ ddrphy_dfi_p0_rddata[81] <= ddrphy_dq_i_data17[2];
+ ddrphy_dfi_p0_rddata[113] <= ddrphy_dq_i_data17[3];
+ ddrphy_dfi_p0_rddata[18] <= ddrphy_dq_i_data18[0];
+ ddrphy_dfi_p0_rddata[50] <= ddrphy_dq_i_data18[1];
+ ddrphy_dfi_p0_rddata[82] <= ddrphy_dq_i_data18[2];
+ ddrphy_dfi_p0_rddata[114] <= ddrphy_dq_i_data18[3];
+ ddrphy_dfi_p0_rddata[19] <= ddrphy_dq_i_data19[0];
+ ddrphy_dfi_p0_rddata[51] <= ddrphy_dq_i_data19[1];
+ ddrphy_dfi_p0_rddata[83] <= ddrphy_dq_i_data19[2];
+ ddrphy_dfi_p0_rddata[115] <= ddrphy_dq_i_data19[3];
+ ddrphy_dfi_p0_rddata[20] <= ddrphy_dq_i_data20[0];
+ ddrphy_dfi_p0_rddata[52] <= ddrphy_dq_i_data20[1];
+ ddrphy_dfi_p0_rddata[84] <= ddrphy_dq_i_data20[2];
+ ddrphy_dfi_p0_rddata[116] <= ddrphy_dq_i_data20[3];
+ ddrphy_dfi_p0_rddata[21] <= ddrphy_dq_i_data21[0];
+ ddrphy_dfi_p0_rddata[53] <= ddrphy_dq_i_data21[1];
+ ddrphy_dfi_p0_rddata[85] <= ddrphy_dq_i_data21[2];
+ ddrphy_dfi_p0_rddata[117] <= ddrphy_dq_i_data21[3];
+ ddrphy_dfi_p0_rddata[22] <= ddrphy_dq_i_data22[0];
+ ddrphy_dfi_p0_rddata[54] <= ddrphy_dq_i_data22[1];
+ ddrphy_dfi_p0_rddata[86] <= ddrphy_dq_i_data22[2];
+ ddrphy_dfi_p0_rddata[118] <= ddrphy_dq_i_data22[3];
+ ddrphy_dfi_p0_rddata[23] <= ddrphy_dq_i_data23[0];
+ ddrphy_dfi_p0_rddata[55] <= ddrphy_dq_i_data23[1];
+ ddrphy_dfi_p0_rddata[87] <= ddrphy_dq_i_data23[2];
+ ddrphy_dfi_p0_rddata[119] <= ddrphy_dq_i_data23[3];
+ ddrphy_dfi_p0_rddata[24] <= ddrphy_dq_i_data24[0];
+ ddrphy_dfi_p0_rddata[56] <= ddrphy_dq_i_data24[1];
+ ddrphy_dfi_p0_rddata[88] <= ddrphy_dq_i_data24[2];
+ ddrphy_dfi_p0_rddata[120] <= ddrphy_dq_i_data24[3];
+ ddrphy_dfi_p0_rddata[25] <= ddrphy_dq_i_data25[0];
+ ddrphy_dfi_p0_rddata[57] <= ddrphy_dq_i_data25[1];
+ ddrphy_dfi_p0_rddata[89] <= ddrphy_dq_i_data25[2];
+ ddrphy_dfi_p0_rddata[121] <= ddrphy_dq_i_data25[3];
+ ddrphy_dfi_p0_rddata[26] <= ddrphy_dq_i_data26[0];
+ ddrphy_dfi_p0_rddata[58] <= ddrphy_dq_i_data26[1];
+ ddrphy_dfi_p0_rddata[90] <= ddrphy_dq_i_data26[2];
+ ddrphy_dfi_p0_rddata[122] <= ddrphy_dq_i_data26[3];
+ ddrphy_dfi_p0_rddata[27] <= ddrphy_dq_i_data27[0];
+ ddrphy_dfi_p0_rddata[59] <= ddrphy_dq_i_data27[1];
+ ddrphy_dfi_p0_rddata[91] <= ddrphy_dq_i_data27[2];
+ ddrphy_dfi_p0_rddata[123] <= ddrphy_dq_i_data27[3];
+ ddrphy_dfi_p0_rddata[28] <= ddrphy_dq_i_data28[0];
+ ddrphy_dfi_p0_rddata[60] <= ddrphy_dq_i_data28[1];
+ ddrphy_dfi_p0_rddata[92] <= ddrphy_dq_i_data28[2];
+ ddrphy_dfi_p0_rddata[124] <= ddrphy_dq_i_data28[3];
+ ddrphy_dfi_p0_rddata[29] <= ddrphy_dq_i_data29[0];
+ ddrphy_dfi_p0_rddata[61] <= ddrphy_dq_i_data29[1];
+ ddrphy_dfi_p0_rddata[93] <= ddrphy_dq_i_data29[2];
+ ddrphy_dfi_p0_rddata[125] <= ddrphy_dq_i_data29[3];
+ ddrphy_dfi_p0_rddata[30] <= ddrphy_dq_i_data30[0];
+ ddrphy_dfi_p0_rddata[62] <= ddrphy_dq_i_data30[1];
+ ddrphy_dfi_p0_rddata[94] <= ddrphy_dq_i_data30[2];
+ ddrphy_dfi_p0_rddata[126] <= ddrphy_dq_i_data30[3];
+ ddrphy_dfi_p0_rddata[31] <= ddrphy_dq_i_data31[0];
+ ddrphy_dfi_p0_rddata[63] <= ddrphy_dq_i_data31[1];
+ ddrphy_dfi_p0_rddata[95] <= ddrphy_dq_i_data31[2];
+ ddrphy_dfi_p0_rddata[127] <= ddrphy_dq_i_data31[3];
+end
+always @(*) begin
+ ddrphy_dfi_p1_rddata <= 128'd0;
+ ddrphy_dfi_p1_rddata[0] <= ddrphy_dq_i_data0[4];
+ ddrphy_dfi_p1_rddata[32] <= ddrphy_dq_i_data0[5];
+ ddrphy_dfi_p1_rddata[64] <= ddrphy_dq_i_data0[6];
+ ddrphy_dfi_p1_rddata[96] <= ddrphy_dq_i_data0[7];
+ ddrphy_dfi_p1_rddata[1] <= ddrphy_dq_i_data1[4];
+ ddrphy_dfi_p1_rddata[33] <= ddrphy_dq_i_data1[5];
+ ddrphy_dfi_p1_rddata[65] <= ddrphy_dq_i_data1[6];
+ ddrphy_dfi_p1_rddata[97] <= ddrphy_dq_i_data1[7];
+ ddrphy_dfi_p1_rddata[2] <= ddrphy_dq_i_data2[4];
+ ddrphy_dfi_p1_rddata[34] <= ddrphy_dq_i_data2[5];
+ ddrphy_dfi_p1_rddata[66] <= ddrphy_dq_i_data2[6];
+ ddrphy_dfi_p1_rddata[98] <= ddrphy_dq_i_data2[7];
+ ddrphy_dfi_p1_rddata[3] <= ddrphy_dq_i_data3[4];
+ ddrphy_dfi_p1_rddata[35] <= ddrphy_dq_i_data3[5];
+ ddrphy_dfi_p1_rddata[67] <= ddrphy_dq_i_data3[6];
+ ddrphy_dfi_p1_rddata[99] <= ddrphy_dq_i_data3[7];
+ ddrphy_dfi_p1_rddata[4] <= ddrphy_dq_i_data4[4];
+ ddrphy_dfi_p1_rddata[36] <= ddrphy_dq_i_data4[5];
+ ddrphy_dfi_p1_rddata[68] <= ddrphy_dq_i_data4[6];
+ ddrphy_dfi_p1_rddata[100] <= ddrphy_dq_i_data4[7];
+ ddrphy_dfi_p1_rddata[5] <= ddrphy_dq_i_data5[4];
+ ddrphy_dfi_p1_rddata[37] <= ddrphy_dq_i_data5[5];
+ ddrphy_dfi_p1_rddata[69] <= ddrphy_dq_i_data5[6];
+ ddrphy_dfi_p1_rddata[101] <= ddrphy_dq_i_data5[7];
+ ddrphy_dfi_p1_rddata[6] <= ddrphy_dq_i_data6[4];
+ ddrphy_dfi_p1_rddata[38] <= ddrphy_dq_i_data6[5];
+ ddrphy_dfi_p1_rddata[70] <= ddrphy_dq_i_data6[6];
+ ddrphy_dfi_p1_rddata[102] <= ddrphy_dq_i_data6[7];
+ ddrphy_dfi_p1_rddata[7] <= ddrphy_dq_i_data7[4];
+ ddrphy_dfi_p1_rddata[39] <= ddrphy_dq_i_data7[5];
+ ddrphy_dfi_p1_rddata[71] <= ddrphy_dq_i_data7[6];
+ ddrphy_dfi_p1_rddata[103] <= ddrphy_dq_i_data7[7];
+ ddrphy_dfi_p1_rddata[8] <= ddrphy_dq_i_data8[4];
+ ddrphy_dfi_p1_rddata[40] <= ddrphy_dq_i_data8[5];
+ ddrphy_dfi_p1_rddata[72] <= ddrphy_dq_i_data8[6];
+ ddrphy_dfi_p1_rddata[104] <= ddrphy_dq_i_data8[7];
+ ddrphy_dfi_p1_rddata[9] <= ddrphy_dq_i_data9[4];
+ ddrphy_dfi_p1_rddata[41] <= ddrphy_dq_i_data9[5];
+ ddrphy_dfi_p1_rddata[73] <= ddrphy_dq_i_data9[6];
+ ddrphy_dfi_p1_rddata[105] <= ddrphy_dq_i_data9[7];
+ ddrphy_dfi_p1_rddata[10] <= ddrphy_dq_i_data10[4];
+ ddrphy_dfi_p1_rddata[42] <= ddrphy_dq_i_data10[5];
+ ddrphy_dfi_p1_rddata[74] <= ddrphy_dq_i_data10[6];
+ ddrphy_dfi_p1_rddata[106] <= ddrphy_dq_i_data10[7];
+ ddrphy_dfi_p1_rddata[11] <= ddrphy_dq_i_data11[4];
+ ddrphy_dfi_p1_rddata[43] <= ddrphy_dq_i_data11[5];
+ ddrphy_dfi_p1_rddata[75] <= ddrphy_dq_i_data11[6];
+ ddrphy_dfi_p1_rddata[107] <= ddrphy_dq_i_data11[7];
+ ddrphy_dfi_p1_rddata[12] <= ddrphy_dq_i_data12[4];
+ ddrphy_dfi_p1_rddata[44] <= ddrphy_dq_i_data12[5];
+ ddrphy_dfi_p1_rddata[76] <= ddrphy_dq_i_data12[6];
+ ddrphy_dfi_p1_rddata[108] <= ddrphy_dq_i_data12[7];
+ ddrphy_dfi_p1_rddata[13] <= ddrphy_dq_i_data13[4];
+ ddrphy_dfi_p1_rddata[45] <= ddrphy_dq_i_data13[5];
+ ddrphy_dfi_p1_rddata[77] <= ddrphy_dq_i_data13[6];
+ ddrphy_dfi_p1_rddata[109] <= ddrphy_dq_i_data13[7];
+ ddrphy_dfi_p1_rddata[14] <= ddrphy_dq_i_data14[4];
+ ddrphy_dfi_p1_rddata[46] <= ddrphy_dq_i_data14[5];
+ ddrphy_dfi_p1_rddata[78] <= ddrphy_dq_i_data14[6];
+ ddrphy_dfi_p1_rddata[110] <= ddrphy_dq_i_data14[7];
+ ddrphy_dfi_p1_rddata[15] <= ddrphy_dq_i_data15[4];
+ ddrphy_dfi_p1_rddata[47] <= ddrphy_dq_i_data15[5];
+ ddrphy_dfi_p1_rddata[79] <= ddrphy_dq_i_data15[6];
+ ddrphy_dfi_p1_rddata[111] <= ddrphy_dq_i_data15[7];
+ ddrphy_dfi_p1_rddata[16] <= ddrphy_dq_i_data16[4];
+ ddrphy_dfi_p1_rddata[48] <= ddrphy_dq_i_data16[5];
+ ddrphy_dfi_p1_rddata[80] <= ddrphy_dq_i_data16[6];
+ ddrphy_dfi_p1_rddata[112] <= ddrphy_dq_i_data16[7];
+ ddrphy_dfi_p1_rddata[17] <= ddrphy_dq_i_data17[4];
+ ddrphy_dfi_p1_rddata[49] <= ddrphy_dq_i_data17[5];
+ ddrphy_dfi_p1_rddata[81] <= ddrphy_dq_i_data17[6];
+ ddrphy_dfi_p1_rddata[113] <= ddrphy_dq_i_data17[7];
+ ddrphy_dfi_p1_rddata[18] <= ddrphy_dq_i_data18[4];
+ ddrphy_dfi_p1_rddata[50] <= ddrphy_dq_i_data18[5];
+ ddrphy_dfi_p1_rddata[82] <= ddrphy_dq_i_data18[6];
+ ddrphy_dfi_p1_rddata[114] <= ddrphy_dq_i_data18[7];
+ ddrphy_dfi_p1_rddata[19] <= ddrphy_dq_i_data19[4];
+ ddrphy_dfi_p1_rddata[51] <= ddrphy_dq_i_data19[5];
+ ddrphy_dfi_p1_rddata[83] <= ddrphy_dq_i_data19[6];
+ ddrphy_dfi_p1_rddata[115] <= ddrphy_dq_i_data19[7];
+ ddrphy_dfi_p1_rddata[20] <= ddrphy_dq_i_data20[4];
+ ddrphy_dfi_p1_rddata[52] <= ddrphy_dq_i_data20[5];
+ ddrphy_dfi_p1_rddata[84] <= ddrphy_dq_i_data20[6];
+ ddrphy_dfi_p1_rddata[116] <= ddrphy_dq_i_data20[7];
+ ddrphy_dfi_p1_rddata[21] <= ddrphy_dq_i_data21[4];
+ ddrphy_dfi_p1_rddata[53] <= ddrphy_dq_i_data21[5];
+ ddrphy_dfi_p1_rddata[85] <= ddrphy_dq_i_data21[6];
+ ddrphy_dfi_p1_rddata[117] <= ddrphy_dq_i_data21[7];
+ ddrphy_dfi_p1_rddata[22] <= ddrphy_dq_i_data22[4];
+ ddrphy_dfi_p1_rddata[54] <= ddrphy_dq_i_data22[5];
+ ddrphy_dfi_p1_rddata[86] <= ddrphy_dq_i_data22[6];
+ ddrphy_dfi_p1_rddata[118] <= ddrphy_dq_i_data22[7];
+ ddrphy_dfi_p1_rddata[23] <= ddrphy_dq_i_data23[4];
+ ddrphy_dfi_p1_rddata[55] <= ddrphy_dq_i_data23[5];
+ ddrphy_dfi_p1_rddata[87] <= ddrphy_dq_i_data23[6];
+ ddrphy_dfi_p1_rddata[119] <= ddrphy_dq_i_data23[7];
+ ddrphy_dfi_p1_rddata[24] <= ddrphy_dq_i_data24[4];
+ ddrphy_dfi_p1_rddata[56] <= ddrphy_dq_i_data24[5];
+ ddrphy_dfi_p1_rddata[88] <= ddrphy_dq_i_data24[6];
+ ddrphy_dfi_p1_rddata[120] <= ddrphy_dq_i_data24[7];
+ ddrphy_dfi_p1_rddata[25] <= ddrphy_dq_i_data25[4];
+ ddrphy_dfi_p1_rddata[57] <= ddrphy_dq_i_data25[5];
+ ddrphy_dfi_p1_rddata[89] <= ddrphy_dq_i_data25[6];
+ ddrphy_dfi_p1_rddata[121] <= ddrphy_dq_i_data25[7];
+ ddrphy_dfi_p1_rddata[26] <= ddrphy_dq_i_data26[4];
+ ddrphy_dfi_p1_rddata[58] <= ddrphy_dq_i_data26[5];
+ ddrphy_dfi_p1_rddata[90] <= ddrphy_dq_i_data26[6];
+ ddrphy_dfi_p1_rddata[122] <= ddrphy_dq_i_data26[7];
+ ddrphy_dfi_p1_rddata[27] <= ddrphy_dq_i_data27[4];
+ ddrphy_dfi_p1_rddata[59] <= ddrphy_dq_i_data27[5];
+ ddrphy_dfi_p1_rddata[91] <= ddrphy_dq_i_data27[6];
+ ddrphy_dfi_p1_rddata[123] <= ddrphy_dq_i_data27[7];
+ ddrphy_dfi_p1_rddata[28] <= ddrphy_dq_i_data28[4];
+ ddrphy_dfi_p1_rddata[60] <= ddrphy_dq_i_data28[5];
+ ddrphy_dfi_p1_rddata[92] <= ddrphy_dq_i_data28[6];
+ ddrphy_dfi_p1_rddata[124] <= ddrphy_dq_i_data28[7];
+ ddrphy_dfi_p1_rddata[29] <= ddrphy_dq_i_data29[4];
+ ddrphy_dfi_p1_rddata[61] <= ddrphy_dq_i_data29[5];
+ ddrphy_dfi_p1_rddata[93] <= ddrphy_dq_i_data29[6];
+ ddrphy_dfi_p1_rddata[125] <= ddrphy_dq_i_data29[7];
+ ddrphy_dfi_p1_rddata[30] <= ddrphy_dq_i_data30[4];
+ ddrphy_dfi_p1_rddata[62] <= ddrphy_dq_i_data30[5];
+ ddrphy_dfi_p1_rddata[94] <= ddrphy_dq_i_data30[6];
+ ddrphy_dfi_p1_rddata[126] <= ddrphy_dq_i_data30[7];
+ ddrphy_dfi_p1_rddata[31] <= ddrphy_dq_i_data31[4];
+ ddrphy_dfi_p1_rddata[63] <= ddrphy_dq_i_data31[5];
+ ddrphy_dfi_p1_rddata[95] <= ddrphy_dq_i_data31[6];
+ ddrphy_dfi_p1_rddata[127] <= ddrphy_dq_i_data31[7];
+end
+always @(*) begin
+ ddrphy_dq_o_data1 <= 8'd0;
+ ddrphy_dq_o_data1[0] <= ddrphy_dfi_p0_wrdata[1];
+ ddrphy_dq_o_data1[1] <= ddrphy_dfi_p0_wrdata[33];
+ ddrphy_dq_o_data1[2] <= ddrphy_dfi_p0_wrdata[65];
+ ddrphy_dq_o_data1[3] <= ddrphy_dfi_p0_wrdata[97];
+ ddrphy_dq_o_data1[4] <= ddrphy_dfi_p1_wrdata[1];
+ ddrphy_dq_o_data1[5] <= ddrphy_dfi_p1_wrdata[33];
+ ddrphy_dq_o_data1[6] <= ddrphy_dfi_p1_wrdata[65];
+ ddrphy_dq_o_data1[7] <= ddrphy_dfi_p1_wrdata[97];
+end
+assign ddrphy_dq_i_data1 = {ddrphy_bitslip1_o, ddrphy_dq_i_bitslip_o_d1};
+always @(*) begin
+ ddrphy_dq_o_data2 <= 8'd0;
+ ddrphy_dq_o_data2[0] <= ddrphy_dfi_p0_wrdata[2];
+ ddrphy_dq_o_data2[1] <= ddrphy_dfi_p0_wrdata[34];
+ ddrphy_dq_o_data2[2] <= ddrphy_dfi_p0_wrdata[66];
+ ddrphy_dq_o_data2[3] <= ddrphy_dfi_p0_wrdata[98];
+ ddrphy_dq_o_data2[4] <= ddrphy_dfi_p1_wrdata[2];
+ ddrphy_dq_o_data2[5] <= ddrphy_dfi_p1_wrdata[34];
+ ddrphy_dq_o_data2[6] <= ddrphy_dfi_p1_wrdata[66];
+ ddrphy_dq_o_data2[7] <= ddrphy_dfi_p1_wrdata[98];
+end
+assign ddrphy_dq_i_data2 = {ddrphy_bitslip2_o, ddrphy_dq_i_bitslip_o_d2};
+always @(*) begin
+ ddrphy_dq_o_data3 <= 8'd0;
+ ddrphy_dq_o_data3[0] <= ddrphy_dfi_p0_wrdata[3];
+ ddrphy_dq_o_data3[1] <= ddrphy_dfi_p0_wrdata[35];
+ ddrphy_dq_o_data3[2] <= ddrphy_dfi_p0_wrdata[67];
+ ddrphy_dq_o_data3[3] <= ddrphy_dfi_p0_wrdata[99];
+ ddrphy_dq_o_data3[4] <= ddrphy_dfi_p1_wrdata[3];
+ ddrphy_dq_o_data3[5] <= ddrphy_dfi_p1_wrdata[35];
+ ddrphy_dq_o_data3[6] <= ddrphy_dfi_p1_wrdata[67];
+ ddrphy_dq_o_data3[7] <= ddrphy_dfi_p1_wrdata[99];
+end
+assign ddrphy_dq_i_data3 = {ddrphy_bitslip3_o, ddrphy_dq_i_bitslip_o_d3};
+always @(*) begin
+ ddrphy_dq_o_data4 <= 8'd0;
+ ddrphy_dq_o_data4[0] <= ddrphy_dfi_p0_wrdata[4];
+ ddrphy_dq_o_data4[1] <= ddrphy_dfi_p0_wrdata[36];
+ ddrphy_dq_o_data4[2] <= ddrphy_dfi_p0_wrdata[68];
+ ddrphy_dq_o_data4[3] <= ddrphy_dfi_p0_wrdata[100];
+ ddrphy_dq_o_data4[4] <= ddrphy_dfi_p1_wrdata[4];
+ ddrphy_dq_o_data4[5] <= ddrphy_dfi_p1_wrdata[36];
+ ddrphy_dq_o_data4[6] <= ddrphy_dfi_p1_wrdata[68];
+ ddrphy_dq_o_data4[7] <= ddrphy_dfi_p1_wrdata[100];
+end
+assign ddrphy_dq_i_data4 = {ddrphy_bitslip4_o, ddrphy_dq_i_bitslip_o_d4};
+always @(*) begin
+ ddrphy_dq_o_data5 <= 8'd0;
+ ddrphy_dq_o_data5[0] <= ddrphy_dfi_p0_wrdata[5];
+ ddrphy_dq_o_data5[1] <= ddrphy_dfi_p0_wrdata[37];
+ ddrphy_dq_o_data5[2] <= ddrphy_dfi_p0_wrdata[69];
+ ddrphy_dq_o_data5[3] <= ddrphy_dfi_p0_wrdata[101];
+ ddrphy_dq_o_data5[4] <= ddrphy_dfi_p1_wrdata[5];
+ ddrphy_dq_o_data5[5] <= ddrphy_dfi_p1_wrdata[37];
+ ddrphy_dq_o_data5[6] <= ddrphy_dfi_p1_wrdata[69];
+ ddrphy_dq_o_data5[7] <= ddrphy_dfi_p1_wrdata[101];
+end
+assign ddrphy_dq_i_data5 = {ddrphy_bitslip5_o, ddrphy_dq_i_bitslip_o_d5};
+always @(*) begin
+ ddrphy_dq_o_data6 <= 8'd0;
+ ddrphy_dq_o_data6[0] <= ddrphy_dfi_p0_wrdata[6];
+ ddrphy_dq_o_data6[1] <= ddrphy_dfi_p0_wrdata[38];
+ ddrphy_dq_o_data6[2] <= ddrphy_dfi_p0_wrdata[70];
+ ddrphy_dq_o_data6[3] <= ddrphy_dfi_p0_wrdata[102];
+ ddrphy_dq_o_data6[4] <= ddrphy_dfi_p1_wrdata[6];
+ ddrphy_dq_o_data6[5] <= ddrphy_dfi_p1_wrdata[38];
+ ddrphy_dq_o_data6[6] <= ddrphy_dfi_p1_wrdata[70];
+ ddrphy_dq_o_data6[7] <= ddrphy_dfi_p1_wrdata[102];
+end
+assign ddrphy_dq_i_data6 = {ddrphy_bitslip6_o, ddrphy_dq_i_bitslip_o_d6};
+always @(*) begin
+ ddrphy_dq_o_data7 <= 8'd0;
+ ddrphy_dq_o_data7[0] <= ddrphy_dfi_p0_wrdata[7];
+ ddrphy_dq_o_data7[1] <= ddrphy_dfi_p0_wrdata[39];
+ ddrphy_dq_o_data7[2] <= ddrphy_dfi_p0_wrdata[71];
+ ddrphy_dq_o_data7[3] <= ddrphy_dfi_p0_wrdata[103];
+ ddrphy_dq_o_data7[4] <= ddrphy_dfi_p1_wrdata[7];
+ ddrphy_dq_o_data7[5] <= ddrphy_dfi_p1_wrdata[39];
+ ddrphy_dq_o_data7[6] <= ddrphy_dfi_p1_wrdata[71];
+ ddrphy_dq_o_data7[7] <= ddrphy_dfi_p1_wrdata[103];
+end
+assign ddrphy_dq_i_data7 = {ddrphy_bitslip7_o, ddrphy_dq_i_bitslip_o_d7};
+always @(*) begin
+ ddrphy_dm_o_data1 <= 8'd0;
+ ddrphy_dm_o_data1[0] <= ddrphy_dfi_p0_wrdata_mask[0];
+ ddrphy_dm_o_data1[1] <= ddrphy_dfi_p0_wrdata_mask[4];
+ ddrphy_dm_o_data1[2] <= ddrphy_dfi_p0_wrdata_mask[8];
+ ddrphy_dm_o_data1[3] <= ddrphy_dfi_p0_wrdata_mask[12];
+ ddrphy_dm_o_data1[4] <= ddrphy_dfi_p1_wrdata_mask[0];
+ ddrphy_dm_o_data1[5] <= ddrphy_dfi_p1_wrdata_mask[4];
+ ddrphy_dm_o_data1[6] <= ddrphy_dfi_p1_wrdata_mask[8];
+ ddrphy_dm_o_data1[7] <= ddrphy_dfi_p1_wrdata_mask[12];
+end
+always @(*) begin
+ ddrphy_dq_o_data8 <= 8'd0;
+ ddrphy_dq_o_data8[0] <= ddrphy_dfi_p0_wrdata[8];
+ ddrphy_dq_o_data8[1] <= ddrphy_dfi_p0_wrdata[40];
+ ddrphy_dq_o_data8[2] <= ddrphy_dfi_p0_wrdata[72];
+ ddrphy_dq_o_data8[3] <= ddrphy_dfi_p0_wrdata[104];
+ ddrphy_dq_o_data8[4] <= ddrphy_dfi_p1_wrdata[8];
+ ddrphy_dq_o_data8[5] <= ddrphy_dfi_p1_wrdata[40];
+ ddrphy_dq_o_data8[6] <= ddrphy_dfi_p1_wrdata[72];
+ ddrphy_dq_o_data8[7] <= ddrphy_dfi_p1_wrdata[104];
+end
+assign ddrphy_dq_i_data8 = {ddrphy_bitslip8_o, ddrphy_dq_i_bitslip_o_d8};
+always @(*) begin
+ ddrphy_dq_o_data9 <= 8'd0;
+ ddrphy_dq_o_data9[0] <= ddrphy_dfi_p0_wrdata[9];
+ ddrphy_dq_o_data9[1] <= ddrphy_dfi_p0_wrdata[41];
+ ddrphy_dq_o_data9[2] <= ddrphy_dfi_p0_wrdata[73];
+ ddrphy_dq_o_data9[3] <= ddrphy_dfi_p0_wrdata[105];
+ ddrphy_dq_o_data9[4] <= ddrphy_dfi_p1_wrdata[9];
+ ddrphy_dq_o_data9[5] <= ddrphy_dfi_p1_wrdata[41];
+ ddrphy_dq_o_data9[6] <= ddrphy_dfi_p1_wrdata[73];
+ ddrphy_dq_o_data9[7] <= ddrphy_dfi_p1_wrdata[105];
+end
+assign ddrphy_dq_i_data9 = {ddrphy_bitslip9_o, ddrphy_dq_i_bitslip_o_d9};
+always @(*) begin
+ ddrphy_dq_o_data10 <= 8'd0;
+ ddrphy_dq_o_data10[0] <= ddrphy_dfi_p0_wrdata[10];
+ ddrphy_dq_o_data10[1] <= ddrphy_dfi_p0_wrdata[42];
+ ddrphy_dq_o_data10[2] <= ddrphy_dfi_p0_wrdata[74];
+ ddrphy_dq_o_data10[3] <= ddrphy_dfi_p0_wrdata[106];
+ ddrphy_dq_o_data10[4] <= ddrphy_dfi_p1_wrdata[10];
+ ddrphy_dq_o_data10[5] <= ddrphy_dfi_p1_wrdata[42];
+ ddrphy_dq_o_data10[6] <= ddrphy_dfi_p1_wrdata[74];
+ ddrphy_dq_o_data10[7] <= ddrphy_dfi_p1_wrdata[106];
+end
+assign ddrphy_dq_i_data10 = {ddrphy_bitslip10_o, ddrphy_dq_i_bitslip_o_d10};
+always @(*) begin
+ ddrphy_dq_o_data11 <= 8'd0;
+ ddrphy_dq_o_data11[0] <= ddrphy_dfi_p0_wrdata[11];
+ ddrphy_dq_o_data11[1] <= ddrphy_dfi_p0_wrdata[43];
+ ddrphy_dq_o_data11[2] <= ddrphy_dfi_p0_wrdata[75];
+ ddrphy_dq_o_data11[3] <= ddrphy_dfi_p0_wrdata[107];
+ ddrphy_dq_o_data11[4] <= ddrphy_dfi_p1_wrdata[11];
+ ddrphy_dq_o_data11[5] <= ddrphy_dfi_p1_wrdata[43];
+ ddrphy_dq_o_data11[6] <= ddrphy_dfi_p1_wrdata[75];
+ ddrphy_dq_o_data11[7] <= ddrphy_dfi_p1_wrdata[107];
+end
+assign ddrphy_dq_i_data11 = {ddrphy_bitslip11_o, ddrphy_dq_i_bitslip_o_d11};
+always @(*) begin
+ ddrphy_dq_o_data12 <= 8'd0;
+ ddrphy_dq_o_data12[0] <= ddrphy_dfi_p0_wrdata[12];
+ ddrphy_dq_o_data12[1] <= ddrphy_dfi_p0_wrdata[44];
+ ddrphy_dq_o_data12[2] <= ddrphy_dfi_p0_wrdata[76];
+ ddrphy_dq_o_data12[3] <= ddrphy_dfi_p0_wrdata[108];
+ ddrphy_dq_o_data12[4] <= ddrphy_dfi_p1_wrdata[12];
+ ddrphy_dq_o_data12[5] <= ddrphy_dfi_p1_wrdata[44];
+ ddrphy_dq_o_data12[6] <= ddrphy_dfi_p1_wrdata[76];
+ ddrphy_dq_o_data12[7] <= ddrphy_dfi_p1_wrdata[108];
+end
+assign ddrphy_dq_i_data12 = {ddrphy_bitslip12_o, ddrphy_dq_i_bitslip_o_d12};
+always @(*) begin
+ ddrphy_dq_o_data13 <= 8'd0;
+ ddrphy_dq_o_data13[0] <= ddrphy_dfi_p0_wrdata[13];
+ ddrphy_dq_o_data13[1] <= ddrphy_dfi_p0_wrdata[45];
+ ddrphy_dq_o_data13[2] <= ddrphy_dfi_p0_wrdata[77];
+ ddrphy_dq_o_data13[3] <= ddrphy_dfi_p0_wrdata[109];
+ ddrphy_dq_o_data13[4] <= ddrphy_dfi_p1_wrdata[13];
+ ddrphy_dq_o_data13[5] <= ddrphy_dfi_p1_wrdata[45];
+ ddrphy_dq_o_data13[6] <= ddrphy_dfi_p1_wrdata[77];
+ ddrphy_dq_o_data13[7] <= ddrphy_dfi_p1_wrdata[109];
+end
+assign ddrphy_dq_i_data13 = {ddrphy_bitslip13_o, ddrphy_dq_i_bitslip_o_d13};
+always @(*) begin
+ ddrphy_dq_o_data14 <= 8'd0;
+ ddrphy_dq_o_data14[0] <= ddrphy_dfi_p0_wrdata[14];
+ ddrphy_dq_o_data14[1] <= ddrphy_dfi_p0_wrdata[46];
+ ddrphy_dq_o_data14[2] <= ddrphy_dfi_p0_wrdata[78];
+ ddrphy_dq_o_data14[3] <= ddrphy_dfi_p0_wrdata[110];
+ ddrphy_dq_o_data14[4] <= ddrphy_dfi_p1_wrdata[14];
+ ddrphy_dq_o_data14[5] <= ddrphy_dfi_p1_wrdata[46];
+ ddrphy_dq_o_data14[6] <= ddrphy_dfi_p1_wrdata[78];
+ ddrphy_dq_o_data14[7] <= ddrphy_dfi_p1_wrdata[110];
+end
+assign ddrphy_dq_i_data14 = {ddrphy_bitslip14_o, ddrphy_dq_i_bitslip_o_d14};
+always @(*) begin
+ ddrphy_dq_o_data15 <= 8'd0;
+ ddrphy_dq_o_data15[0] <= ddrphy_dfi_p0_wrdata[15];
+ ddrphy_dq_o_data15[1] <= ddrphy_dfi_p0_wrdata[47];
+ ddrphy_dq_o_data15[2] <= ddrphy_dfi_p0_wrdata[79];
+ ddrphy_dq_o_data15[3] <= ddrphy_dfi_p0_wrdata[111];
+ ddrphy_dq_o_data15[4] <= ddrphy_dfi_p1_wrdata[15];
+ ddrphy_dq_o_data15[5] <= ddrphy_dfi_p1_wrdata[47];
+ ddrphy_dq_o_data15[6] <= ddrphy_dfi_p1_wrdata[79];
+ ddrphy_dq_o_data15[7] <= ddrphy_dfi_p1_wrdata[111];
+end
+assign ddrphy_dq_i_data15 = {ddrphy_bitslip15_o, ddrphy_dq_i_bitslip_o_d15};
+always @(*) begin
+ ddrphy_dm_o_data2 <= 8'd0;
+ ddrphy_dm_o_data2[0] <= ddrphy_dfi_p0_wrdata_mask[2];
+ ddrphy_dm_o_data2[1] <= ddrphy_dfi_p0_wrdata_mask[6];
+ ddrphy_dm_o_data2[2] <= ddrphy_dfi_p0_wrdata_mask[10];
+ ddrphy_dm_o_data2[3] <= ddrphy_dfi_p0_wrdata_mask[14];
+ ddrphy_dm_o_data2[4] <= ddrphy_dfi_p1_wrdata_mask[2];
+ ddrphy_dm_o_data2[5] <= ddrphy_dfi_p1_wrdata_mask[6];
+ ddrphy_dm_o_data2[6] <= ddrphy_dfi_p1_wrdata_mask[10];
+ ddrphy_dm_o_data2[7] <= ddrphy_dfi_p1_wrdata_mask[14];
+end
+always @(*) begin
+ ddrphy_dq_o_data16 <= 8'd0;
+ ddrphy_dq_o_data16[0] <= ddrphy_dfi_p0_wrdata[16];
+ ddrphy_dq_o_data16[1] <= ddrphy_dfi_p0_wrdata[48];
+ ddrphy_dq_o_data16[2] <= ddrphy_dfi_p0_wrdata[80];
+ ddrphy_dq_o_data16[3] <= ddrphy_dfi_p0_wrdata[112];
+ ddrphy_dq_o_data16[4] <= ddrphy_dfi_p1_wrdata[16];
+ ddrphy_dq_o_data16[5] <= ddrphy_dfi_p1_wrdata[48];
+ ddrphy_dq_o_data16[6] <= ddrphy_dfi_p1_wrdata[80];
+ ddrphy_dq_o_data16[7] <= ddrphy_dfi_p1_wrdata[112];
+end
+assign ddrphy_dq_i_data16 = {ddrphy_bitslip16_o, ddrphy_dq_i_bitslip_o_d16};
+always @(*) begin
+ ddrphy_dq_o_data17 <= 8'd0;
+ ddrphy_dq_o_data17[0] <= ddrphy_dfi_p0_wrdata[17];
+ ddrphy_dq_o_data17[1] <= ddrphy_dfi_p0_wrdata[49];
+ ddrphy_dq_o_data17[2] <= ddrphy_dfi_p0_wrdata[81];
+ ddrphy_dq_o_data17[3] <= ddrphy_dfi_p0_wrdata[113];
+ ddrphy_dq_o_data17[4] <= ddrphy_dfi_p1_wrdata[17];
+ ddrphy_dq_o_data17[5] <= ddrphy_dfi_p1_wrdata[49];
+ ddrphy_dq_o_data17[6] <= ddrphy_dfi_p1_wrdata[81];
+ ddrphy_dq_o_data17[7] <= ddrphy_dfi_p1_wrdata[113];
+end
+assign ddrphy_dq_i_data17 = {ddrphy_bitslip17_o, ddrphy_dq_i_bitslip_o_d17};
+always @(*) begin
+ ddrphy_dq_o_data18 <= 8'd0;
+ ddrphy_dq_o_data18[0] <= ddrphy_dfi_p0_wrdata[18];
+ ddrphy_dq_o_data18[1] <= ddrphy_dfi_p0_wrdata[50];
+ ddrphy_dq_o_data18[2] <= ddrphy_dfi_p0_wrdata[82];
+ ddrphy_dq_o_data18[3] <= ddrphy_dfi_p0_wrdata[114];
+ ddrphy_dq_o_data18[4] <= ddrphy_dfi_p1_wrdata[18];
+ ddrphy_dq_o_data18[5] <= ddrphy_dfi_p1_wrdata[50];
+ ddrphy_dq_o_data18[6] <= ddrphy_dfi_p1_wrdata[82];
+ ddrphy_dq_o_data18[7] <= ddrphy_dfi_p1_wrdata[114];
+end
+assign ddrphy_dq_i_data18 = {ddrphy_bitslip18_o, ddrphy_dq_i_bitslip_o_d18};
+always @(*) begin
+ ddrphy_dq_o_data19 <= 8'd0;
+ ddrphy_dq_o_data19[0] <= ddrphy_dfi_p0_wrdata[19];
+ ddrphy_dq_o_data19[1] <= ddrphy_dfi_p0_wrdata[51];
+ ddrphy_dq_o_data19[2] <= ddrphy_dfi_p0_wrdata[83];
+ ddrphy_dq_o_data19[3] <= ddrphy_dfi_p0_wrdata[115];
+ ddrphy_dq_o_data19[4] <= ddrphy_dfi_p1_wrdata[19];
+ ddrphy_dq_o_data19[5] <= ddrphy_dfi_p1_wrdata[51];
+ ddrphy_dq_o_data19[6] <= ddrphy_dfi_p1_wrdata[83];
+ ddrphy_dq_o_data19[7] <= ddrphy_dfi_p1_wrdata[115];
+end
+assign ddrphy_dq_i_data19 = {ddrphy_bitslip19_o, ddrphy_dq_i_bitslip_o_d19};
+always @(*) begin
+ ddrphy_dq_o_data20 <= 8'd0;
+ ddrphy_dq_o_data20[0] <= ddrphy_dfi_p0_wrdata[20];
+ ddrphy_dq_o_data20[1] <= ddrphy_dfi_p0_wrdata[52];
+ ddrphy_dq_o_data20[2] <= ddrphy_dfi_p0_wrdata[84];
+ ddrphy_dq_o_data20[3] <= ddrphy_dfi_p0_wrdata[116];
+ ddrphy_dq_o_data20[4] <= ddrphy_dfi_p1_wrdata[20];
+ ddrphy_dq_o_data20[5] <= ddrphy_dfi_p1_wrdata[52];
+ ddrphy_dq_o_data20[6] <= ddrphy_dfi_p1_wrdata[84];
+ ddrphy_dq_o_data20[7] <= ddrphy_dfi_p1_wrdata[116];
+end
+assign ddrphy_dq_i_data20 = {ddrphy_bitslip20_o, ddrphy_dq_i_bitslip_o_d20};
+always @(*) begin
+ ddrphy_dq_o_data21 <= 8'd0;
+ ddrphy_dq_o_data21[0] <= ddrphy_dfi_p0_wrdata[21];
+ ddrphy_dq_o_data21[1] <= ddrphy_dfi_p0_wrdata[53];
+ ddrphy_dq_o_data21[2] <= ddrphy_dfi_p0_wrdata[85];
+ ddrphy_dq_o_data21[3] <= ddrphy_dfi_p0_wrdata[117];
+ ddrphy_dq_o_data21[4] <= ddrphy_dfi_p1_wrdata[21];
+ ddrphy_dq_o_data21[5] <= ddrphy_dfi_p1_wrdata[53];
+ ddrphy_dq_o_data21[6] <= ddrphy_dfi_p1_wrdata[85];
+ ddrphy_dq_o_data21[7] <= ddrphy_dfi_p1_wrdata[117];
+end
+assign ddrphy_dq_i_data21 = {ddrphy_bitslip21_o, ddrphy_dq_i_bitslip_o_d21};
+always @(*) begin
+ ddrphy_dq_o_data22 <= 8'd0;
+ ddrphy_dq_o_data22[0] <= ddrphy_dfi_p0_wrdata[22];
+ ddrphy_dq_o_data22[1] <= ddrphy_dfi_p0_wrdata[54];
+ ddrphy_dq_o_data22[2] <= ddrphy_dfi_p0_wrdata[86];
+ ddrphy_dq_o_data22[3] <= ddrphy_dfi_p0_wrdata[118];
+ ddrphy_dq_o_data22[4] <= ddrphy_dfi_p1_wrdata[22];
+ ddrphy_dq_o_data22[5] <= ddrphy_dfi_p1_wrdata[54];
+ ddrphy_dq_o_data22[6] <= ddrphy_dfi_p1_wrdata[86];
+ ddrphy_dq_o_data22[7] <= ddrphy_dfi_p1_wrdata[118];
+end
+assign ddrphy_dq_i_data22 = {ddrphy_bitslip22_o, ddrphy_dq_i_bitslip_o_d22};
+always @(*) begin
+ ddrphy_dq_o_data23 <= 8'd0;
+ ddrphy_dq_o_data23[0] <= ddrphy_dfi_p0_wrdata[23];
+ ddrphy_dq_o_data23[1] <= ddrphy_dfi_p0_wrdata[55];
+ ddrphy_dq_o_data23[2] <= ddrphy_dfi_p0_wrdata[87];
+ ddrphy_dq_o_data23[3] <= ddrphy_dfi_p0_wrdata[119];
+ ddrphy_dq_o_data23[4] <= ddrphy_dfi_p1_wrdata[23];
+ ddrphy_dq_o_data23[5] <= ddrphy_dfi_p1_wrdata[55];
+ ddrphy_dq_o_data23[6] <= ddrphy_dfi_p1_wrdata[87];
+ ddrphy_dq_o_data23[7] <= ddrphy_dfi_p1_wrdata[119];
+end
+assign ddrphy_dq_i_data23 = {ddrphy_bitslip23_o, ddrphy_dq_i_bitslip_o_d23};
+always @(*) begin
+ ddrphy_dm_o_data3 <= 8'd0;
+ ddrphy_dm_o_data3[0] <= ddrphy_dfi_p0_wrdata_mask[3];
+ ddrphy_dm_o_data3[1] <= ddrphy_dfi_p0_wrdata_mask[7];
+ ddrphy_dm_o_data3[2] <= ddrphy_dfi_p0_wrdata_mask[11];
+ ddrphy_dm_o_data3[3] <= ddrphy_dfi_p0_wrdata_mask[15];
+ ddrphy_dm_o_data3[4] <= ddrphy_dfi_p1_wrdata_mask[3];
+ ddrphy_dm_o_data3[5] <= ddrphy_dfi_p1_wrdata_mask[7];
+ ddrphy_dm_o_data3[6] <= ddrphy_dfi_p1_wrdata_mask[11];
+ ddrphy_dm_o_data3[7] <= ddrphy_dfi_p1_wrdata_mask[15];
+end
+always @(*) begin
+ ddrphy_dq_o_data24 <= 8'd0;
+ ddrphy_dq_o_data24[0] <= ddrphy_dfi_p0_wrdata[24];
+ ddrphy_dq_o_data24[1] <= ddrphy_dfi_p0_wrdata[56];
+ ddrphy_dq_o_data24[2] <= ddrphy_dfi_p0_wrdata[88];
+ ddrphy_dq_o_data24[3] <= ddrphy_dfi_p0_wrdata[120];
+ ddrphy_dq_o_data24[4] <= ddrphy_dfi_p1_wrdata[24];
+ ddrphy_dq_o_data24[5] <= ddrphy_dfi_p1_wrdata[56];
+ ddrphy_dq_o_data24[6] <= ddrphy_dfi_p1_wrdata[88];
+ ddrphy_dq_o_data24[7] <= ddrphy_dfi_p1_wrdata[120];
+end
+assign ddrphy_dq_i_data24 = {ddrphy_bitslip24_o, ddrphy_dq_i_bitslip_o_d24};
+always @(*) begin
+ ddrphy_dq_o_data25 <= 8'd0;
+ ddrphy_dq_o_data25[0] <= ddrphy_dfi_p0_wrdata[25];
+ ddrphy_dq_o_data25[1] <= ddrphy_dfi_p0_wrdata[57];
+ ddrphy_dq_o_data25[2] <= ddrphy_dfi_p0_wrdata[89];
+ ddrphy_dq_o_data25[3] <= ddrphy_dfi_p0_wrdata[121];
+ ddrphy_dq_o_data25[4] <= ddrphy_dfi_p1_wrdata[25];
+ ddrphy_dq_o_data25[5] <= ddrphy_dfi_p1_wrdata[57];
+ ddrphy_dq_o_data25[6] <= ddrphy_dfi_p1_wrdata[89];
+ ddrphy_dq_o_data25[7] <= ddrphy_dfi_p1_wrdata[121];
+end
+assign ddrphy_dq_i_data25 = {ddrphy_bitslip25_o, ddrphy_dq_i_bitslip_o_d25};
+always @(*) begin
+ ddrphy_dq_o_data26 <= 8'd0;
+ ddrphy_dq_o_data26[0] <= ddrphy_dfi_p0_wrdata[26];
+ ddrphy_dq_o_data26[1] <= ddrphy_dfi_p0_wrdata[58];
+ ddrphy_dq_o_data26[2] <= ddrphy_dfi_p0_wrdata[90];
+ ddrphy_dq_o_data26[3] <= ddrphy_dfi_p0_wrdata[122];
+ ddrphy_dq_o_data26[4] <= ddrphy_dfi_p1_wrdata[26];
+ ddrphy_dq_o_data26[5] <= ddrphy_dfi_p1_wrdata[58];
+ ddrphy_dq_o_data26[6] <= ddrphy_dfi_p1_wrdata[90];
+ ddrphy_dq_o_data26[7] <= ddrphy_dfi_p1_wrdata[122];
+end
+assign ddrphy_dq_i_data26 = {ddrphy_bitslip26_o, ddrphy_dq_i_bitslip_o_d26};
+always @(*) begin
+ ddrphy_dq_o_data27 <= 8'd0;
+ ddrphy_dq_o_data27[0] <= ddrphy_dfi_p0_wrdata[27];
+ ddrphy_dq_o_data27[1] <= ddrphy_dfi_p0_wrdata[59];
+ ddrphy_dq_o_data27[2] <= ddrphy_dfi_p0_wrdata[91];
+ ddrphy_dq_o_data27[3] <= ddrphy_dfi_p0_wrdata[123];
+ ddrphy_dq_o_data27[4] <= ddrphy_dfi_p1_wrdata[27];
+ ddrphy_dq_o_data27[5] <= ddrphy_dfi_p1_wrdata[59];
+ ddrphy_dq_o_data27[6] <= ddrphy_dfi_p1_wrdata[91];
+ ddrphy_dq_o_data27[7] <= ddrphy_dfi_p1_wrdata[123];
+end
+assign ddrphy_dq_i_data27 = {ddrphy_bitslip27_o, ddrphy_dq_i_bitslip_o_d27};
+always @(*) begin
+ ddrphy_dq_o_data28 <= 8'd0;
+ ddrphy_dq_o_data28[0] <= ddrphy_dfi_p0_wrdata[28];
+ ddrphy_dq_o_data28[1] <= ddrphy_dfi_p0_wrdata[60];
+ ddrphy_dq_o_data28[2] <= ddrphy_dfi_p0_wrdata[92];
+ ddrphy_dq_o_data28[3] <= ddrphy_dfi_p0_wrdata[124];
+ ddrphy_dq_o_data28[4] <= ddrphy_dfi_p1_wrdata[28];
+ ddrphy_dq_o_data28[5] <= ddrphy_dfi_p1_wrdata[60];
+ ddrphy_dq_o_data28[6] <= ddrphy_dfi_p1_wrdata[92];
+ ddrphy_dq_o_data28[7] <= ddrphy_dfi_p1_wrdata[124];
+end
+assign ddrphy_dq_i_data28 = {ddrphy_bitslip28_o, ddrphy_dq_i_bitslip_o_d28};
+always @(*) begin
+ ddrphy_dq_o_data29 <= 8'd0;
+ ddrphy_dq_o_data29[0] <= ddrphy_dfi_p0_wrdata[29];
+ ddrphy_dq_o_data29[1] <= ddrphy_dfi_p0_wrdata[61];
+ ddrphy_dq_o_data29[2] <= ddrphy_dfi_p0_wrdata[93];
+ ddrphy_dq_o_data29[3] <= ddrphy_dfi_p0_wrdata[125];
+ ddrphy_dq_o_data29[4] <= ddrphy_dfi_p1_wrdata[29];
+ ddrphy_dq_o_data29[5] <= ddrphy_dfi_p1_wrdata[61];
+ ddrphy_dq_o_data29[6] <= ddrphy_dfi_p1_wrdata[93];
+ ddrphy_dq_o_data29[7] <= ddrphy_dfi_p1_wrdata[125];
+end
+assign ddrphy_dq_i_data29 = {ddrphy_bitslip29_o, ddrphy_dq_i_bitslip_o_d29};
+always @(*) begin
+ ddrphy_dq_o_data30 <= 8'd0;
+ ddrphy_dq_o_data30[0] <= ddrphy_dfi_p0_wrdata[30];
+ ddrphy_dq_o_data30[1] <= ddrphy_dfi_p0_wrdata[62];
+ ddrphy_dq_o_data30[2] <= ddrphy_dfi_p0_wrdata[94];
+ ddrphy_dq_o_data30[3] <= ddrphy_dfi_p0_wrdata[126];
+ ddrphy_dq_o_data30[4] <= ddrphy_dfi_p1_wrdata[30];
+ ddrphy_dq_o_data30[5] <= ddrphy_dfi_p1_wrdata[62];
+ ddrphy_dq_o_data30[6] <= ddrphy_dfi_p1_wrdata[94];
+ ddrphy_dq_o_data30[7] <= ddrphy_dfi_p1_wrdata[126];
+end
+assign ddrphy_dq_i_data30 = {ddrphy_bitslip30_o, ddrphy_dq_i_bitslip_o_d30};
+always @(*) begin
+ ddrphy_dq_o_data31 <= 8'd0;
+ ddrphy_dq_o_data31[0] <= ddrphy_dfi_p0_wrdata[31];
+ ddrphy_dq_o_data31[1] <= ddrphy_dfi_p0_wrdata[63];
+ ddrphy_dq_o_data31[2] <= ddrphy_dfi_p0_wrdata[95];
+ ddrphy_dq_o_data31[3] <= ddrphy_dfi_p0_wrdata[127];
+ ddrphy_dq_o_data31[4] <= ddrphy_dfi_p1_wrdata[31];
+ ddrphy_dq_o_data31[5] <= ddrphy_dfi_p1_wrdata[63];
+ ddrphy_dq_o_data31[6] <= ddrphy_dfi_p1_wrdata[95];
+ ddrphy_dq_o_data31[7] <= ddrphy_dfi_p1_wrdata[127];
+end
+assign ddrphy_dq_i_data31 = {ddrphy_bitslip31_o, ddrphy_dq_i_bitslip_o_d31};
+assign ddrphy_dfi_p0_rddata_valid = ddrphy_rddata_en_tappeddelayline12;
+assign ddrphy_dfi_p1_rddata_valid = ddrphy_rddata_en_tappeddelayline12;
+assign ddrphy_dqs_re = (ddrphy_rddata_en_tappeddelayline3 | ddrphy_rddata_en_tappeddelayline4);
+assign ddrphy_dq_oe = (ddrphy_wrdata_en_tappeddelayline3 | ddrphy_wrdata_en_tappeddelayline4);
+assign ddrphy_bl8_chunk = ddrphy_wrdata_en_tappeddelayline3;
+assign ddrphy_dqs_oe = ddrphy_dq_oe;
+assign ddrphy_dqs_preamble = (ddrphy_wrdata_en_tappeddelayline2 & (~ddrphy_wrdata_en_tappeddelayline3));
+assign ddrphy_dqs_postamble = (ddrphy_wrdata_en_tappeddelayline5 & (~ddrphy_wrdata_en_tappeddelayline4));
+assign ddrphy_new_lock = (ddrphy_lock1 & (~ddrphy_lock_d));
+assign ddrphy_pause0 = ddrphy_pause1;
+assign ddrphy_stop0 = ddrphy_stop1;
+assign ddrphy_delay0 = ddrphy_delay1;
+assign ddrphy_reset0 = ddrphy_reset1;
+always @(*) begin
+ ddrphy_bitslip0_o <= 4'd0;
+ case (ddrphy_bitslip0_value)
+ 1'd0: begin
+ ddrphy_bitslip0_o <= ddrphy_bitslip0_r[3:0];
+ end
+ 1'd1: begin
+ ddrphy_bitslip0_o <= ddrphy_bitslip0_r[4:1];
+ end
+ 2'd2: begin
+ ddrphy_bitslip0_o <= ddrphy_bitslip0_r[5:2];
+ end
+ 2'd3: begin
+ ddrphy_bitslip0_o <= ddrphy_bitslip0_r[6:3];
+ end
+ endcase
+end
+always @(*) begin
+ ddrphy_bitslip1_o <= 4'd0;
+ case (ddrphy_bitslip1_value)
+ 1'd0: begin
+ ddrphy_bitslip1_o <= ddrphy_bitslip1_r[3:0];
+ end
+ 1'd1: begin
+ ddrphy_bitslip1_o <= ddrphy_bitslip1_r[4:1];
+ end
+ 2'd2: begin
+ ddrphy_bitslip1_o <= ddrphy_bitslip1_r[5:2];
+ end
+ 2'd3: begin
+ ddrphy_bitslip1_o <= ddrphy_bitslip1_r[6:3];
+ end
+ endcase
+end
+always @(*) begin
+ ddrphy_bitslip2_o <= 4'd0;
+ case (ddrphy_bitslip2_value)
+ 1'd0: begin
+ ddrphy_bitslip2_o <= ddrphy_bitslip2_r[3:0];
+ end
+ 1'd1: begin
+ ddrphy_bitslip2_o <= ddrphy_bitslip2_r[4:1];
+ end
+ 2'd2: begin
+ ddrphy_bitslip2_o <= ddrphy_bitslip2_r[5:2];
+ end
+ 2'd3: begin
+ ddrphy_bitslip2_o <= ddrphy_bitslip2_r[6:3];
+ end
+ endcase
+end
+always @(*) begin
+ ddrphy_bitslip3_o <= 4'd0;
+ case (ddrphy_bitslip3_value)
+ 1'd0: begin
+ ddrphy_bitslip3_o <= ddrphy_bitslip3_r[3:0];
+ end
+ 1'd1: begin
+ ddrphy_bitslip3_o <= ddrphy_bitslip3_r[4:1];
+ end
+ 2'd2: begin
+ ddrphy_bitslip3_o <= ddrphy_bitslip3_r[5:2];
+ end
+ 2'd3: begin
+ ddrphy_bitslip3_o <= ddrphy_bitslip3_r[6:3];
+ end
+ endcase
+end
+always @(*) begin
+ ddrphy_bitslip4_o <= 4'd0;
+ case (ddrphy_bitslip4_value)
+ 1'd0: begin
+ ddrphy_bitslip4_o <= ddrphy_bitslip4_r[3:0];
+ end
+ 1'd1: begin
+ ddrphy_bitslip4_o <= ddrphy_bitslip4_r[4:1];
+ end
+ 2'd2: begin
+ ddrphy_bitslip4_o <= ddrphy_bitslip4_r[5:2];
+ end
+ 2'd3: begin
+ ddrphy_bitslip4_o <= ddrphy_bitslip4_r[6:3];
+ end
+ endcase
+end
+always @(*) begin
+ ddrphy_bitslip5_o <= 4'd0;
+ case (ddrphy_bitslip5_value)
+ 1'd0: begin
+ ddrphy_bitslip5_o <= ddrphy_bitslip5_r[3:0];
+ end
+ 1'd1: begin
+ ddrphy_bitslip5_o <= ddrphy_bitslip5_r[4:1];
+ end
+ 2'd2: begin
+ ddrphy_bitslip5_o <= ddrphy_bitslip5_r[5:2];
+ end
+ 2'd3: begin
+ ddrphy_bitslip5_o <= ddrphy_bitslip5_r[6:3];
+ end
+ endcase
+end
+always @(*) begin
+ ddrphy_bitslip6_o <= 4'd0;
+ case (ddrphy_bitslip6_value)
+ 1'd0: begin
+ ddrphy_bitslip6_o <= ddrphy_bitslip6_r[3:0];
+ end
+ 1'd1: begin
+ ddrphy_bitslip6_o <= ddrphy_bitslip6_r[4:1];
+ end
+ 2'd2: begin
+ ddrphy_bitslip6_o <= ddrphy_bitslip6_r[5:2];
+ end
+ 2'd3: begin
+ ddrphy_bitslip6_o <= ddrphy_bitslip6_r[6:3];
+ end
+ endcase
+end
+always @(*) begin
+ ddrphy_bitslip7_o <= 4'd0;
+ case (ddrphy_bitslip7_value)
+ 1'd0: begin
+ ddrphy_bitslip7_o <= ddrphy_bitslip7_r[3:0];
+ end
+ 1'd1: begin
+ ddrphy_bitslip7_o <= ddrphy_bitslip7_r[4:1];
+ end
+ 2'd2: begin
+ ddrphy_bitslip7_o <= ddrphy_bitslip7_r[5:2];
+ end
+ 2'd3: begin
+ ddrphy_bitslip7_o <= ddrphy_bitslip7_r[6:3];
+ end
+ endcase
+end
+always @(*) begin
+ ddrphy_bitslip8_o <= 4'd0;
+ case (ddrphy_bitslip8_value)
+ 1'd0: begin
+ ddrphy_bitslip8_o <= ddrphy_bitslip8_r[3:0];
+ end
+ 1'd1: begin
+ ddrphy_bitslip8_o <= ddrphy_bitslip8_r[4:1];
+ end
+ 2'd2: begin
+ ddrphy_bitslip8_o <= ddrphy_bitslip8_r[5:2];
+ end
+ 2'd3: begin
+ ddrphy_bitslip8_o <= ddrphy_bitslip8_r[6:3];
+ end
+ endcase
+end
+always @(*) begin
+ ddrphy_bitslip9_o <= 4'd0;
+ case (ddrphy_bitslip9_value)
+ 1'd0: begin
+ ddrphy_bitslip9_o <= ddrphy_bitslip9_r[3:0];
+ end
+ 1'd1: begin
+ ddrphy_bitslip9_o <= ddrphy_bitslip9_r[4:1];
+ end
+ 2'd2: begin
+ ddrphy_bitslip9_o <= ddrphy_bitslip9_r[5:2];
+ end
+ 2'd3: begin
+ ddrphy_bitslip9_o <= ddrphy_bitslip9_r[6:3];
+ end
+ endcase
+end
+always @(*) begin
+ ddrphy_bitslip10_o <= 4'd0;
+ case (ddrphy_bitslip10_value)
+ 1'd0: begin
+ ddrphy_bitslip10_o <= ddrphy_bitslip10_r[3:0];
+ end
+ 1'd1: begin
+ ddrphy_bitslip10_o <= ddrphy_bitslip10_r[4:1];
+ end
+ 2'd2: begin
+ ddrphy_bitslip10_o <= ddrphy_bitslip10_r[5:2];
+ end
+ 2'd3: begin
+ ddrphy_bitslip10_o <= ddrphy_bitslip10_r[6:3];
+ end
+ endcase
+end
+always @(*) begin
+ ddrphy_bitslip11_o <= 4'd0;
+ case (ddrphy_bitslip11_value)
+ 1'd0: begin
+ ddrphy_bitslip11_o <= ddrphy_bitslip11_r[3:0];
+ end
+ 1'd1: begin
+ ddrphy_bitslip11_o <= ddrphy_bitslip11_r[4:1];
+ end
+ 2'd2: begin
+ ddrphy_bitslip11_o <= ddrphy_bitslip11_r[5:2];
+ end
+ 2'd3: begin
+ ddrphy_bitslip11_o <= ddrphy_bitslip11_r[6:3];
+ end
+ endcase
+end
+always @(*) begin
+ ddrphy_bitslip12_o <= 4'd0;
+ case (ddrphy_bitslip12_value)
+ 1'd0: begin
+ ddrphy_bitslip12_o <= ddrphy_bitslip12_r[3:0];
+ end
+ 1'd1: begin
+ ddrphy_bitslip12_o <= ddrphy_bitslip12_r[4:1];
+ end
+ 2'd2: begin
+ ddrphy_bitslip12_o <= ddrphy_bitslip12_r[5:2];
+ end
+ 2'd3: begin
+ ddrphy_bitslip12_o <= ddrphy_bitslip12_r[6:3];
+ end
+ endcase
+end
+always @(*) begin
+ ddrphy_bitslip13_o <= 4'd0;
+ case (ddrphy_bitslip13_value)
+ 1'd0: begin
+ ddrphy_bitslip13_o <= ddrphy_bitslip13_r[3:0];
+ end
+ 1'd1: begin
+ ddrphy_bitslip13_o <= ddrphy_bitslip13_r[4:1];
+ end
+ 2'd2: begin
+ ddrphy_bitslip13_o <= ddrphy_bitslip13_r[5:2];
+ end
+ 2'd3: begin
+ ddrphy_bitslip13_o <= ddrphy_bitslip13_r[6:3];
+ end
+ endcase
+end
+always @(*) begin
+ ddrphy_bitslip14_o <= 4'd0;
+ case (ddrphy_bitslip14_value)
+ 1'd0: begin
+ ddrphy_bitslip14_o <= ddrphy_bitslip14_r[3:0];
+ end
+ 1'd1: begin
+ ddrphy_bitslip14_o <= ddrphy_bitslip14_r[4:1];
+ end
+ 2'd2: begin
+ ddrphy_bitslip14_o <= ddrphy_bitslip14_r[5:2];
+ end
+ 2'd3: begin
+ ddrphy_bitslip14_o <= ddrphy_bitslip14_r[6:3];
+ end
+ endcase
+end
+always @(*) begin
+ ddrphy_bitslip15_o <= 4'd0;
+ case (ddrphy_bitslip15_value)
+ 1'd0: begin
+ ddrphy_bitslip15_o <= ddrphy_bitslip15_r[3:0];
+ end
+ 1'd1: begin
+ ddrphy_bitslip15_o <= ddrphy_bitslip15_r[4:1];
+ end
+ 2'd2: begin
+ ddrphy_bitslip15_o <= ddrphy_bitslip15_r[5:2];
+ end
+ 2'd3: begin
+ ddrphy_bitslip15_o <= ddrphy_bitslip15_r[6:3];
+ end
+ endcase
+end
+always @(*) begin
+ ddrphy_bitslip16_o <= 4'd0;
+ case (ddrphy_bitslip16_value)
+ 1'd0: begin
+ ddrphy_bitslip16_o <= ddrphy_bitslip16_r[3:0];
+ end
+ 1'd1: begin
+ ddrphy_bitslip16_o <= ddrphy_bitslip16_r[4:1];
+ end
+ 2'd2: begin
+ ddrphy_bitslip16_o <= ddrphy_bitslip16_r[5:2];
+ end
+ 2'd3: begin
+ ddrphy_bitslip16_o <= ddrphy_bitslip16_r[6:3];
+ end
+ endcase
+end
+always @(*) begin
+ ddrphy_bitslip17_o <= 4'd0;
+ case (ddrphy_bitslip17_value)
+ 1'd0: begin
+ ddrphy_bitslip17_o <= ddrphy_bitslip17_r[3:0];
+ end
+ 1'd1: begin
+ ddrphy_bitslip17_o <= ddrphy_bitslip17_r[4:1];
+ end
+ 2'd2: begin
+ ddrphy_bitslip17_o <= ddrphy_bitslip17_r[5:2];
+ end
+ 2'd3: begin
+ ddrphy_bitslip17_o <= ddrphy_bitslip17_r[6:3];
+ end
+ endcase
+end
+always @(*) begin
+ ddrphy_bitslip18_o <= 4'd0;
+ case (ddrphy_bitslip18_value)
+ 1'd0: begin
+ ddrphy_bitslip18_o <= ddrphy_bitslip18_r[3:0];
+ end
+ 1'd1: begin
+ ddrphy_bitslip18_o <= ddrphy_bitslip18_r[4:1];
+ end
+ 2'd2: begin
+ ddrphy_bitslip18_o <= ddrphy_bitslip18_r[5:2];
+ end
+ 2'd3: begin
+ ddrphy_bitslip18_o <= ddrphy_bitslip18_r[6:3];
+ end
+ endcase
+end
+always @(*) begin
+ ddrphy_bitslip19_o <= 4'd0;
+ case (ddrphy_bitslip19_value)
+ 1'd0: begin
+ ddrphy_bitslip19_o <= ddrphy_bitslip19_r[3:0];
+ end
+ 1'd1: begin
+ ddrphy_bitslip19_o <= ddrphy_bitslip19_r[4:1];
+ end
+ 2'd2: begin
+ ddrphy_bitslip19_o <= ddrphy_bitslip19_r[5:2];
+ end
+ 2'd3: begin
+ ddrphy_bitslip19_o <= ddrphy_bitslip19_r[6:3];
+ end
+ endcase
+end
+always @(*) begin
+ ddrphy_bitslip20_o <= 4'd0;
+ case (ddrphy_bitslip20_value)
+ 1'd0: begin
+ ddrphy_bitslip20_o <= ddrphy_bitslip20_r[3:0];
+ end
+ 1'd1: begin
+ ddrphy_bitslip20_o <= ddrphy_bitslip20_r[4:1];
+ end
+ 2'd2: begin
+ ddrphy_bitslip20_o <= ddrphy_bitslip20_r[5:2];
+ end
+ 2'd3: begin
+ ddrphy_bitslip20_o <= ddrphy_bitslip20_r[6:3];
+ end
+ endcase
+end
+always @(*) begin
+ ddrphy_bitslip21_o <= 4'd0;
+ case (ddrphy_bitslip21_value)
+ 1'd0: begin
+ ddrphy_bitslip21_o <= ddrphy_bitslip21_r[3:0];
+ end
+ 1'd1: begin
+ ddrphy_bitslip21_o <= ddrphy_bitslip21_r[4:1];
+ end
+ 2'd2: begin
+ ddrphy_bitslip21_o <= ddrphy_bitslip21_r[5:2];
+ end
+ 2'd3: begin
+ ddrphy_bitslip21_o <= ddrphy_bitslip21_r[6:3];
+ end
+ endcase
+end
+always @(*) begin
+ ddrphy_bitslip22_o <= 4'd0;
+ case (ddrphy_bitslip22_value)
+ 1'd0: begin
+ ddrphy_bitslip22_o <= ddrphy_bitslip22_r[3:0];
+ end
+ 1'd1: begin
+ ddrphy_bitslip22_o <= ddrphy_bitslip22_r[4:1];
+ end
+ 2'd2: begin
+ ddrphy_bitslip22_o <= ddrphy_bitslip22_r[5:2];
+ end
+ 2'd3: begin
+ ddrphy_bitslip22_o <= ddrphy_bitslip22_r[6:3];
+ end
+ endcase
+end
+always @(*) begin
+ ddrphy_bitslip23_o <= 4'd0;
+ case (ddrphy_bitslip23_value)
+ 1'd0: begin
+ ddrphy_bitslip23_o <= ddrphy_bitslip23_r[3:0];
+ end
+ 1'd1: begin
+ ddrphy_bitslip23_o <= ddrphy_bitslip23_r[4:1];
+ end
+ 2'd2: begin
+ ddrphy_bitslip23_o <= ddrphy_bitslip23_r[5:2];
+ end
+ 2'd3: begin
+ ddrphy_bitslip23_o <= ddrphy_bitslip23_r[6:3];
+ end
+ endcase
+end
+always @(*) begin
+ ddrphy_bitslip24_o <= 4'd0;
+ case (ddrphy_bitslip24_value)
+ 1'd0: begin
+ ddrphy_bitslip24_o <= ddrphy_bitslip24_r[3:0];
+ end
+ 1'd1: begin
+ ddrphy_bitslip24_o <= ddrphy_bitslip24_r[4:1];
+ end
+ 2'd2: begin
+ ddrphy_bitslip24_o <= ddrphy_bitslip24_r[5:2];
+ end
+ 2'd3: begin
+ ddrphy_bitslip24_o <= ddrphy_bitslip24_r[6:3];
+ end
+ endcase
+end
+always @(*) begin
+ ddrphy_bitslip25_o <= 4'd0;
+ case (ddrphy_bitslip25_value)
+ 1'd0: begin
+ ddrphy_bitslip25_o <= ddrphy_bitslip25_r[3:0];
+ end
+ 1'd1: begin
+ ddrphy_bitslip25_o <= ddrphy_bitslip25_r[4:1];
+ end
+ 2'd2: begin
+ ddrphy_bitslip25_o <= ddrphy_bitslip25_r[5:2];
+ end
+ 2'd3: begin
+ ddrphy_bitslip25_o <= ddrphy_bitslip25_r[6:3];
+ end
+ endcase
+end
+always @(*) begin
+ ddrphy_bitslip26_o <= 4'd0;
+ case (ddrphy_bitslip26_value)
+ 1'd0: begin
+ ddrphy_bitslip26_o <= ddrphy_bitslip26_r[3:0];
+ end
+ 1'd1: begin
+ ddrphy_bitslip26_o <= ddrphy_bitslip26_r[4:1];
+ end
+ 2'd2: begin
+ ddrphy_bitslip26_o <= ddrphy_bitslip26_r[5:2];
+ end
+ 2'd3: begin
+ ddrphy_bitslip26_o <= ddrphy_bitslip26_r[6:3];
+ end
+ endcase
+end
+always @(*) begin
+ ddrphy_bitslip27_o <= 4'd0;
+ case (ddrphy_bitslip27_value)
+ 1'd0: begin
+ ddrphy_bitslip27_o <= ddrphy_bitslip27_r[3:0];
+ end
+ 1'd1: begin
+ ddrphy_bitslip27_o <= ddrphy_bitslip27_r[4:1];
+ end
+ 2'd2: begin
+ ddrphy_bitslip27_o <= ddrphy_bitslip27_r[5:2];
+ end
+ 2'd3: begin
+ ddrphy_bitslip27_o <= ddrphy_bitslip27_r[6:3];
+ end
+ endcase
+end
+always @(*) begin
+ ddrphy_bitslip28_o <= 4'd0;
+ case (ddrphy_bitslip28_value)
+ 1'd0: begin
+ ddrphy_bitslip28_o <= ddrphy_bitslip28_r[3:0];
+ end
+ 1'd1: begin
+ ddrphy_bitslip28_o <= ddrphy_bitslip28_r[4:1];
+ end
+ 2'd2: begin
+ ddrphy_bitslip28_o <= ddrphy_bitslip28_r[5:2];
+ end
+ 2'd3: begin
+ ddrphy_bitslip28_o <= ddrphy_bitslip28_r[6:3];
+ end
+ endcase
+end
+always @(*) begin
+ ddrphy_bitslip29_o <= 4'd0;
+ case (ddrphy_bitslip29_value)
+ 1'd0: begin
+ ddrphy_bitslip29_o <= ddrphy_bitslip29_r[3:0];
+ end
+ 1'd1: begin
+ ddrphy_bitslip29_o <= ddrphy_bitslip29_r[4:1];
+ end
+ 2'd2: begin
+ ddrphy_bitslip29_o <= ddrphy_bitslip29_r[5:2];
+ end
+ 2'd3: begin
+ ddrphy_bitslip29_o <= ddrphy_bitslip29_r[6:3];
+ end
+ endcase
+end
+always @(*) begin
+ ddrphy_bitslip30_o <= 4'd0;
+ case (ddrphy_bitslip30_value)
+ 1'd0: begin
+ ddrphy_bitslip30_o <= ddrphy_bitslip30_r[3:0];
+ end
+ 1'd1: begin
+ ddrphy_bitslip30_o <= ddrphy_bitslip30_r[4:1];
+ end
+ 2'd2: begin
+ ddrphy_bitslip30_o <= ddrphy_bitslip30_r[5:2];
+ end
+ 2'd3: begin
+ ddrphy_bitslip30_o <= ddrphy_bitslip30_r[6:3];
+ end
+ endcase
+end
+always @(*) begin
+ ddrphy_bitslip31_o <= 4'd0;
+ case (ddrphy_bitslip31_value)
+ 1'd0: begin
+ ddrphy_bitslip31_o <= ddrphy_bitslip31_r[3:0];
+ end
+ 1'd1: begin
+ ddrphy_bitslip31_o <= ddrphy_bitslip31_r[4:1];
+ end
+ 2'd2: begin
+ ddrphy_bitslip31_o <= ddrphy_bitslip31_r[5:2];
+ end
+ 2'd3: begin
+ ddrphy_bitslip31_o <= ddrphy_bitslip31_r[6:3];
+ end
+ endcase
+end
+assign ddrphy_dfi_p0_address = litedramcore_master_p0_address;
+assign ddrphy_dfi_p0_bank = litedramcore_master_p0_bank;
+assign ddrphy_dfi_p0_cas_n = litedramcore_master_p0_cas_n;
+assign ddrphy_dfi_p0_cs_n = litedramcore_master_p0_cs_n;
+assign ddrphy_dfi_p0_ras_n = litedramcore_master_p0_ras_n;
+assign ddrphy_dfi_p0_we_n = litedramcore_master_p0_we_n;
+assign ddrphy_dfi_p0_cke = litedramcore_master_p0_cke;
+assign ddrphy_dfi_p0_odt = litedramcore_master_p0_odt;
+assign ddrphy_dfi_p0_reset_n = litedramcore_master_p0_reset_n;
+assign ddrphy_dfi_p0_act_n = litedramcore_master_p0_act_n;
+assign ddrphy_dfi_p0_wrdata = litedramcore_master_p0_wrdata;
+assign ddrphy_dfi_p0_wrdata_en = litedramcore_master_p0_wrdata_en;
+assign ddrphy_dfi_p0_wrdata_mask = litedramcore_master_p0_wrdata_mask;
+assign ddrphy_dfi_p0_rddata_en = litedramcore_master_p0_rddata_en;
+assign litedramcore_master_p0_rddata = ddrphy_dfi_p0_rddata;
+assign litedramcore_master_p0_rddata_valid = ddrphy_dfi_p0_rddata_valid;
+assign ddrphy_dfi_p1_address = litedramcore_master_p1_address;
+assign ddrphy_dfi_p1_bank = litedramcore_master_p1_bank;
+assign ddrphy_dfi_p1_cas_n = litedramcore_master_p1_cas_n;
+assign ddrphy_dfi_p1_cs_n = litedramcore_master_p1_cs_n;
+assign ddrphy_dfi_p1_ras_n = litedramcore_master_p1_ras_n;
+assign ddrphy_dfi_p1_we_n = litedramcore_master_p1_we_n;
+assign ddrphy_dfi_p1_cke = litedramcore_master_p1_cke;
+assign ddrphy_dfi_p1_odt = litedramcore_master_p1_odt;
+assign ddrphy_dfi_p1_reset_n = litedramcore_master_p1_reset_n;
+assign ddrphy_dfi_p1_act_n = litedramcore_master_p1_act_n;
+assign ddrphy_dfi_p1_wrdata = litedramcore_master_p1_wrdata;
+assign ddrphy_dfi_p1_wrdata_en = litedramcore_master_p1_wrdata_en;
+assign ddrphy_dfi_p1_wrdata_mask = litedramcore_master_p1_wrdata_mask;
+assign ddrphy_dfi_p1_rddata_en = litedramcore_master_p1_rddata_en;
+assign litedramcore_master_p1_rddata = ddrphy_dfi_p1_rddata;
+assign litedramcore_master_p1_rddata_valid = ddrphy_dfi_p1_rddata_valid;
+assign litedramcore_slave_p0_address = litedramcore_dfi_p0_address;
+assign litedramcore_slave_p0_bank = litedramcore_dfi_p0_bank;
+assign litedramcore_slave_p0_cas_n = litedramcore_dfi_p0_cas_n;
+assign litedramcore_slave_p0_cs_n = litedramcore_dfi_p0_cs_n;
+assign litedramcore_slave_p0_ras_n = litedramcore_dfi_p0_ras_n;
+assign litedramcore_slave_p0_we_n = litedramcore_dfi_p0_we_n;
+assign litedramcore_slave_p0_cke = litedramcore_dfi_p0_cke;
+assign litedramcore_slave_p0_odt = litedramcore_dfi_p0_odt;
+assign litedramcore_slave_p0_reset_n = litedramcore_dfi_p0_reset_n;
+assign litedramcore_slave_p0_act_n = litedramcore_dfi_p0_act_n;
+assign litedramcore_slave_p0_wrdata = litedramcore_dfi_p0_wrdata;
+assign litedramcore_slave_p0_wrdata_en = litedramcore_dfi_p0_wrdata_en;
+assign litedramcore_slave_p0_wrdata_mask = litedramcore_dfi_p0_wrdata_mask;
+assign litedramcore_slave_p0_rddata_en = litedramcore_dfi_p0_rddata_en;
+assign litedramcore_dfi_p0_rddata = litedramcore_slave_p0_rddata;
+assign litedramcore_dfi_p0_rddata_valid = litedramcore_slave_p0_rddata_valid;
+assign litedramcore_slave_p1_address = litedramcore_dfi_p1_address;
+assign litedramcore_slave_p1_bank = litedramcore_dfi_p1_bank;
+assign litedramcore_slave_p1_cas_n = litedramcore_dfi_p1_cas_n;
+assign litedramcore_slave_p1_cs_n = litedramcore_dfi_p1_cs_n;
+assign litedramcore_slave_p1_ras_n = litedramcore_dfi_p1_ras_n;
+assign litedramcore_slave_p1_we_n = litedramcore_dfi_p1_we_n;
+assign litedramcore_slave_p1_cke = litedramcore_dfi_p1_cke;
+assign litedramcore_slave_p1_odt = litedramcore_dfi_p1_odt;
+assign litedramcore_slave_p1_reset_n = litedramcore_dfi_p1_reset_n;
+assign litedramcore_slave_p1_act_n = litedramcore_dfi_p1_act_n;
+assign litedramcore_slave_p1_wrdata = litedramcore_dfi_p1_wrdata;
+assign litedramcore_slave_p1_wrdata_en = litedramcore_dfi_p1_wrdata_en;
+assign litedramcore_slave_p1_wrdata_mask = litedramcore_dfi_p1_wrdata_mask;
+assign litedramcore_slave_p1_rddata_en = litedramcore_dfi_p1_rddata_en;
+assign litedramcore_dfi_p1_rddata = litedramcore_slave_p1_rddata;
+assign litedramcore_dfi_p1_rddata_valid = litedramcore_slave_p1_rddata_valid;
+always @(*) begin
+ litedramcore_master_p1_rddata_en <= 1'd0;
+ if (litedramcore_sel) begin
+ litedramcore_master_p1_rddata_en <= litedramcore_slave_p1_rddata_en;
+ end else begin
+ litedramcore_master_p1_rddata_en <= litedramcore_inti_p1_rddata_en;
+ end
+end
+always @(*) begin
+ litedramcore_slave_p0_rddata <= 128'd0;
+ if (litedramcore_sel) begin
+ litedramcore_slave_p0_rddata <= litedramcore_master_p0_rddata;
+ end else begin
+ end
+end
+always @(*) begin
+ litedramcore_slave_p0_rddata_valid <= 1'd0;
+ if (litedramcore_sel) begin
+ litedramcore_slave_p0_rddata_valid <= litedramcore_master_p0_rddata_valid;
+ end else begin
+ end
+end
+always @(*) begin
+ litedramcore_slave_p1_rddata <= 128'd0;
+ if (litedramcore_sel) begin
+ litedramcore_slave_p1_rddata <= litedramcore_master_p1_rddata;
+ end else begin
+ end
+end
+always @(*) begin
+ litedramcore_slave_p1_rddata_valid <= 1'd0;
+ if (litedramcore_sel) begin
+ litedramcore_slave_p1_rddata_valid <= litedramcore_master_p1_rddata_valid;
+ end else begin
+ end
+end
+always @(*) begin
+ litedramcore_master_p0_address <= 15'd0;
+ if (litedramcore_sel) begin
+ litedramcore_master_p0_address <= litedramcore_slave_p0_address;
+ end else begin
+ litedramcore_master_p0_address <= litedramcore_inti_p0_address;
+ end
+end
+always @(*) begin
+ litedramcore_master_p0_bank <= 3'd0;
+ if (litedramcore_sel) begin
+ litedramcore_master_p0_bank <= litedramcore_slave_p0_bank;
+ end else begin
+ litedramcore_master_p0_bank <= litedramcore_inti_p0_bank;
+ end
+end
+always @(*) begin
+ litedramcore_master_p0_cas_n <= 1'd1;
+ if (litedramcore_sel) begin
+ litedramcore_master_p0_cas_n <= litedramcore_slave_p0_cas_n;
+ end else begin
+ litedramcore_master_p0_cas_n <= litedramcore_inti_p0_cas_n;
+ end
+end
+always @(*) begin
+ litedramcore_master_p0_cs_n <= 1'd1;
+ if (litedramcore_sel) begin
+ litedramcore_master_p0_cs_n <= litedramcore_slave_p0_cs_n;
+ end else begin
+ litedramcore_master_p0_cs_n <= litedramcore_inti_p0_cs_n;
+ end
+end
+always @(*) begin
+ litedramcore_master_p0_ras_n <= 1'd1;
+ if (litedramcore_sel) begin
+ litedramcore_master_p0_ras_n <= litedramcore_slave_p0_ras_n;
+ end else begin
+ litedramcore_master_p0_ras_n <= litedramcore_inti_p0_ras_n;
+ end
+end
+always @(*) begin
+ litedramcore_inti_p0_rddata <= 128'd0;
+ if (litedramcore_sel) begin
+ end else begin
+ litedramcore_inti_p0_rddata <= litedramcore_master_p0_rddata;
+ end
+end
+always @(*) begin
+ litedramcore_master_p0_we_n <= 1'd1;
+ if (litedramcore_sel) begin
+ litedramcore_master_p0_we_n <= litedramcore_slave_p0_we_n;
+ end else begin
+ litedramcore_master_p0_we_n <= litedramcore_inti_p0_we_n;
+ end
+end
+always @(*) begin
+ litedramcore_inti_p0_rddata_valid <= 1'd0;
+ if (litedramcore_sel) begin
+ end else begin
+ litedramcore_inti_p0_rddata_valid <= litedramcore_master_p0_rddata_valid;
+ end
+end
+always @(*) begin
+ litedramcore_master_p0_cke <= 1'd0;
+ if (litedramcore_sel) begin
+ litedramcore_master_p0_cke <= litedramcore_slave_p0_cke;
+ end else begin
+ litedramcore_master_p0_cke <= litedramcore_inti_p0_cke;
+ end
+end
+always @(*) begin
+ litedramcore_master_p0_odt <= 1'd0;
+ if (litedramcore_sel) begin
+ litedramcore_master_p0_odt <= litedramcore_slave_p0_odt;
+ end else begin
+ litedramcore_master_p0_odt <= litedramcore_inti_p0_odt;
+ end
+end
+always @(*) begin
+ litedramcore_master_p0_reset_n <= 1'd0;
+ if (litedramcore_sel) begin
+ litedramcore_master_p0_reset_n <= litedramcore_slave_p0_reset_n;
+ end else begin
+ litedramcore_master_p0_reset_n <= litedramcore_inti_p0_reset_n;
+ end
+end
+always @(*) begin
+ litedramcore_master_p0_act_n <= 1'd1;
+ if (litedramcore_sel) begin
+ litedramcore_master_p0_act_n <= litedramcore_slave_p0_act_n;
+ end else begin
+ litedramcore_master_p0_act_n <= litedramcore_inti_p0_act_n;
+ end
+end
+always @(*) begin
+ litedramcore_master_p0_wrdata <= 128'd0;
+ if (litedramcore_sel) begin
+ litedramcore_master_p0_wrdata <= litedramcore_slave_p0_wrdata;
+ end else begin
+ litedramcore_master_p0_wrdata <= litedramcore_inti_p0_wrdata;
+ end
+end
+always @(*) begin
+ litedramcore_master_p0_wrdata_en <= 1'd0;
+ if (litedramcore_sel) begin
+ litedramcore_master_p0_wrdata_en <= litedramcore_slave_p0_wrdata_en;
+ end else begin
+ litedramcore_master_p0_wrdata_en <= litedramcore_inti_p0_wrdata_en;
+ end
+end
+always @(*) begin
+ litedramcore_master_p0_wrdata_mask <= 16'd0;
+ if (litedramcore_sel) begin
+ litedramcore_master_p0_wrdata_mask <= litedramcore_slave_p0_wrdata_mask;
+ end else begin
+ litedramcore_master_p0_wrdata_mask <= litedramcore_inti_p0_wrdata_mask;
+ end
+end
+always @(*) begin
+ litedramcore_master_p0_rddata_en <= 1'd0;
+ if (litedramcore_sel) begin
+ litedramcore_master_p0_rddata_en <= litedramcore_slave_p0_rddata_en;
+ end else begin
+ litedramcore_master_p0_rddata_en <= litedramcore_inti_p0_rddata_en;
+ end
+end
+always @(*) begin
+ litedramcore_master_p1_address <= 15'd0;
+ if (litedramcore_sel) begin
+ litedramcore_master_p1_address <= litedramcore_slave_p1_address;
+ end else begin
+ litedramcore_master_p1_address <= litedramcore_inti_p1_address;
+ end
+end
+always @(*) begin
+ litedramcore_master_p1_bank <= 3'd0;
+ if (litedramcore_sel) begin
+ litedramcore_master_p1_bank <= litedramcore_slave_p1_bank;
+ end else begin
+ litedramcore_master_p1_bank <= litedramcore_inti_p1_bank;
+ end
+end
+always @(*) begin
+ litedramcore_master_p1_cas_n <= 1'd1;
+ if (litedramcore_sel) begin
+ litedramcore_master_p1_cas_n <= litedramcore_slave_p1_cas_n;
+ end else begin
+ litedramcore_master_p1_cas_n <= litedramcore_inti_p1_cas_n;
+ end
+end
+always @(*) begin
+ litedramcore_master_p1_cs_n <= 1'd1;
+ if (litedramcore_sel) begin
+ litedramcore_master_p1_cs_n <= litedramcore_slave_p1_cs_n;
+ end else begin
+ litedramcore_master_p1_cs_n <= litedramcore_inti_p1_cs_n;
+ end
+end
+always @(*) begin
+ litedramcore_master_p1_ras_n <= 1'd1;
+ if (litedramcore_sel) begin
+ litedramcore_master_p1_ras_n <= litedramcore_slave_p1_ras_n;
+ end else begin
+ litedramcore_master_p1_ras_n <= litedramcore_inti_p1_ras_n;
+ end
+end
+always @(*) begin
+ litedramcore_inti_p1_rddata <= 128'd0;
+ if (litedramcore_sel) begin
+ end else begin
+ litedramcore_inti_p1_rddata <= litedramcore_master_p1_rddata;
+ end
+end
+always @(*) begin
+ litedramcore_master_p1_we_n <= 1'd1;
+ if (litedramcore_sel) begin
+ litedramcore_master_p1_we_n <= litedramcore_slave_p1_we_n;
+ end else begin
+ litedramcore_master_p1_we_n <= litedramcore_inti_p1_we_n;
+ end
+end
+always @(*) begin
+ litedramcore_inti_p1_rddata_valid <= 1'd0;
+ if (litedramcore_sel) begin
+ end else begin
+ litedramcore_inti_p1_rddata_valid <= litedramcore_master_p1_rddata_valid;
+ end
+end
+always @(*) begin
+ litedramcore_master_p1_cke <= 1'd0;
+ if (litedramcore_sel) begin
+ litedramcore_master_p1_cke <= litedramcore_slave_p1_cke;
+ end else begin
+ litedramcore_master_p1_cke <= litedramcore_inti_p1_cke;
+ end
+end
+always @(*) begin
+ litedramcore_master_p1_odt <= 1'd0;
+ if (litedramcore_sel) begin
+ litedramcore_master_p1_odt <= litedramcore_slave_p1_odt;
+ end else begin
+ litedramcore_master_p1_odt <= litedramcore_inti_p1_odt;
+ end
+end
+always @(*) begin
+ litedramcore_master_p1_reset_n <= 1'd0;
+ if (litedramcore_sel) begin
+ litedramcore_master_p1_reset_n <= litedramcore_slave_p1_reset_n;
+ end else begin
+ litedramcore_master_p1_reset_n <= litedramcore_inti_p1_reset_n;
+ end
+end
+always @(*) begin
+ litedramcore_master_p1_act_n <= 1'd1;
+ if (litedramcore_sel) begin
+ litedramcore_master_p1_act_n <= litedramcore_slave_p1_act_n;
+ end else begin
+ litedramcore_master_p1_act_n <= litedramcore_inti_p1_act_n;
+ end
+end
+always @(*) begin
+ litedramcore_master_p1_wrdata <= 128'd0;
+ if (litedramcore_sel) begin
+ litedramcore_master_p1_wrdata <= litedramcore_slave_p1_wrdata;
+ end else begin
+ litedramcore_master_p1_wrdata <= litedramcore_inti_p1_wrdata;
+ end
+end
+always @(*) begin
+ litedramcore_master_p1_wrdata_en <= 1'd0;
+ if (litedramcore_sel) begin
+ litedramcore_master_p1_wrdata_en <= litedramcore_slave_p1_wrdata_en;
+ end else begin
+ litedramcore_master_p1_wrdata_en <= litedramcore_inti_p1_wrdata_en;
+ end
+end
+always @(*) begin
+ litedramcore_master_p1_wrdata_mask <= 16'd0;
+ if (litedramcore_sel) begin
+ litedramcore_master_p1_wrdata_mask <= litedramcore_slave_p1_wrdata_mask;
+ end else begin
+ litedramcore_master_p1_wrdata_mask <= litedramcore_inti_p1_wrdata_mask;
+ end
+end
+assign litedramcore_inti_p0_cke = litedramcore_cke;
+assign litedramcore_inti_p1_cke = litedramcore_cke;
+assign litedramcore_inti_p0_odt = litedramcore_odt;
+assign litedramcore_inti_p1_odt = litedramcore_odt;
+assign litedramcore_inti_p0_reset_n = litedramcore_reset_n;
+assign litedramcore_inti_p1_reset_n = litedramcore_reset_n;
+always @(*) begin
+ litedramcore_inti_p0_cs_n <= 1'd1;
+ if (litedramcore_phaseinjector0_command_issue_re) begin
+ litedramcore_inti_p0_cs_n <= {1{(~litedramcore_phaseinjector0_command_storage[0])}};
+ end else begin
+ litedramcore_inti_p0_cs_n <= {1{1'd1}};
+ end
+end
+always @(*) begin
+ litedramcore_inti_p0_ras_n <= 1'd1;
+ if (litedramcore_phaseinjector0_command_issue_re) begin
+ litedramcore_inti_p0_ras_n <= (~litedramcore_phaseinjector0_command_storage[3]);
+ end else begin
+ litedramcore_inti_p0_ras_n <= 1'd1;
+ end
+end
+always @(*) begin
+ litedramcore_inti_p0_we_n <= 1'd1;
+ if (litedramcore_phaseinjector0_command_issue_re) begin
+ litedramcore_inti_p0_we_n <= (~litedramcore_phaseinjector0_command_storage[1]);
+ end else begin
+ litedramcore_inti_p0_we_n <= 1'd1;
+ end
+end
+always @(*) begin
+ litedramcore_inti_p0_cas_n <= 1'd1;
+ if (litedramcore_phaseinjector0_command_issue_re) begin
+ litedramcore_inti_p0_cas_n <= (~litedramcore_phaseinjector0_command_storage[2]);
+ end else begin
+ litedramcore_inti_p0_cas_n <= 1'd1;
+ end
+end
+assign litedramcore_inti_p0_address = litedramcore_phaseinjector0_address_storage;
+assign litedramcore_inti_p0_bank = litedramcore_phaseinjector0_baddress_storage;
+assign litedramcore_inti_p0_wrdata_en = (litedramcore_phaseinjector0_command_issue_re & litedramcore_phaseinjector0_command_storage[4]);
+assign litedramcore_inti_p0_rddata_en = (litedramcore_phaseinjector0_command_issue_re & litedramcore_phaseinjector0_command_storage[5]);
+assign litedramcore_inti_p0_wrdata = litedramcore_phaseinjector0_wrdata_storage;
+assign litedramcore_inti_p0_wrdata_mask = 1'd0;
+always @(*) begin
+ litedramcore_inti_p1_cs_n <= 1'd1;
+ if (litedramcore_phaseinjector1_command_issue_re) begin
+ litedramcore_inti_p1_cs_n <= {1{(~litedramcore_phaseinjector1_command_storage[0])}};
+ end else begin
+ litedramcore_inti_p1_cs_n <= {1{1'd1}};
+ end
+end
+always @(*) begin
+ litedramcore_inti_p1_ras_n <= 1'd1;
+ if (litedramcore_phaseinjector1_command_issue_re) begin
+ litedramcore_inti_p1_ras_n <= (~litedramcore_phaseinjector1_command_storage[3]);
+ end else begin
+ litedramcore_inti_p1_ras_n <= 1'd1;
+ end
+end
+always @(*) begin
+ litedramcore_inti_p1_we_n <= 1'd1;
+ if (litedramcore_phaseinjector1_command_issue_re) begin
+ litedramcore_inti_p1_we_n <= (~litedramcore_phaseinjector1_command_storage[1]);
+ end else begin
+ litedramcore_inti_p1_we_n <= 1'd1;
+ end
+end
+always @(*) begin
+ litedramcore_inti_p1_cas_n <= 1'd1;
+ if (litedramcore_phaseinjector1_command_issue_re) begin
+ litedramcore_inti_p1_cas_n <= (~litedramcore_phaseinjector1_command_storage[2]);
+ end else begin
+ litedramcore_inti_p1_cas_n <= 1'd1;
+ end
+end
+assign litedramcore_inti_p1_address = litedramcore_phaseinjector1_address_storage;
+assign litedramcore_inti_p1_bank = litedramcore_phaseinjector1_baddress_storage;
+assign litedramcore_inti_p1_wrdata_en = (litedramcore_phaseinjector1_command_issue_re & litedramcore_phaseinjector1_command_storage[4]);
+assign litedramcore_inti_p1_rddata_en = (litedramcore_phaseinjector1_command_issue_re & litedramcore_phaseinjector1_command_storage[5]);
+assign litedramcore_inti_p1_wrdata = litedramcore_phaseinjector1_wrdata_storage;
+assign litedramcore_inti_p1_wrdata_mask = 1'd0;
+assign litedramcore_bankmachine0_req_valid = litedramcore_interface_bank0_valid;
+assign litedramcore_interface_bank0_ready = litedramcore_bankmachine0_req_ready;
+assign litedramcore_bankmachine0_req_we = litedramcore_interface_bank0_we;
+assign litedramcore_bankmachine0_req_addr = litedramcore_interface_bank0_addr;
+assign litedramcore_interface_bank0_lock = litedramcore_bankmachine0_req_lock;
+assign litedramcore_interface_bank0_wdata_ready = litedramcore_bankmachine0_req_wdata_ready;
+assign litedramcore_interface_bank0_rdata_valid = litedramcore_bankmachine0_req_rdata_valid;
+assign litedramcore_bankmachine1_req_valid = litedramcore_interface_bank1_valid;
+assign litedramcore_interface_bank1_ready = litedramcore_bankmachine1_req_ready;
+assign litedramcore_bankmachine1_req_we = litedramcore_interface_bank1_we;
+assign litedramcore_bankmachine1_req_addr = litedramcore_interface_bank1_addr;
+assign litedramcore_interface_bank1_lock = litedramcore_bankmachine1_req_lock;
+assign litedramcore_interface_bank1_wdata_ready = litedramcore_bankmachine1_req_wdata_ready;
+assign litedramcore_interface_bank1_rdata_valid = litedramcore_bankmachine1_req_rdata_valid;
+assign litedramcore_bankmachine2_req_valid = litedramcore_interface_bank2_valid;
+assign litedramcore_interface_bank2_ready = litedramcore_bankmachine2_req_ready;
+assign litedramcore_bankmachine2_req_we = litedramcore_interface_bank2_we;
+assign litedramcore_bankmachine2_req_addr = litedramcore_interface_bank2_addr;
+assign litedramcore_interface_bank2_lock = litedramcore_bankmachine2_req_lock;
+assign litedramcore_interface_bank2_wdata_ready = litedramcore_bankmachine2_req_wdata_ready;
+assign litedramcore_interface_bank2_rdata_valid = litedramcore_bankmachine2_req_rdata_valid;
+assign litedramcore_bankmachine3_req_valid = litedramcore_interface_bank3_valid;
+assign litedramcore_interface_bank3_ready = litedramcore_bankmachine3_req_ready;
+assign litedramcore_bankmachine3_req_we = litedramcore_interface_bank3_we;
+assign litedramcore_bankmachine3_req_addr = litedramcore_interface_bank3_addr;
+assign litedramcore_interface_bank3_lock = litedramcore_bankmachine3_req_lock;
+assign litedramcore_interface_bank3_wdata_ready = litedramcore_bankmachine3_req_wdata_ready;
+assign litedramcore_interface_bank3_rdata_valid = litedramcore_bankmachine3_req_rdata_valid;
+assign litedramcore_bankmachine4_req_valid = litedramcore_interface_bank4_valid;
+assign litedramcore_interface_bank4_ready = litedramcore_bankmachine4_req_ready;
+assign litedramcore_bankmachine4_req_we = litedramcore_interface_bank4_we;
+assign litedramcore_bankmachine4_req_addr = litedramcore_interface_bank4_addr;
+assign litedramcore_interface_bank4_lock = litedramcore_bankmachine4_req_lock;
+assign litedramcore_interface_bank4_wdata_ready = litedramcore_bankmachine4_req_wdata_ready;
+assign litedramcore_interface_bank4_rdata_valid = litedramcore_bankmachine4_req_rdata_valid;
+assign litedramcore_bankmachine5_req_valid = litedramcore_interface_bank5_valid;
+assign litedramcore_interface_bank5_ready = litedramcore_bankmachine5_req_ready;
+assign litedramcore_bankmachine5_req_we = litedramcore_interface_bank5_we;
+assign litedramcore_bankmachine5_req_addr = litedramcore_interface_bank5_addr;
+assign litedramcore_interface_bank5_lock = litedramcore_bankmachine5_req_lock;
+assign litedramcore_interface_bank5_wdata_ready = litedramcore_bankmachine5_req_wdata_ready;
+assign litedramcore_interface_bank5_rdata_valid = litedramcore_bankmachine5_req_rdata_valid;
+assign litedramcore_bankmachine6_req_valid = litedramcore_interface_bank6_valid;
+assign litedramcore_interface_bank6_ready = litedramcore_bankmachine6_req_ready;
+assign litedramcore_bankmachine6_req_we = litedramcore_interface_bank6_we;
+assign litedramcore_bankmachine6_req_addr = litedramcore_interface_bank6_addr;
+assign litedramcore_interface_bank6_lock = litedramcore_bankmachine6_req_lock;
+assign litedramcore_interface_bank6_wdata_ready = litedramcore_bankmachine6_req_wdata_ready;
+assign litedramcore_interface_bank6_rdata_valid = litedramcore_bankmachine6_req_rdata_valid;
+assign litedramcore_bankmachine7_req_valid = litedramcore_interface_bank7_valid;
+assign litedramcore_interface_bank7_ready = litedramcore_bankmachine7_req_ready;
+assign litedramcore_bankmachine7_req_we = litedramcore_interface_bank7_we;
+assign litedramcore_bankmachine7_req_addr = litedramcore_interface_bank7_addr;
+assign litedramcore_interface_bank7_lock = litedramcore_bankmachine7_req_lock;
+assign litedramcore_interface_bank7_wdata_ready = litedramcore_bankmachine7_req_wdata_ready;
+assign litedramcore_interface_bank7_rdata_valid = litedramcore_bankmachine7_req_rdata_valid;
+assign litedramcore_timer_wait = (~litedramcore_timer_done0);
+assign litedramcore_postponer_req_i = litedramcore_timer_done0;
+assign litedramcore_wants_refresh = litedramcore_postponer_req_o;
+assign litedramcore_wants_zqcs = litedramcore_zqcs_timer_done0;
+assign litedramcore_zqcs_timer_wait = (~litedramcore_zqcs_executer_done);
+assign litedramcore_timer_done1 = (litedramcore_timer_count1 == 1'd0);
+assign litedramcore_timer_done0 = litedramcore_timer_done1;
+assign litedramcore_timer_count0 = litedramcore_timer_count1;
+assign litedramcore_sequencer_start1 = (litedramcore_sequencer_start0 | (litedramcore_sequencer_count != 1'd0));
+assign litedramcore_sequencer_done0 = (litedramcore_sequencer_done1 & (litedramcore_sequencer_count == 1'd0));
+assign litedramcore_zqcs_timer_done1 = (litedramcore_zqcs_timer_count1 == 1'd0);
+assign litedramcore_zqcs_timer_done0 = litedramcore_zqcs_timer_done1;
+assign litedramcore_zqcs_timer_count0 = litedramcore_zqcs_timer_count1;
+always @(*) begin
+ litedramcore_refresher_next_state <= 2'd0;
+ litedramcore_refresher_next_state <= litedramcore_refresher_state;
+ case (litedramcore_refresher_state)
+ 1'd1: begin
+ if (litedramcore_cmd_ready) begin
+ litedramcore_refresher_next_state <= 2'd2;
+ end
+ end
+ 2'd2: begin
+ if (litedramcore_sequencer_done0) begin
+ if (litedramcore_wants_zqcs) begin
+ litedramcore_refresher_next_state <= 2'd3;
+ end else begin
+ litedramcore_refresher_next_state <= 1'd0;
+ end
+ end
+ end
+ 2'd3: begin
+ if (litedramcore_zqcs_executer_done) begin
+ litedramcore_refresher_next_state <= 1'd0;
+ end
+ end
+ default: begin
+ if (1'd1) begin
+ if (litedramcore_wants_refresh) begin
+ litedramcore_refresher_next_state <= 1'd1;
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_sequencer_start0 <= 1'd0;
+ case (litedramcore_refresher_state)
+ 1'd1: begin
+ if (litedramcore_cmd_ready) begin
+ litedramcore_sequencer_start0 <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_cmd_valid <= 1'd0;
+ case (litedramcore_refresher_state)
+ 1'd1: begin
+ litedramcore_cmd_valid <= 1'd1;
+ end
+ 2'd2: begin
+ litedramcore_cmd_valid <= 1'd1;
+ if (litedramcore_sequencer_done0) begin
+ if (litedramcore_wants_zqcs) begin
+ end else begin
+ litedramcore_cmd_valid <= 1'd0;
+ end
+ end
+ end
+ 2'd3: begin
+ litedramcore_cmd_valid <= 1'd1;
+ if (litedramcore_zqcs_executer_done) begin
+ litedramcore_cmd_valid <= 1'd0;
+ end
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_zqcs_executer_start <= 1'd0;
+ case (litedramcore_refresher_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ if (litedramcore_sequencer_done0) begin
+ if (litedramcore_wants_zqcs) begin
+ litedramcore_zqcs_executer_start <= 1'd1;
+ end else begin
+ end
+ end
+ end
+ 2'd3: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_cmd_last <= 1'd0;
+ case (litedramcore_refresher_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ if (litedramcore_sequencer_done0) begin
+ if (litedramcore_wants_zqcs) begin
+ end else begin
+ litedramcore_cmd_last <= 1'd1;
+ end
+ end
+ end
+ 2'd3: begin
+ if (litedramcore_zqcs_executer_done) begin
+ litedramcore_cmd_last <= 1'd1;
+ end
+ end
+ default: begin
+ end
+ endcase
+end
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine0_req_valid;
+assign litedramcore_bankmachine0_req_ready = litedramcore_bankmachine0_cmd_buffer_lookahead_sink_ready;
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine0_req_we;
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine0_req_addr;
+assign litedramcore_bankmachine0_cmd_buffer_sink_valid = litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid;
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine0_cmd_buffer_sink_ready;
+assign litedramcore_bankmachine0_cmd_buffer_sink_first = litedramcore_bankmachine0_cmd_buffer_lookahead_source_first;
+assign litedramcore_bankmachine0_cmd_buffer_sink_last = litedramcore_bankmachine0_cmd_buffer_lookahead_source_last;
+assign litedramcore_bankmachine0_cmd_buffer_sink_payload_we = litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_we;
+assign litedramcore_bankmachine0_cmd_buffer_sink_payload_addr = litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr;
+assign litedramcore_bankmachine0_cmd_buffer_source_ready = (litedramcore_bankmachine0_req_wdata_ready | litedramcore_bankmachine0_req_rdata_valid);
+assign litedramcore_bankmachine0_req_lock = (litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine0_cmd_buffer_source_valid);
+assign litedramcore_bankmachine0_row_hit = (litedramcore_bankmachine0_row == litedramcore_bankmachine0_cmd_buffer_source_payload_addr[21:7]);
+assign litedramcore_bankmachine0_cmd_payload_ba = 1'd0;
+always @(*) begin
+ litedramcore_bankmachine0_cmd_payload_a <= 15'd0;
+ if (litedramcore_bankmachine0_row_col_n_addr_sel) begin
+ litedramcore_bankmachine0_cmd_payload_a <= litedramcore_bankmachine0_cmd_buffer_source_payload_addr[21:7];
+ end else begin
+ litedramcore_bankmachine0_cmd_payload_a <= ((litedramcore_bankmachine0_auto_precharge <<< 4'd10) | {litedramcore_bankmachine0_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
+ end
+end
+assign litedramcore_bankmachine0_twtpcon_valid = ((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_ready) & litedramcore_bankmachine0_cmd_payload_is_write);
+assign litedramcore_bankmachine0_trccon_valid = ((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_ready) & litedramcore_bankmachine0_row_open);
+assign litedramcore_bankmachine0_trascon_valid = ((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_ready) & litedramcore_bankmachine0_row_open);
+always @(*) begin
+ litedramcore_bankmachine0_auto_precharge <= 1'd0;
+ if ((litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine0_cmd_buffer_source_valid)) begin
+ if ((litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr[21:7] != litedramcore_bankmachine0_cmd_buffer_source_payload_addr[21:7])) begin
+ litedramcore_bankmachine0_auto_precharge <= (litedramcore_bankmachine0_row_close == 1'd0);
+ end
+ end
+end
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din = {litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we};
+assign {litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
+assign {litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
+assign {litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
+assign {litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable;
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we = litedramcore_bankmachine0_cmd_buffer_lookahead_sink_valid;
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine0_cmd_buffer_lookahead_sink_first;
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine0_cmd_buffer_lookahead_sink_last;
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_we;
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_addr;
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable;
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_source_first = litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first;
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_source_last = litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last;
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we;
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr;
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_re = litedramcore_bankmachine0_cmd_buffer_lookahead_source_ready;
+always @(*) begin
+ litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr <= 4'd0;
+ if (litedramcore_bankmachine0_cmd_buffer_lookahead_replace) begin
+ litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine0_cmd_buffer_lookahead_produce - 1'd1);
+ end else begin
+ litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine0_cmd_buffer_lookahead_produce;
+ end
+end
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din;
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & (litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable | litedramcore_bankmachine0_cmd_buffer_lookahead_replace));
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable & litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_re);
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine0_cmd_buffer_lookahead_consume;
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout = litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_dat_r;
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable = (litedramcore_bankmachine0_cmd_buffer_lookahead_level != 5'd16);
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable = (litedramcore_bankmachine0_cmd_buffer_lookahead_level != 1'd0);
+assign litedramcore_bankmachine0_cmd_buffer_sink_ready = ((~litedramcore_bankmachine0_cmd_buffer_source_valid) | litedramcore_bankmachine0_cmd_buffer_source_ready);
+always @(*) begin
+ litedramcore_bankmachine0_next_state <= 3'd0;
+ litedramcore_bankmachine0_next_state <= litedramcore_bankmachine0_state;
+ case (litedramcore_bankmachine0_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
+ if (litedramcore_bankmachine0_cmd_ready) begin
+ litedramcore_bankmachine0_next_state <= 3'd5;
+ end
+ end
+ end
+ 2'd2: begin
+ if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
+ litedramcore_bankmachine0_next_state <= 3'd5;
+ end
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine0_trccon_ready) begin
+ if (litedramcore_bankmachine0_cmd_ready) begin
+ litedramcore_bankmachine0_next_state <= 3'd6;
+ end
+ end
+ end
+ 3'd4: begin
+ if ((~litedramcore_bankmachine0_refresh_req)) begin
+ litedramcore_bankmachine0_next_state <= 1'd0;
+ end
+ end
+ 3'd5: begin
+ litedramcore_bankmachine0_next_state <= 2'd3;
+ end
+ 3'd6: begin
+ litedramcore_bankmachine0_next_state <= 1'd0;
+ end
+ default: begin
+ if (litedramcore_bankmachine0_refresh_req) begin
+ litedramcore_bankmachine0_next_state <= 3'd4;
+ end else begin
+ if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin
+ if (litedramcore_bankmachine0_row_opened) begin
+ if (litedramcore_bankmachine0_row_hit) begin
+ if ((litedramcore_bankmachine0_cmd_ready & litedramcore_bankmachine0_auto_precharge)) begin
+ litedramcore_bankmachine0_next_state <= 2'd2;
+ end
+ end else begin
+ litedramcore_bankmachine0_next_state <= 1'd1;
+ end
+ end else begin
+ litedramcore_bankmachine0_next_state <= 2'd3;
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine0_row_open <= 1'd0;
+ case (litedramcore_bankmachine0_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine0_trccon_ready) begin
+ litedramcore_bankmachine0_row_open <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine0_row_close <= 1'd0;
+ case (litedramcore_bankmachine0_state)
+ 1'd1: begin
+ litedramcore_bankmachine0_row_close <= 1'd1;
+ end
+ 2'd2: begin
+ litedramcore_bankmachine0_row_close <= 1'd1;
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ litedramcore_bankmachine0_row_close <= 1'd1;
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine0_cmd_payload_cas <= 1'd0;
+ case (litedramcore_bankmachine0_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine0_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin
+ if (litedramcore_bankmachine0_row_opened) begin
+ if (litedramcore_bankmachine0_row_hit) begin
+ litedramcore_bankmachine0_cmd_payload_cas <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine0_cmd_payload_ras <= 1'd0;
+ case (litedramcore_bankmachine0_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
+ litedramcore_bankmachine0_cmd_payload_ras <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine0_trccon_ready) begin
+ litedramcore_bankmachine0_cmd_payload_ras <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine0_cmd_payload_we <= 1'd0;
+ case (litedramcore_bankmachine0_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
+ litedramcore_bankmachine0_cmd_payload_we <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine0_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin
+ if (litedramcore_bankmachine0_row_opened) begin
+ if (litedramcore_bankmachine0_row_hit) begin
+ if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
+ litedramcore_bankmachine0_cmd_payload_we <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd0;
+ case (litedramcore_bankmachine0_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine0_trccon_ready) begin
+ litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd0;
+ case (litedramcore_bankmachine0_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
+ litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine0_trccon_ready) begin
+ litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1;
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine0_cmd_payload_is_read <= 1'd0;
+ case (litedramcore_bankmachine0_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine0_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin
+ if (litedramcore_bankmachine0_row_opened) begin
+ if (litedramcore_bankmachine0_row_hit) begin
+ if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
+ end else begin
+ litedramcore_bankmachine0_cmd_payload_is_read <= 1'd1;
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine0_cmd_payload_is_write <= 1'd0;
+ case (litedramcore_bankmachine0_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine0_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin
+ if (litedramcore_bankmachine0_row_opened) begin
+ if (litedramcore_bankmachine0_row_hit) begin
+ if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
+ litedramcore_bankmachine0_cmd_payload_is_write <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine0_req_wdata_ready <= 1'd0;
+ case (litedramcore_bankmachine0_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine0_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin
+ if (litedramcore_bankmachine0_row_opened) begin
+ if (litedramcore_bankmachine0_row_hit) begin
+ if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
+ litedramcore_bankmachine0_req_wdata_ready <= litedramcore_bankmachine0_cmd_ready;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine0_req_rdata_valid <= 1'd0;
+ case (litedramcore_bankmachine0_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine0_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin
+ if (litedramcore_bankmachine0_row_opened) begin
+ if (litedramcore_bankmachine0_row_hit) begin
+ if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
+ end else begin
+ litedramcore_bankmachine0_req_rdata_valid <= litedramcore_bankmachine0_cmd_ready;
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine0_refresh_gnt <= 1'd0;
+ case (litedramcore_bankmachine0_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ if (litedramcore_bankmachine0_twtpcon_ready) begin
+ litedramcore_bankmachine0_refresh_gnt <= 1'd1;
+ end
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine0_cmd_valid <= 1'd0;
+ case (litedramcore_bankmachine0_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
+ litedramcore_bankmachine0_cmd_valid <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine0_trccon_ready) begin
+ litedramcore_bankmachine0_cmd_valid <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine0_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin
+ if (litedramcore_bankmachine0_row_opened) begin
+ if (litedramcore_bankmachine0_row_hit) begin
+ litedramcore_bankmachine0_cmd_valid <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine1_req_valid;
+assign litedramcore_bankmachine1_req_ready = litedramcore_bankmachine1_cmd_buffer_lookahead_sink_ready;
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine1_req_we;
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine1_req_addr;
+assign litedramcore_bankmachine1_cmd_buffer_sink_valid = litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid;
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine1_cmd_buffer_sink_ready;
+assign litedramcore_bankmachine1_cmd_buffer_sink_first = litedramcore_bankmachine1_cmd_buffer_lookahead_source_first;
+assign litedramcore_bankmachine1_cmd_buffer_sink_last = litedramcore_bankmachine1_cmd_buffer_lookahead_source_last;
+assign litedramcore_bankmachine1_cmd_buffer_sink_payload_we = litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_we;
+assign litedramcore_bankmachine1_cmd_buffer_sink_payload_addr = litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr;
+assign litedramcore_bankmachine1_cmd_buffer_source_ready = (litedramcore_bankmachine1_req_wdata_ready | litedramcore_bankmachine1_req_rdata_valid);
+assign litedramcore_bankmachine1_req_lock = (litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine1_cmd_buffer_source_valid);
+assign litedramcore_bankmachine1_row_hit = (litedramcore_bankmachine1_row == litedramcore_bankmachine1_cmd_buffer_source_payload_addr[21:7]);
+assign litedramcore_bankmachine1_cmd_payload_ba = 1'd1;
+always @(*) begin
+ litedramcore_bankmachine1_cmd_payload_a <= 15'd0;
+ if (litedramcore_bankmachine1_row_col_n_addr_sel) begin
+ litedramcore_bankmachine1_cmd_payload_a <= litedramcore_bankmachine1_cmd_buffer_source_payload_addr[21:7];
+ end else begin
+ litedramcore_bankmachine1_cmd_payload_a <= ((litedramcore_bankmachine1_auto_precharge <<< 4'd10) | {litedramcore_bankmachine1_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
+ end
+end
+assign litedramcore_bankmachine1_twtpcon_valid = ((litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_ready) & litedramcore_bankmachine1_cmd_payload_is_write);
+assign litedramcore_bankmachine1_trccon_valid = ((litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_ready) & litedramcore_bankmachine1_row_open);
+assign litedramcore_bankmachine1_trascon_valid = ((litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_ready) & litedramcore_bankmachine1_row_open);
+always @(*) begin
+ litedramcore_bankmachine1_auto_precharge <= 1'd0;
+ if ((litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine1_cmd_buffer_source_valid)) begin
+ if ((litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr[21:7] != litedramcore_bankmachine1_cmd_buffer_source_payload_addr[21:7])) begin
+ litedramcore_bankmachine1_auto_precharge <= (litedramcore_bankmachine1_row_close == 1'd0);
+ end
+ end
+end
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din = {litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we};
+assign {litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
+assign {litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
+assign {litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
+assign {litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable;
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we = litedramcore_bankmachine1_cmd_buffer_lookahead_sink_valid;
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine1_cmd_buffer_lookahead_sink_first;
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine1_cmd_buffer_lookahead_sink_last;
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_we;
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_addr;
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable;
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_source_first = litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first;
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_source_last = litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last;
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we;
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr;
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_re = litedramcore_bankmachine1_cmd_buffer_lookahead_source_ready;
+always @(*) begin
+ litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr <= 4'd0;
+ if (litedramcore_bankmachine1_cmd_buffer_lookahead_replace) begin
+ litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine1_cmd_buffer_lookahead_produce - 1'd1);
+ end else begin
+ litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine1_cmd_buffer_lookahead_produce;
+ end
+end
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din;
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & (litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable | litedramcore_bankmachine1_cmd_buffer_lookahead_replace));
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable & litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_re);
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine1_cmd_buffer_lookahead_consume;
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout = litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_dat_r;
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable = (litedramcore_bankmachine1_cmd_buffer_lookahead_level != 5'd16);
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable = (litedramcore_bankmachine1_cmd_buffer_lookahead_level != 1'd0);
+assign litedramcore_bankmachine1_cmd_buffer_sink_ready = ((~litedramcore_bankmachine1_cmd_buffer_source_valid) | litedramcore_bankmachine1_cmd_buffer_source_ready);
+always @(*) begin
+ litedramcore_bankmachine1_next_state <= 3'd0;
+ litedramcore_bankmachine1_next_state <= litedramcore_bankmachine1_state;
+ case (litedramcore_bankmachine1_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
+ if (litedramcore_bankmachine1_cmd_ready) begin
+ litedramcore_bankmachine1_next_state <= 3'd5;
+ end
+ end
+ end
+ 2'd2: begin
+ if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
+ litedramcore_bankmachine1_next_state <= 3'd5;
+ end
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine1_trccon_ready) begin
+ if (litedramcore_bankmachine1_cmd_ready) begin
+ litedramcore_bankmachine1_next_state <= 3'd6;
+ end
+ end
+ end
+ 3'd4: begin
+ if ((~litedramcore_bankmachine1_refresh_req)) begin
+ litedramcore_bankmachine1_next_state <= 1'd0;
+ end
+ end
+ 3'd5: begin
+ litedramcore_bankmachine1_next_state <= 2'd3;
+ end
+ 3'd6: begin
+ litedramcore_bankmachine1_next_state <= 1'd0;
+ end
+ default: begin
+ if (litedramcore_bankmachine1_refresh_req) begin
+ litedramcore_bankmachine1_next_state <= 3'd4;
+ end else begin
+ if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
+ if (litedramcore_bankmachine1_row_opened) begin
+ if (litedramcore_bankmachine1_row_hit) begin
+ if ((litedramcore_bankmachine1_cmd_ready & litedramcore_bankmachine1_auto_precharge)) begin
+ litedramcore_bankmachine1_next_state <= 2'd2;
+ end
+ end else begin
+ litedramcore_bankmachine1_next_state <= 1'd1;
+ end
+ end else begin
+ litedramcore_bankmachine1_next_state <= 2'd3;
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine1_row_open <= 1'd0;
+ case (litedramcore_bankmachine1_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine1_trccon_ready) begin
+ litedramcore_bankmachine1_row_open <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine1_row_close <= 1'd0;
+ case (litedramcore_bankmachine1_state)
+ 1'd1: begin
+ litedramcore_bankmachine1_row_close <= 1'd1;
+ end
+ 2'd2: begin
+ litedramcore_bankmachine1_row_close <= 1'd1;
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ litedramcore_bankmachine1_row_close <= 1'd1;
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine1_cmd_payload_cas <= 1'd0;
+ case (litedramcore_bankmachine1_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine1_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
+ if (litedramcore_bankmachine1_row_opened) begin
+ if (litedramcore_bankmachine1_row_hit) begin
+ litedramcore_bankmachine1_cmd_payload_cas <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine1_cmd_payload_ras <= 1'd0;
+ case (litedramcore_bankmachine1_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
+ litedramcore_bankmachine1_cmd_payload_ras <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine1_trccon_ready) begin
+ litedramcore_bankmachine1_cmd_payload_ras <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine1_cmd_payload_we <= 1'd0;
+ case (litedramcore_bankmachine1_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
+ litedramcore_bankmachine1_cmd_payload_we <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine1_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
+ if (litedramcore_bankmachine1_row_opened) begin
+ if (litedramcore_bankmachine1_row_hit) begin
+ if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
+ litedramcore_bankmachine1_cmd_payload_we <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd0;
+ case (litedramcore_bankmachine1_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine1_trccon_ready) begin
+ litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd0;
+ case (litedramcore_bankmachine1_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
+ litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine1_trccon_ready) begin
+ litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1;
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine1_cmd_payload_is_read <= 1'd0;
+ case (litedramcore_bankmachine1_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine1_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
+ if (litedramcore_bankmachine1_row_opened) begin
+ if (litedramcore_bankmachine1_row_hit) begin
+ if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
+ end else begin
+ litedramcore_bankmachine1_cmd_payload_is_read <= 1'd1;
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine1_cmd_payload_is_write <= 1'd0;
+ case (litedramcore_bankmachine1_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine1_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
+ if (litedramcore_bankmachine1_row_opened) begin
+ if (litedramcore_bankmachine1_row_hit) begin
+ if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
+ litedramcore_bankmachine1_cmd_payload_is_write <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine1_req_wdata_ready <= 1'd0;
+ case (litedramcore_bankmachine1_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine1_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
+ if (litedramcore_bankmachine1_row_opened) begin
+ if (litedramcore_bankmachine1_row_hit) begin
+ if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
+ litedramcore_bankmachine1_req_wdata_ready <= litedramcore_bankmachine1_cmd_ready;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine1_req_rdata_valid <= 1'd0;
+ case (litedramcore_bankmachine1_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine1_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
+ if (litedramcore_bankmachine1_row_opened) begin
+ if (litedramcore_bankmachine1_row_hit) begin
+ if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
+ end else begin
+ litedramcore_bankmachine1_req_rdata_valid <= litedramcore_bankmachine1_cmd_ready;
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine1_refresh_gnt <= 1'd0;
+ case (litedramcore_bankmachine1_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ if (litedramcore_bankmachine1_twtpcon_ready) begin
+ litedramcore_bankmachine1_refresh_gnt <= 1'd1;
+ end
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine1_cmd_valid <= 1'd0;
+ case (litedramcore_bankmachine1_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
+ litedramcore_bankmachine1_cmd_valid <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine1_trccon_ready) begin
+ litedramcore_bankmachine1_cmd_valid <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine1_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
+ if (litedramcore_bankmachine1_row_opened) begin
+ if (litedramcore_bankmachine1_row_hit) begin
+ litedramcore_bankmachine1_cmd_valid <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine2_req_valid;
+assign litedramcore_bankmachine2_req_ready = litedramcore_bankmachine2_cmd_buffer_lookahead_sink_ready;
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine2_req_we;
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine2_req_addr;
+assign litedramcore_bankmachine2_cmd_buffer_sink_valid = litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid;
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine2_cmd_buffer_sink_ready;
+assign litedramcore_bankmachine2_cmd_buffer_sink_first = litedramcore_bankmachine2_cmd_buffer_lookahead_source_first;
+assign litedramcore_bankmachine2_cmd_buffer_sink_last = litedramcore_bankmachine2_cmd_buffer_lookahead_source_last;
+assign litedramcore_bankmachine2_cmd_buffer_sink_payload_we = litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_we;
+assign litedramcore_bankmachine2_cmd_buffer_sink_payload_addr = litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr;
+assign litedramcore_bankmachine2_cmd_buffer_source_ready = (litedramcore_bankmachine2_req_wdata_ready | litedramcore_bankmachine2_req_rdata_valid);
+assign litedramcore_bankmachine2_req_lock = (litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine2_cmd_buffer_source_valid);
+assign litedramcore_bankmachine2_row_hit = (litedramcore_bankmachine2_row == litedramcore_bankmachine2_cmd_buffer_source_payload_addr[21:7]);
+assign litedramcore_bankmachine2_cmd_payload_ba = 2'd2;
+always @(*) begin
+ litedramcore_bankmachine2_cmd_payload_a <= 15'd0;
+ if (litedramcore_bankmachine2_row_col_n_addr_sel) begin
+ litedramcore_bankmachine2_cmd_payload_a <= litedramcore_bankmachine2_cmd_buffer_source_payload_addr[21:7];
+ end else begin
+ litedramcore_bankmachine2_cmd_payload_a <= ((litedramcore_bankmachine2_auto_precharge <<< 4'd10) | {litedramcore_bankmachine2_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
+ end
+end
+assign litedramcore_bankmachine2_twtpcon_valid = ((litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_ready) & litedramcore_bankmachine2_cmd_payload_is_write);
+assign litedramcore_bankmachine2_trccon_valid = ((litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_ready) & litedramcore_bankmachine2_row_open);
+assign litedramcore_bankmachine2_trascon_valid = ((litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_ready) & litedramcore_bankmachine2_row_open);
+always @(*) begin
+ litedramcore_bankmachine2_auto_precharge <= 1'd0;
+ if ((litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine2_cmd_buffer_source_valid)) begin
+ if ((litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr[21:7] != litedramcore_bankmachine2_cmd_buffer_source_payload_addr[21:7])) begin
+ litedramcore_bankmachine2_auto_precharge <= (litedramcore_bankmachine2_row_close == 1'd0);
+ end
+ end
+end
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din = {litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we};
+assign {litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
+assign {litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
+assign {litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
+assign {litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable;
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we = litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid;
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine2_cmd_buffer_lookahead_sink_first;
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine2_cmd_buffer_lookahead_sink_last;
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_we;
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_addr;
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable;
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_source_first = litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first;
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_source_last = litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last;
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we;
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr;
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_re = litedramcore_bankmachine2_cmd_buffer_lookahead_source_ready;
+always @(*) begin
+ litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr <= 4'd0;
+ if (litedramcore_bankmachine2_cmd_buffer_lookahead_replace) begin
+ litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine2_cmd_buffer_lookahead_produce - 1'd1);
+ end else begin
+ litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine2_cmd_buffer_lookahead_produce;
+ end
+end
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din;
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & (litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable | litedramcore_bankmachine2_cmd_buffer_lookahead_replace));
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable & litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_re);
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine2_cmd_buffer_lookahead_consume;
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout = litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_dat_r;
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable = (litedramcore_bankmachine2_cmd_buffer_lookahead_level != 5'd16);
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable = (litedramcore_bankmachine2_cmd_buffer_lookahead_level != 1'd0);
+assign litedramcore_bankmachine2_cmd_buffer_sink_ready = ((~litedramcore_bankmachine2_cmd_buffer_source_valid) | litedramcore_bankmachine2_cmd_buffer_source_ready);
+always @(*) begin
+ litedramcore_bankmachine2_next_state <= 3'd0;
+ litedramcore_bankmachine2_next_state <= litedramcore_bankmachine2_state;
+ case (litedramcore_bankmachine2_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
+ if (litedramcore_bankmachine2_cmd_ready) begin
+ litedramcore_bankmachine2_next_state <= 3'd5;
+ end
+ end
+ end
+ 2'd2: begin
+ if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
+ litedramcore_bankmachine2_next_state <= 3'd5;
+ end
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine2_trccon_ready) begin
+ if (litedramcore_bankmachine2_cmd_ready) begin
+ litedramcore_bankmachine2_next_state <= 3'd6;
+ end
+ end
+ end
+ 3'd4: begin
+ if ((~litedramcore_bankmachine2_refresh_req)) begin
+ litedramcore_bankmachine2_next_state <= 1'd0;
+ end
+ end
+ 3'd5: begin
+ litedramcore_bankmachine2_next_state <= 2'd3;
+ end
+ 3'd6: begin
+ litedramcore_bankmachine2_next_state <= 1'd0;
+ end
+ default: begin
+ if (litedramcore_bankmachine2_refresh_req) begin
+ litedramcore_bankmachine2_next_state <= 3'd4;
+ end else begin
+ if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
+ if (litedramcore_bankmachine2_row_opened) begin
+ if (litedramcore_bankmachine2_row_hit) begin
+ if ((litedramcore_bankmachine2_cmd_ready & litedramcore_bankmachine2_auto_precharge)) begin
+ litedramcore_bankmachine2_next_state <= 2'd2;
+ end
+ end else begin
+ litedramcore_bankmachine2_next_state <= 1'd1;
+ end
+ end else begin
+ litedramcore_bankmachine2_next_state <= 2'd3;
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine2_row_open <= 1'd0;
+ case (litedramcore_bankmachine2_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine2_trccon_ready) begin
+ litedramcore_bankmachine2_row_open <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine2_row_close <= 1'd0;
+ case (litedramcore_bankmachine2_state)
+ 1'd1: begin
+ litedramcore_bankmachine2_row_close <= 1'd1;
+ end
+ 2'd2: begin
+ litedramcore_bankmachine2_row_close <= 1'd1;
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ litedramcore_bankmachine2_row_close <= 1'd1;
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine2_cmd_payload_cas <= 1'd0;
+ case (litedramcore_bankmachine2_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine2_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
+ if (litedramcore_bankmachine2_row_opened) begin
+ if (litedramcore_bankmachine2_row_hit) begin
+ litedramcore_bankmachine2_cmd_payload_cas <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine2_cmd_payload_ras <= 1'd0;
+ case (litedramcore_bankmachine2_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
+ litedramcore_bankmachine2_cmd_payload_ras <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine2_trccon_ready) begin
+ litedramcore_bankmachine2_cmd_payload_ras <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine2_cmd_payload_we <= 1'd0;
+ case (litedramcore_bankmachine2_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
+ litedramcore_bankmachine2_cmd_payload_we <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine2_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
+ if (litedramcore_bankmachine2_row_opened) begin
+ if (litedramcore_bankmachine2_row_hit) begin
+ if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
+ litedramcore_bankmachine2_cmd_payload_we <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd0;
+ case (litedramcore_bankmachine2_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine2_trccon_ready) begin
+ litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd0;
+ case (litedramcore_bankmachine2_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
+ litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine2_trccon_ready) begin
+ litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1;
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine2_cmd_payload_is_read <= 1'd0;
+ case (litedramcore_bankmachine2_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine2_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
+ if (litedramcore_bankmachine2_row_opened) begin
+ if (litedramcore_bankmachine2_row_hit) begin
+ if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
+ end else begin
+ litedramcore_bankmachine2_cmd_payload_is_read <= 1'd1;
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine2_cmd_payload_is_write <= 1'd0;
+ case (litedramcore_bankmachine2_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine2_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
+ if (litedramcore_bankmachine2_row_opened) begin
+ if (litedramcore_bankmachine2_row_hit) begin
+ if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
+ litedramcore_bankmachine2_cmd_payload_is_write <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine2_req_wdata_ready <= 1'd0;
+ case (litedramcore_bankmachine2_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine2_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
+ if (litedramcore_bankmachine2_row_opened) begin
+ if (litedramcore_bankmachine2_row_hit) begin
+ if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
+ litedramcore_bankmachine2_req_wdata_ready <= litedramcore_bankmachine2_cmd_ready;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine2_req_rdata_valid <= 1'd0;
+ case (litedramcore_bankmachine2_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine2_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
+ if (litedramcore_bankmachine2_row_opened) begin
+ if (litedramcore_bankmachine2_row_hit) begin
+ if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
+ end else begin
+ litedramcore_bankmachine2_req_rdata_valid <= litedramcore_bankmachine2_cmd_ready;
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine2_refresh_gnt <= 1'd0;
+ case (litedramcore_bankmachine2_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ if (litedramcore_bankmachine2_twtpcon_ready) begin
+ litedramcore_bankmachine2_refresh_gnt <= 1'd1;
+ end
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine2_cmd_valid <= 1'd0;
+ case (litedramcore_bankmachine2_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
+ litedramcore_bankmachine2_cmd_valid <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine2_trccon_ready) begin
+ litedramcore_bankmachine2_cmd_valid <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine2_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
+ if (litedramcore_bankmachine2_row_opened) begin
+ if (litedramcore_bankmachine2_row_hit) begin
+ litedramcore_bankmachine2_cmd_valid <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine3_req_valid;
+assign litedramcore_bankmachine3_req_ready = litedramcore_bankmachine3_cmd_buffer_lookahead_sink_ready;
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine3_req_we;
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine3_req_addr;
+assign litedramcore_bankmachine3_cmd_buffer_sink_valid = litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid;
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine3_cmd_buffer_sink_ready;
+assign litedramcore_bankmachine3_cmd_buffer_sink_first = litedramcore_bankmachine3_cmd_buffer_lookahead_source_first;
+assign litedramcore_bankmachine3_cmd_buffer_sink_last = litedramcore_bankmachine3_cmd_buffer_lookahead_source_last;
+assign litedramcore_bankmachine3_cmd_buffer_sink_payload_we = litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_we;
+assign litedramcore_bankmachine3_cmd_buffer_sink_payload_addr = litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr;
+assign litedramcore_bankmachine3_cmd_buffer_source_ready = (litedramcore_bankmachine3_req_wdata_ready | litedramcore_bankmachine3_req_rdata_valid);
+assign litedramcore_bankmachine3_req_lock = (litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine3_cmd_buffer_source_valid);
+assign litedramcore_bankmachine3_row_hit = (litedramcore_bankmachine3_row == litedramcore_bankmachine3_cmd_buffer_source_payload_addr[21:7]);
+assign litedramcore_bankmachine3_cmd_payload_ba = 2'd3;
+always @(*) begin
+ litedramcore_bankmachine3_cmd_payload_a <= 15'd0;
+ if (litedramcore_bankmachine3_row_col_n_addr_sel) begin
+ litedramcore_bankmachine3_cmd_payload_a <= litedramcore_bankmachine3_cmd_buffer_source_payload_addr[21:7];
+ end else begin
+ litedramcore_bankmachine3_cmd_payload_a <= ((litedramcore_bankmachine3_auto_precharge <<< 4'd10) | {litedramcore_bankmachine3_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
+ end
+end
+assign litedramcore_bankmachine3_twtpcon_valid = ((litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_ready) & litedramcore_bankmachine3_cmd_payload_is_write);
+assign litedramcore_bankmachine3_trccon_valid = ((litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_ready) & litedramcore_bankmachine3_row_open);
+assign litedramcore_bankmachine3_trascon_valid = ((litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_ready) & litedramcore_bankmachine3_row_open);
+always @(*) begin
+ litedramcore_bankmachine3_auto_precharge <= 1'd0;
+ if ((litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine3_cmd_buffer_source_valid)) begin
+ if ((litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr[21:7] != litedramcore_bankmachine3_cmd_buffer_source_payload_addr[21:7])) begin
+ litedramcore_bankmachine3_auto_precharge <= (litedramcore_bankmachine3_row_close == 1'd0);
+ end
+ end
+end
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din = {litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we};
+assign {litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
+assign {litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
+assign {litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
+assign {litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable;
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we = litedramcore_bankmachine3_cmd_buffer_lookahead_sink_valid;
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine3_cmd_buffer_lookahead_sink_first;
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine3_cmd_buffer_lookahead_sink_last;
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_we;
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_addr;
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable;
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_source_first = litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first;
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_source_last = litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last;
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we;
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr;
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_re = litedramcore_bankmachine3_cmd_buffer_lookahead_source_ready;
+always @(*) begin
+ litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr <= 4'd0;
+ if (litedramcore_bankmachine3_cmd_buffer_lookahead_replace) begin
+ litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine3_cmd_buffer_lookahead_produce - 1'd1);
+ end else begin
+ litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine3_cmd_buffer_lookahead_produce;
+ end
+end
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din;
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & (litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable | litedramcore_bankmachine3_cmd_buffer_lookahead_replace));
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable & litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_re);
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine3_cmd_buffer_lookahead_consume;
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout = litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_dat_r;
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable = (litedramcore_bankmachine3_cmd_buffer_lookahead_level != 5'd16);
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable = (litedramcore_bankmachine3_cmd_buffer_lookahead_level != 1'd0);
+assign litedramcore_bankmachine3_cmd_buffer_sink_ready = ((~litedramcore_bankmachine3_cmd_buffer_source_valid) | litedramcore_bankmachine3_cmd_buffer_source_ready);
+always @(*) begin
+ litedramcore_bankmachine3_next_state <= 3'd0;
+ litedramcore_bankmachine3_next_state <= litedramcore_bankmachine3_state;
+ case (litedramcore_bankmachine3_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
+ if (litedramcore_bankmachine3_cmd_ready) begin
+ litedramcore_bankmachine3_next_state <= 3'd5;
+ end
+ end
+ end
+ 2'd2: begin
+ if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
+ litedramcore_bankmachine3_next_state <= 3'd5;
+ end
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine3_trccon_ready) begin
+ if (litedramcore_bankmachine3_cmd_ready) begin
+ litedramcore_bankmachine3_next_state <= 3'd6;
+ end
+ end
+ end
+ 3'd4: begin
+ if ((~litedramcore_bankmachine3_refresh_req)) begin
+ litedramcore_bankmachine3_next_state <= 1'd0;
+ end
+ end
+ 3'd5: begin
+ litedramcore_bankmachine3_next_state <= 2'd3;
+ end
+ 3'd6: begin
+ litedramcore_bankmachine3_next_state <= 1'd0;
+ end
+ default: begin
+ if (litedramcore_bankmachine3_refresh_req) begin
+ litedramcore_bankmachine3_next_state <= 3'd4;
+ end else begin
+ if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
+ if (litedramcore_bankmachine3_row_opened) begin
+ if (litedramcore_bankmachine3_row_hit) begin
+ if ((litedramcore_bankmachine3_cmd_ready & litedramcore_bankmachine3_auto_precharge)) begin
+ litedramcore_bankmachine3_next_state <= 2'd2;
+ end
+ end else begin
+ litedramcore_bankmachine3_next_state <= 1'd1;
+ end
+ end else begin
+ litedramcore_bankmachine3_next_state <= 2'd3;
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine3_row_open <= 1'd0;
+ case (litedramcore_bankmachine3_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine3_trccon_ready) begin
+ litedramcore_bankmachine3_row_open <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine3_row_close <= 1'd0;
+ case (litedramcore_bankmachine3_state)
+ 1'd1: begin
+ litedramcore_bankmachine3_row_close <= 1'd1;
+ end
+ 2'd2: begin
+ litedramcore_bankmachine3_row_close <= 1'd1;
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ litedramcore_bankmachine3_row_close <= 1'd1;
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine3_refresh_gnt <= 1'd0;
+ case (litedramcore_bankmachine3_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ if (litedramcore_bankmachine3_twtpcon_ready) begin
+ litedramcore_bankmachine3_refresh_gnt <= 1'd1;
+ end
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine3_cmd_payload_cas <= 1'd0;
+ case (litedramcore_bankmachine3_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine3_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
+ if (litedramcore_bankmachine3_row_opened) begin
+ if (litedramcore_bankmachine3_row_hit) begin
+ litedramcore_bankmachine3_cmd_payload_cas <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine3_cmd_payload_ras <= 1'd0;
+ case (litedramcore_bankmachine3_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
+ litedramcore_bankmachine3_cmd_payload_ras <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine3_trccon_ready) begin
+ litedramcore_bankmachine3_cmd_payload_ras <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine3_cmd_payload_we <= 1'd0;
+ case (litedramcore_bankmachine3_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
+ litedramcore_bankmachine3_cmd_payload_we <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine3_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
+ if (litedramcore_bankmachine3_row_opened) begin
+ if (litedramcore_bankmachine3_row_hit) begin
+ if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
+ litedramcore_bankmachine3_cmd_payload_we <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd0;
+ case (litedramcore_bankmachine3_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine3_trccon_ready) begin
+ litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd0;
+ case (litedramcore_bankmachine3_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
+ litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine3_trccon_ready) begin
+ litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1;
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine3_cmd_payload_is_read <= 1'd0;
+ case (litedramcore_bankmachine3_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine3_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
+ if (litedramcore_bankmachine3_row_opened) begin
+ if (litedramcore_bankmachine3_row_hit) begin
+ if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
+ end else begin
+ litedramcore_bankmachine3_cmd_payload_is_read <= 1'd1;
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine3_cmd_payload_is_write <= 1'd0;
+ case (litedramcore_bankmachine3_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine3_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
+ if (litedramcore_bankmachine3_row_opened) begin
+ if (litedramcore_bankmachine3_row_hit) begin
+ if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
+ litedramcore_bankmachine3_cmd_payload_is_write <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine3_req_wdata_ready <= 1'd0;
+ case (litedramcore_bankmachine3_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine3_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
+ if (litedramcore_bankmachine3_row_opened) begin
+ if (litedramcore_bankmachine3_row_hit) begin
+ if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
+ litedramcore_bankmachine3_req_wdata_ready <= litedramcore_bankmachine3_cmd_ready;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine3_req_rdata_valid <= 1'd0;
+ case (litedramcore_bankmachine3_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine3_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
+ if (litedramcore_bankmachine3_row_opened) begin
+ if (litedramcore_bankmachine3_row_hit) begin
+ if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
+ end else begin
+ litedramcore_bankmachine3_req_rdata_valid <= litedramcore_bankmachine3_cmd_ready;
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine3_cmd_valid <= 1'd0;
+ case (litedramcore_bankmachine3_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
+ litedramcore_bankmachine3_cmd_valid <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine3_trccon_ready) begin
+ litedramcore_bankmachine3_cmd_valid <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine3_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
+ if (litedramcore_bankmachine3_row_opened) begin
+ if (litedramcore_bankmachine3_row_hit) begin
+ litedramcore_bankmachine3_cmd_valid <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine4_req_valid;
+assign litedramcore_bankmachine4_req_ready = litedramcore_bankmachine4_cmd_buffer_lookahead_sink_ready;
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine4_req_we;
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine4_req_addr;
+assign litedramcore_bankmachine4_cmd_buffer_sink_valid = litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid;
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine4_cmd_buffer_sink_ready;
+assign litedramcore_bankmachine4_cmd_buffer_sink_first = litedramcore_bankmachine4_cmd_buffer_lookahead_source_first;
+assign litedramcore_bankmachine4_cmd_buffer_sink_last = litedramcore_bankmachine4_cmd_buffer_lookahead_source_last;
+assign litedramcore_bankmachine4_cmd_buffer_sink_payload_we = litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_we;
+assign litedramcore_bankmachine4_cmd_buffer_sink_payload_addr = litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr;
+assign litedramcore_bankmachine4_cmd_buffer_source_ready = (litedramcore_bankmachine4_req_wdata_ready | litedramcore_bankmachine4_req_rdata_valid);
+assign litedramcore_bankmachine4_req_lock = (litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine4_cmd_buffer_source_valid);
+assign litedramcore_bankmachine4_row_hit = (litedramcore_bankmachine4_row == litedramcore_bankmachine4_cmd_buffer_source_payload_addr[21:7]);
+assign litedramcore_bankmachine4_cmd_payload_ba = 3'd4;
+always @(*) begin
+ litedramcore_bankmachine4_cmd_payload_a <= 15'd0;
+ if (litedramcore_bankmachine4_row_col_n_addr_sel) begin
+ litedramcore_bankmachine4_cmd_payload_a <= litedramcore_bankmachine4_cmd_buffer_source_payload_addr[21:7];
+ end else begin
+ litedramcore_bankmachine4_cmd_payload_a <= ((litedramcore_bankmachine4_auto_precharge <<< 4'd10) | {litedramcore_bankmachine4_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
+ end
+end
+assign litedramcore_bankmachine4_twtpcon_valid = ((litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_ready) & litedramcore_bankmachine4_cmd_payload_is_write);
+assign litedramcore_bankmachine4_trccon_valid = ((litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_ready) & litedramcore_bankmachine4_row_open);
+assign litedramcore_bankmachine4_trascon_valid = ((litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_ready) & litedramcore_bankmachine4_row_open);
+always @(*) begin
+ litedramcore_bankmachine4_auto_precharge <= 1'd0;
+ if ((litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine4_cmd_buffer_source_valid)) begin
+ if ((litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr[21:7] != litedramcore_bankmachine4_cmd_buffer_source_payload_addr[21:7])) begin
+ litedramcore_bankmachine4_auto_precharge <= (litedramcore_bankmachine4_row_close == 1'd0);
+ end
+ end
+end
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din = {litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we};
+assign {litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout;
+assign {litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout;
+assign {litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout;
+assign {litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout;
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable;
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we = litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid;
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine4_cmd_buffer_lookahead_sink_first;
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine4_cmd_buffer_lookahead_sink_last;
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_we;
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_addr;
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable;
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_source_first = litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first;
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_source_last = litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last;
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we;
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr;
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_re = litedramcore_bankmachine4_cmd_buffer_lookahead_source_ready;
+always @(*) begin
+ litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr <= 4'd0;
+ if (litedramcore_bankmachine4_cmd_buffer_lookahead_replace) begin
+ litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine4_cmd_buffer_lookahead_produce - 1'd1);
+ end else begin
+ litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine4_cmd_buffer_lookahead_produce;
+ end
+end
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din;
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & (litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable | litedramcore_bankmachine4_cmd_buffer_lookahead_replace));
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable & litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_re);
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine4_cmd_buffer_lookahead_consume;
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout = litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_dat_r;
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable = (litedramcore_bankmachine4_cmd_buffer_lookahead_level != 5'd16);
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable = (litedramcore_bankmachine4_cmd_buffer_lookahead_level != 1'd0);
+assign litedramcore_bankmachine4_cmd_buffer_sink_ready = ((~litedramcore_bankmachine4_cmd_buffer_source_valid) | litedramcore_bankmachine4_cmd_buffer_source_ready);
+always @(*) begin
+ litedramcore_bankmachine4_next_state <= 3'd0;
+ litedramcore_bankmachine4_next_state <= litedramcore_bankmachine4_state;
+ case (litedramcore_bankmachine4_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
+ if (litedramcore_bankmachine4_cmd_ready) begin
+ litedramcore_bankmachine4_next_state <= 3'd5;
+ end
+ end
+ end
+ 2'd2: begin
+ if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
+ litedramcore_bankmachine4_next_state <= 3'd5;
+ end
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine4_trccon_ready) begin
+ if (litedramcore_bankmachine4_cmd_ready) begin
+ litedramcore_bankmachine4_next_state <= 3'd6;
+ end
+ end
+ end
+ 3'd4: begin
+ if ((~litedramcore_bankmachine4_refresh_req)) begin
+ litedramcore_bankmachine4_next_state <= 1'd0;
+ end
+ end
+ 3'd5: begin
+ litedramcore_bankmachine4_next_state <= 2'd3;
+ end
+ 3'd6: begin
+ litedramcore_bankmachine4_next_state <= 1'd0;
+ end
+ default: begin
+ if (litedramcore_bankmachine4_refresh_req) begin
+ litedramcore_bankmachine4_next_state <= 3'd4;
+ end else begin
+ if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin
+ if (litedramcore_bankmachine4_row_opened) begin
+ if (litedramcore_bankmachine4_row_hit) begin
+ if ((litedramcore_bankmachine4_cmd_ready & litedramcore_bankmachine4_auto_precharge)) begin
+ litedramcore_bankmachine4_next_state <= 2'd2;
+ end
+ end else begin
+ litedramcore_bankmachine4_next_state <= 1'd1;
+ end
+ end else begin
+ litedramcore_bankmachine4_next_state <= 2'd3;
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine4_row_open <= 1'd0;
+ case (litedramcore_bankmachine4_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine4_trccon_ready) begin
+ litedramcore_bankmachine4_row_open <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine4_row_close <= 1'd0;
+ case (litedramcore_bankmachine4_state)
+ 1'd1: begin
+ litedramcore_bankmachine4_row_close <= 1'd1;
+ end
+ 2'd2: begin
+ litedramcore_bankmachine4_row_close <= 1'd1;
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ litedramcore_bankmachine4_row_close <= 1'd1;
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine4_cmd_payload_cas <= 1'd0;
+ case (litedramcore_bankmachine4_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine4_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin
+ if (litedramcore_bankmachine4_row_opened) begin
+ if (litedramcore_bankmachine4_row_hit) begin
+ litedramcore_bankmachine4_cmd_payload_cas <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine4_cmd_payload_ras <= 1'd0;
+ case (litedramcore_bankmachine4_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
+ litedramcore_bankmachine4_cmd_payload_ras <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine4_trccon_ready) begin
+ litedramcore_bankmachine4_cmd_payload_ras <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine4_cmd_payload_we <= 1'd0;
+ case (litedramcore_bankmachine4_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
+ litedramcore_bankmachine4_cmd_payload_we <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine4_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin
+ if (litedramcore_bankmachine4_row_opened) begin
+ if (litedramcore_bankmachine4_row_hit) begin
+ if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
+ litedramcore_bankmachine4_cmd_payload_we <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd0;
+ case (litedramcore_bankmachine4_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine4_trccon_ready) begin
+ litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd0;
+ case (litedramcore_bankmachine4_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
+ litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine4_trccon_ready) begin
+ litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine4_cmd_payload_is_read <= 1'd0;
+ case (litedramcore_bankmachine4_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine4_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin
+ if (litedramcore_bankmachine4_row_opened) begin
+ if (litedramcore_bankmachine4_row_hit) begin
+ if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
+ end else begin
+ litedramcore_bankmachine4_cmd_payload_is_read <= 1'd1;
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine4_cmd_payload_is_write <= 1'd0;
+ case (litedramcore_bankmachine4_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine4_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin
+ if (litedramcore_bankmachine4_row_opened) begin
+ if (litedramcore_bankmachine4_row_hit) begin
+ if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
+ litedramcore_bankmachine4_cmd_payload_is_write <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine4_req_wdata_ready <= 1'd0;
+ case (litedramcore_bankmachine4_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine4_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin
+ if (litedramcore_bankmachine4_row_opened) begin
+ if (litedramcore_bankmachine4_row_hit) begin
+ if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
+ litedramcore_bankmachine4_req_wdata_ready <= litedramcore_bankmachine4_cmd_ready;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine4_req_rdata_valid <= 1'd0;
+ case (litedramcore_bankmachine4_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine4_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin
+ if (litedramcore_bankmachine4_row_opened) begin
+ if (litedramcore_bankmachine4_row_hit) begin
+ if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
+ end else begin
+ litedramcore_bankmachine4_req_rdata_valid <= litedramcore_bankmachine4_cmd_ready;
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine4_refresh_gnt <= 1'd0;
+ case (litedramcore_bankmachine4_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ if (litedramcore_bankmachine4_twtpcon_ready) begin
+ litedramcore_bankmachine4_refresh_gnt <= 1'd1;
+ end
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine4_cmd_valid <= 1'd0;
+ case (litedramcore_bankmachine4_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
+ litedramcore_bankmachine4_cmd_valid <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine4_trccon_ready) begin
+ litedramcore_bankmachine4_cmd_valid <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine4_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin
+ if (litedramcore_bankmachine4_row_opened) begin
+ if (litedramcore_bankmachine4_row_hit) begin
+ litedramcore_bankmachine4_cmd_valid <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine5_req_valid;
+assign litedramcore_bankmachine5_req_ready = litedramcore_bankmachine5_cmd_buffer_lookahead_sink_ready;
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine5_req_we;
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine5_req_addr;
+assign litedramcore_bankmachine5_cmd_buffer_sink_valid = litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid;
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine5_cmd_buffer_sink_ready;
+assign litedramcore_bankmachine5_cmd_buffer_sink_first = litedramcore_bankmachine5_cmd_buffer_lookahead_source_first;
+assign litedramcore_bankmachine5_cmd_buffer_sink_last = litedramcore_bankmachine5_cmd_buffer_lookahead_source_last;
+assign litedramcore_bankmachine5_cmd_buffer_sink_payload_we = litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_we;
+assign litedramcore_bankmachine5_cmd_buffer_sink_payload_addr = litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr;
+assign litedramcore_bankmachine5_cmd_buffer_source_ready = (litedramcore_bankmachine5_req_wdata_ready | litedramcore_bankmachine5_req_rdata_valid);
+assign litedramcore_bankmachine5_req_lock = (litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine5_cmd_buffer_source_valid);
+assign litedramcore_bankmachine5_row_hit = (litedramcore_bankmachine5_row == litedramcore_bankmachine5_cmd_buffer_source_payload_addr[21:7]);
+assign litedramcore_bankmachine5_cmd_payload_ba = 3'd5;
+always @(*) begin
+ litedramcore_bankmachine5_cmd_payload_a <= 15'd0;
+ if (litedramcore_bankmachine5_row_col_n_addr_sel) begin
+ litedramcore_bankmachine5_cmd_payload_a <= litedramcore_bankmachine5_cmd_buffer_source_payload_addr[21:7];
+ end else begin
+ litedramcore_bankmachine5_cmd_payload_a <= ((litedramcore_bankmachine5_auto_precharge <<< 4'd10) | {litedramcore_bankmachine5_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
+ end
+end
+assign litedramcore_bankmachine5_twtpcon_valid = ((litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_ready) & litedramcore_bankmachine5_cmd_payload_is_write);
+assign litedramcore_bankmachine5_trccon_valid = ((litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_ready) & litedramcore_bankmachine5_row_open);
+assign litedramcore_bankmachine5_trascon_valid = ((litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_ready) & litedramcore_bankmachine5_row_open);
+always @(*) begin
+ litedramcore_bankmachine5_auto_precharge <= 1'd0;
+ if ((litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine5_cmd_buffer_source_valid)) begin
+ if ((litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr[21:7] != litedramcore_bankmachine5_cmd_buffer_source_payload_addr[21:7])) begin
+ litedramcore_bankmachine5_auto_precharge <= (litedramcore_bankmachine5_row_close == 1'd0);
+ end
+ end
+end
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din = {litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we};
+assign {litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout;
+assign {litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout;
+assign {litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout;
+assign {litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout;
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable;
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we = litedramcore_bankmachine5_cmd_buffer_lookahead_sink_valid;
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine5_cmd_buffer_lookahead_sink_first;
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine5_cmd_buffer_lookahead_sink_last;
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_we;
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_addr;
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable;
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_source_first = litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first;
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_source_last = litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last;
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we;
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr;
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_re = litedramcore_bankmachine5_cmd_buffer_lookahead_source_ready;
+always @(*) begin
+ litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr <= 4'd0;
+ if (litedramcore_bankmachine5_cmd_buffer_lookahead_replace) begin
+ litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine5_cmd_buffer_lookahead_produce - 1'd1);
+ end else begin
+ litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine5_cmd_buffer_lookahead_produce;
+ end
+end
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din;
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & (litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable | litedramcore_bankmachine5_cmd_buffer_lookahead_replace));
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable & litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_re);
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine5_cmd_buffer_lookahead_consume;
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout = litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_dat_r;
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable = (litedramcore_bankmachine5_cmd_buffer_lookahead_level != 5'd16);
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable = (litedramcore_bankmachine5_cmd_buffer_lookahead_level != 1'd0);
+assign litedramcore_bankmachine5_cmd_buffer_sink_ready = ((~litedramcore_bankmachine5_cmd_buffer_source_valid) | litedramcore_bankmachine5_cmd_buffer_source_ready);
+always @(*) begin
+ litedramcore_bankmachine5_next_state <= 3'd0;
+ litedramcore_bankmachine5_next_state <= litedramcore_bankmachine5_state;
+ case (litedramcore_bankmachine5_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
+ if (litedramcore_bankmachine5_cmd_ready) begin
+ litedramcore_bankmachine5_next_state <= 3'd5;
+ end
+ end
+ end
+ 2'd2: begin
+ if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
+ litedramcore_bankmachine5_next_state <= 3'd5;
+ end
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine5_trccon_ready) begin
+ if (litedramcore_bankmachine5_cmd_ready) begin
+ litedramcore_bankmachine5_next_state <= 3'd6;
+ end
+ end
+ end
+ 3'd4: begin
+ if ((~litedramcore_bankmachine5_refresh_req)) begin
+ litedramcore_bankmachine5_next_state <= 1'd0;
+ end
+ end
+ 3'd5: begin
+ litedramcore_bankmachine5_next_state <= 2'd3;
+ end
+ 3'd6: begin
+ litedramcore_bankmachine5_next_state <= 1'd0;
+ end
+ default: begin
+ if (litedramcore_bankmachine5_refresh_req) begin
+ litedramcore_bankmachine5_next_state <= 3'd4;
+ end else begin
+ if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
+ if (litedramcore_bankmachine5_row_opened) begin
+ if (litedramcore_bankmachine5_row_hit) begin
+ if ((litedramcore_bankmachine5_cmd_ready & litedramcore_bankmachine5_auto_precharge)) begin
+ litedramcore_bankmachine5_next_state <= 2'd2;
+ end
+ end else begin
+ litedramcore_bankmachine5_next_state <= 1'd1;
+ end
+ end else begin
+ litedramcore_bankmachine5_next_state <= 2'd3;
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine5_row_open <= 1'd0;
+ case (litedramcore_bankmachine5_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine5_trccon_ready) begin
+ litedramcore_bankmachine5_row_open <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine5_row_close <= 1'd0;
+ case (litedramcore_bankmachine5_state)
+ 1'd1: begin
+ litedramcore_bankmachine5_row_close <= 1'd1;
+ end
+ 2'd2: begin
+ litedramcore_bankmachine5_row_close <= 1'd1;
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ litedramcore_bankmachine5_row_close <= 1'd1;
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine5_cmd_payload_cas <= 1'd0;
+ case (litedramcore_bankmachine5_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine5_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
+ if (litedramcore_bankmachine5_row_opened) begin
+ if (litedramcore_bankmachine5_row_hit) begin
+ litedramcore_bankmachine5_cmd_payload_cas <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine5_cmd_payload_ras <= 1'd0;
+ case (litedramcore_bankmachine5_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
+ litedramcore_bankmachine5_cmd_payload_ras <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine5_trccon_ready) begin
+ litedramcore_bankmachine5_cmd_payload_ras <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine5_cmd_payload_we <= 1'd0;
+ case (litedramcore_bankmachine5_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
+ litedramcore_bankmachine5_cmd_payload_we <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine5_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
+ if (litedramcore_bankmachine5_row_opened) begin
+ if (litedramcore_bankmachine5_row_hit) begin
+ if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
+ litedramcore_bankmachine5_cmd_payload_we <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd0;
+ case (litedramcore_bankmachine5_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine5_trccon_ready) begin
+ litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd0;
+ case (litedramcore_bankmachine5_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
+ litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine5_trccon_ready) begin
+ litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1;
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine5_cmd_payload_is_read <= 1'd0;
+ case (litedramcore_bankmachine5_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine5_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
+ if (litedramcore_bankmachine5_row_opened) begin
+ if (litedramcore_bankmachine5_row_hit) begin
+ if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
+ end else begin
+ litedramcore_bankmachine5_cmd_payload_is_read <= 1'd1;
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine5_cmd_payload_is_write <= 1'd0;
+ case (litedramcore_bankmachine5_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine5_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
+ if (litedramcore_bankmachine5_row_opened) begin
+ if (litedramcore_bankmachine5_row_hit) begin
+ if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
+ litedramcore_bankmachine5_cmd_payload_is_write <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine5_req_wdata_ready <= 1'd0;
+ case (litedramcore_bankmachine5_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine5_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
+ if (litedramcore_bankmachine5_row_opened) begin
+ if (litedramcore_bankmachine5_row_hit) begin
+ if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
+ litedramcore_bankmachine5_req_wdata_ready <= litedramcore_bankmachine5_cmd_ready;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine5_req_rdata_valid <= 1'd0;
+ case (litedramcore_bankmachine5_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine5_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
+ if (litedramcore_bankmachine5_row_opened) begin
+ if (litedramcore_bankmachine5_row_hit) begin
+ if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
+ end else begin
+ litedramcore_bankmachine5_req_rdata_valid <= litedramcore_bankmachine5_cmd_ready;
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine5_refresh_gnt <= 1'd0;
+ case (litedramcore_bankmachine5_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ if (litedramcore_bankmachine5_twtpcon_ready) begin
+ litedramcore_bankmachine5_refresh_gnt <= 1'd1;
+ end
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine5_cmd_valid <= 1'd0;
+ case (litedramcore_bankmachine5_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
+ litedramcore_bankmachine5_cmd_valid <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine5_trccon_ready) begin
+ litedramcore_bankmachine5_cmd_valid <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine5_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
+ if (litedramcore_bankmachine5_row_opened) begin
+ if (litedramcore_bankmachine5_row_hit) begin
+ litedramcore_bankmachine5_cmd_valid <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine6_req_valid;
+assign litedramcore_bankmachine6_req_ready = litedramcore_bankmachine6_cmd_buffer_lookahead_sink_ready;
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine6_req_we;
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine6_req_addr;
+assign litedramcore_bankmachine6_cmd_buffer_sink_valid = litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid;
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine6_cmd_buffer_sink_ready;
+assign litedramcore_bankmachine6_cmd_buffer_sink_first = litedramcore_bankmachine6_cmd_buffer_lookahead_source_first;
+assign litedramcore_bankmachine6_cmd_buffer_sink_last = litedramcore_bankmachine6_cmd_buffer_lookahead_source_last;
+assign litedramcore_bankmachine6_cmd_buffer_sink_payload_we = litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_we;
+assign litedramcore_bankmachine6_cmd_buffer_sink_payload_addr = litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr;
+assign litedramcore_bankmachine6_cmd_buffer_source_ready = (litedramcore_bankmachine6_req_wdata_ready | litedramcore_bankmachine6_req_rdata_valid);
+assign litedramcore_bankmachine6_req_lock = (litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine6_cmd_buffer_source_valid);
+assign litedramcore_bankmachine6_row_hit = (litedramcore_bankmachine6_row == litedramcore_bankmachine6_cmd_buffer_source_payload_addr[21:7]);
+assign litedramcore_bankmachine6_cmd_payload_ba = 3'd6;
+always @(*) begin
+ litedramcore_bankmachine6_cmd_payload_a <= 15'd0;
+ if (litedramcore_bankmachine6_row_col_n_addr_sel) begin
+ litedramcore_bankmachine6_cmd_payload_a <= litedramcore_bankmachine6_cmd_buffer_source_payload_addr[21:7];
+ end else begin
+ litedramcore_bankmachine6_cmd_payload_a <= ((litedramcore_bankmachine6_auto_precharge <<< 4'd10) | {litedramcore_bankmachine6_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
+ end
+end
+assign litedramcore_bankmachine6_twtpcon_valid = ((litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_ready) & litedramcore_bankmachine6_cmd_payload_is_write);
+assign litedramcore_bankmachine6_trccon_valid = ((litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_ready) & litedramcore_bankmachine6_row_open);
+assign litedramcore_bankmachine6_trascon_valid = ((litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_ready) & litedramcore_bankmachine6_row_open);
+always @(*) begin
+ litedramcore_bankmachine6_auto_precharge <= 1'd0;
+ if ((litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine6_cmd_buffer_source_valid)) begin
+ if ((litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr[21:7] != litedramcore_bankmachine6_cmd_buffer_source_payload_addr[21:7])) begin
+ litedramcore_bankmachine6_auto_precharge <= (litedramcore_bankmachine6_row_close == 1'd0);
+ end
+ end
+end
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din = {litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we};
+assign {litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout;
+assign {litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout;
+assign {litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout;
+assign {litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout;
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable;
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we = litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid;
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine6_cmd_buffer_lookahead_sink_first;
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine6_cmd_buffer_lookahead_sink_last;
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_we;
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_addr;
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable;
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_source_first = litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first;
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_source_last = litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last;
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we;
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr;
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_re = litedramcore_bankmachine6_cmd_buffer_lookahead_source_ready;
+always @(*) begin
+ litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr <= 4'd0;
+ if (litedramcore_bankmachine6_cmd_buffer_lookahead_replace) begin
+ litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine6_cmd_buffer_lookahead_produce - 1'd1);
+ end else begin
+ litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine6_cmd_buffer_lookahead_produce;
+ end
+end
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din;
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & (litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable | litedramcore_bankmachine6_cmd_buffer_lookahead_replace));
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable & litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_re);
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine6_cmd_buffer_lookahead_consume;
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout = litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_dat_r;
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable = (litedramcore_bankmachine6_cmd_buffer_lookahead_level != 5'd16);
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable = (litedramcore_bankmachine6_cmd_buffer_lookahead_level != 1'd0);
+assign litedramcore_bankmachine6_cmd_buffer_sink_ready = ((~litedramcore_bankmachine6_cmd_buffer_source_valid) | litedramcore_bankmachine6_cmd_buffer_source_ready);
+always @(*) begin
+ litedramcore_bankmachine6_next_state <= 3'd0;
+ litedramcore_bankmachine6_next_state <= litedramcore_bankmachine6_state;
+ case (litedramcore_bankmachine6_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
+ if (litedramcore_bankmachine6_cmd_ready) begin
+ litedramcore_bankmachine6_next_state <= 3'd5;
+ end
+ end
+ end
+ 2'd2: begin
+ if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
+ litedramcore_bankmachine6_next_state <= 3'd5;
+ end
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine6_trccon_ready) begin
+ if (litedramcore_bankmachine6_cmd_ready) begin
+ litedramcore_bankmachine6_next_state <= 3'd6;
+ end
+ end
+ end
+ 3'd4: begin
+ if ((~litedramcore_bankmachine6_refresh_req)) begin
+ litedramcore_bankmachine6_next_state <= 1'd0;
+ end
+ end
+ 3'd5: begin
+ litedramcore_bankmachine6_next_state <= 2'd3;
+ end
+ 3'd6: begin
+ litedramcore_bankmachine6_next_state <= 1'd0;
+ end
+ default: begin
+ if (litedramcore_bankmachine6_refresh_req) begin
+ litedramcore_bankmachine6_next_state <= 3'd4;
+ end else begin
+ if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin
+ if (litedramcore_bankmachine6_row_opened) begin
+ if (litedramcore_bankmachine6_row_hit) begin
+ if ((litedramcore_bankmachine6_cmd_ready & litedramcore_bankmachine6_auto_precharge)) begin
+ litedramcore_bankmachine6_next_state <= 2'd2;
+ end
+ end else begin
+ litedramcore_bankmachine6_next_state <= 1'd1;
+ end
+ end else begin
+ litedramcore_bankmachine6_next_state <= 2'd3;
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine6_row_open <= 1'd0;
+ case (litedramcore_bankmachine6_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine6_trccon_ready) begin
+ litedramcore_bankmachine6_row_open <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine6_row_close <= 1'd0;
+ case (litedramcore_bankmachine6_state)
+ 1'd1: begin
+ litedramcore_bankmachine6_row_close <= 1'd1;
+ end
+ 2'd2: begin
+ litedramcore_bankmachine6_row_close <= 1'd1;
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ litedramcore_bankmachine6_row_close <= 1'd1;
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine6_cmd_payload_cas <= 1'd0;
+ case (litedramcore_bankmachine6_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine6_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin
+ if (litedramcore_bankmachine6_row_opened) begin
+ if (litedramcore_bankmachine6_row_hit) begin
+ litedramcore_bankmachine6_cmd_payload_cas <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine6_cmd_payload_ras <= 1'd0;
+ case (litedramcore_bankmachine6_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
+ litedramcore_bankmachine6_cmd_payload_ras <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine6_trccon_ready) begin
+ litedramcore_bankmachine6_cmd_payload_ras <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine6_cmd_payload_we <= 1'd0;
+ case (litedramcore_bankmachine6_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
+ litedramcore_bankmachine6_cmd_payload_we <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine6_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin
+ if (litedramcore_bankmachine6_row_opened) begin
+ if (litedramcore_bankmachine6_row_hit) begin
+ if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
+ litedramcore_bankmachine6_cmd_payload_we <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd0;
+ case (litedramcore_bankmachine6_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine6_trccon_ready) begin
+ litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd0;
+ case (litedramcore_bankmachine6_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
+ litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine6_trccon_ready) begin
+ litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine6_cmd_payload_is_read <= 1'd0;
+ case (litedramcore_bankmachine6_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine6_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin
+ if (litedramcore_bankmachine6_row_opened) begin
+ if (litedramcore_bankmachine6_row_hit) begin
+ if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
+ end else begin
+ litedramcore_bankmachine6_cmd_payload_is_read <= 1'd1;
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine6_cmd_payload_is_write <= 1'd0;
+ case (litedramcore_bankmachine6_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine6_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin
+ if (litedramcore_bankmachine6_row_opened) begin
+ if (litedramcore_bankmachine6_row_hit) begin
+ if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
+ litedramcore_bankmachine6_cmd_payload_is_write <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine6_req_wdata_ready <= 1'd0;
+ case (litedramcore_bankmachine6_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine6_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin
+ if (litedramcore_bankmachine6_row_opened) begin
+ if (litedramcore_bankmachine6_row_hit) begin
+ if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
+ litedramcore_bankmachine6_req_wdata_ready <= litedramcore_bankmachine6_cmd_ready;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine6_req_rdata_valid <= 1'd0;
+ case (litedramcore_bankmachine6_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine6_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin
+ if (litedramcore_bankmachine6_row_opened) begin
+ if (litedramcore_bankmachine6_row_hit) begin
+ if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
+ end else begin
+ litedramcore_bankmachine6_req_rdata_valid <= litedramcore_bankmachine6_cmd_ready;
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine6_refresh_gnt <= 1'd0;
+ case (litedramcore_bankmachine6_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ if (litedramcore_bankmachine6_twtpcon_ready) begin
+ litedramcore_bankmachine6_refresh_gnt <= 1'd1;
+ end
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine6_cmd_valid <= 1'd0;
+ case (litedramcore_bankmachine6_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
+ litedramcore_bankmachine6_cmd_valid <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine6_trccon_ready) begin
+ litedramcore_bankmachine6_cmd_valid <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine6_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin
+ if (litedramcore_bankmachine6_row_opened) begin
+ if (litedramcore_bankmachine6_row_hit) begin
+ litedramcore_bankmachine6_cmd_valid <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine7_req_valid;
+assign litedramcore_bankmachine7_req_ready = litedramcore_bankmachine7_cmd_buffer_lookahead_sink_ready;
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine7_req_we;
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine7_req_addr;
+assign litedramcore_bankmachine7_cmd_buffer_sink_valid = litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid;
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine7_cmd_buffer_sink_ready;
+assign litedramcore_bankmachine7_cmd_buffer_sink_first = litedramcore_bankmachine7_cmd_buffer_lookahead_source_first;
+assign litedramcore_bankmachine7_cmd_buffer_sink_last = litedramcore_bankmachine7_cmd_buffer_lookahead_source_last;
+assign litedramcore_bankmachine7_cmd_buffer_sink_payload_we = litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_we;
+assign litedramcore_bankmachine7_cmd_buffer_sink_payload_addr = litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr;
+assign litedramcore_bankmachine7_cmd_buffer_source_ready = (litedramcore_bankmachine7_req_wdata_ready | litedramcore_bankmachine7_req_rdata_valid);
+assign litedramcore_bankmachine7_req_lock = (litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine7_cmd_buffer_source_valid);
+assign litedramcore_bankmachine7_row_hit = (litedramcore_bankmachine7_row == litedramcore_bankmachine7_cmd_buffer_source_payload_addr[21:7]);
+assign litedramcore_bankmachine7_cmd_payload_ba = 3'd7;
+always @(*) begin
+ litedramcore_bankmachine7_cmd_payload_a <= 15'd0;
+ if (litedramcore_bankmachine7_row_col_n_addr_sel) begin
+ litedramcore_bankmachine7_cmd_payload_a <= litedramcore_bankmachine7_cmd_buffer_source_payload_addr[21:7];
+ end else begin
+ litedramcore_bankmachine7_cmd_payload_a <= ((litedramcore_bankmachine7_auto_precharge <<< 4'd10) | {litedramcore_bankmachine7_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
+ end
+end
+assign litedramcore_bankmachine7_twtpcon_valid = ((litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_ready) & litedramcore_bankmachine7_cmd_payload_is_write);
+assign litedramcore_bankmachine7_trccon_valid = ((litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_ready) & litedramcore_bankmachine7_row_open);
+assign litedramcore_bankmachine7_trascon_valid = ((litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_ready) & litedramcore_bankmachine7_row_open);
+always @(*) begin
+ litedramcore_bankmachine7_auto_precharge <= 1'd0;
+ if ((litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine7_cmd_buffer_source_valid)) begin
+ if ((litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr[21:7] != litedramcore_bankmachine7_cmd_buffer_source_payload_addr[21:7])) begin
+ litedramcore_bankmachine7_auto_precharge <= (litedramcore_bankmachine7_row_close == 1'd0);
+ end
+ end
+end
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din = {litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we};
+assign {litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout;
+assign {litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout;
+assign {litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout;
+assign {litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout;
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable;
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we = litedramcore_bankmachine7_cmd_buffer_lookahead_sink_valid;
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine7_cmd_buffer_lookahead_sink_first;
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine7_cmd_buffer_lookahead_sink_last;
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_we;
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_addr;
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable;
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_source_first = litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first;
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_source_last = litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last;
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we;
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr;
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_re = litedramcore_bankmachine7_cmd_buffer_lookahead_source_ready;
+always @(*) begin
+ litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr <= 4'd0;
+ if (litedramcore_bankmachine7_cmd_buffer_lookahead_replace) begin
+ litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine7_cmd_buffer_lookahead_produce - 1'd1);
+ end else begin
+ litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine7_cmd_buffer_lookahead_produce;
+ end
+end
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din;
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & (litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable | litedramcore_bankmachine7_cmd_buffer_lookahead_replace));
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable & litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_re);
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine7_cmd_buffer_lookahead_consume;
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout = litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_dat_r;
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable = (litedramcore_bankmachine7_cmd_buffer_lookahead_level != 5'd16);
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable = (litedramcore_bankmachine7_cmd_buffer_lookahead_level != 1'd0);
+assign litedramcore_bankmachine7_cmd_buffer_sink_ready = ((~litedramcore_bankmachine7_cmd_buffer_source_valid) | litedramcore_bankmachine7_cmd_buffer_source_ready);
+always @(*) begin
+ litedramcore_bankmachine7_next_state <= 3'd0;
+ litedramcore_bankmachine7_next_state <= litedramcore_bankmachine7_state;
+ case (litedramcore_bankmachine7_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
+ if (litedramcore_bankmachine7_cmd_ready) begin
+ litedramcore_bankmachine7_next_state <= 3'd5;
+ end
+ end
+ end
+ 2'd2: begin
+ if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
+ litedramcore_bankmachine7_next_state <= 3'd5;
+ end
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine7_trccon_ready) begin
+ if (litedramcore_bankmachine7_cmd_ready) begin
+ litedramcore_bankmachine7_next_state <= 3'd6;
+ end
+ end
+ end
+ 3'd4: begin
+ if ((~litedramcore_bankmachine7_refresh_req)) begin
+ litedramcore_bankmachine7_next_state <= 1'd0;
+ end
+ end
+ 3'd5: begin
+ litedramcore_bankmachine7_next_state <= 2'd3;
+ end
+ 3'd6: begin
+ litedramcore_bankmachine7_next_state <= 1'd0;
+ end
+ default: begin
+ if (litedramcore_bankmachine7_refresh_req) begin
+ litedramcore_bankmachine7_next_state <= 3'd4;
+ end else begin
+ if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin
+ if (litedramcore_bankmachine7_row_opened) begin
+ if (litedramcore_bankmachine7_row_hit) begin
+ if ((litedramcore_bankmachine7_cmd_ready & litedramcore_bankmachine7_auto_precharge)) begin
+ litedramcore_bankmachine7_next_state <= 2'd2;
+ end
+ end else begin
+ litedramcore_bankmachine7_next_state <= 1'd1;
+ end
+ end else begin
+ litedramcore_bankmachine7_next_state <= 2'd3;
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine7_row_open <= 1'd0;
+ case (litedramcore_bankmachine7_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine7_trccon_ready) begin
+ litedramcore_bankmachine7_row_open <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine7_row_close <= 1'd0;
+ case (litedramcore_bankmachine7_state)
+ 1'd1: begin
+ litedramcore_bankmachine7_row_close <= 1'd1;
+ end
+ 2'd2: begin
+ litedramcore_bankmachine7_row_close <= 1'd1;
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ litedramcore_bankmachine7_row_close <= 1'd1;
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine7_cmd_payload_cas <= 1'd0;
+ case (litedramcore_bankmachine7_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine7_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin
+ if (litedramcore_bankmachine7_row_opened) begin
+ if (litedramcore_bankmachine7_row_hit) begin
+ litedramcore_bankmachine7_cmd_payload_cas <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine7_cmd_payload_ras <= 1'd0;
+ case (litedramcore_bankmachine7_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
+ litedramcore_bankmachine7_cmd_payload_ras <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine7_trccon_ready) begin
+ litedramcore_bankmachine7_cmd_payload_ras <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine7_cmd_payload_we <= 1'd0;
+ case (litedramcore_bankmachine7_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
+ litedramcore_bankmachine7_cmd_payload_we <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine7_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin
+ if (litedramcore_bankmachine7_row_opened) begin
+ if (litedramcore_bankmachine7_row_hit) begin
+ if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
+ litedramcore_bankmachine7_cmd_payload_we <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd0;
+ case (litedramcore_bankmachine7_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine7_trccon_ready) begin
+ litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd0;
+ case (litedramcore_bankmachine7_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
+ litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine7_trccon_ready) begin
+ litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine7_cmd_payload_is_read <= 1'd0;
+ case (litedramcore_bankmachine7_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine7_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin
+ if (litedramcore_bankmachine7_row_opened) begin
+ if (litedramcore_bankmachine7_row_hit) begin
+ if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
+ end else begin
+ litedramcore_bankmachine7_cmd_payload_is_read <= 1'd1;
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine7_cmd_payload_is_write <= 1'd0;
+ case (litedramcore_bankmachine7_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine7_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin
+ if (litedramcore_bankmachine7_row_opened) begin
+ if (litedramcore_bankmachine7_row_hit) begin
+ if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
+ litedramcore_bankmachine7_cmd_payload_is_write <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine7_req_wdata_ready <= 1'd0;
+ case (litedramcore_bankmachine7_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine7_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin
+ if (litedramcore_bankmachine7_row_opened) begin
+ if (litedramcore_bankmachine7_row_hit) begin
+ if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
+ litedramcore_bankmachine7_req_wdata_ready <= litedramcore_bankmachine7_cmd_ready;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine7_req_rdata_valid <= 1'd0;
+ case (litedramcore_bankmachine7_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine7_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin
+ if (litedramcore_bankmachine7_row_opened) begin
+ if (litedramcore_bankmachine7_row_hit) begin
+ if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
+ end else begin
+ litedramcore_bankmachine7_req_rdata_valid <= litedramcore_bankmachine7_cmd_ready;
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine7_refresh_gnt <= 1'd0;
+ case (litedramcore_bankmachine7_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ if (litedramcore_bankmachine7_twtpcon_ready) begin
+ litedramcore_bankmachine7_refresh_gnt <= 1'd1;
+ end
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine7_cmd_valid <= 1'd0;
+ case (litedramcore_bankmachine7_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
+ litedramcore_bankmachine7_cmd_valid <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine7_trccon_ready) begin
+ litedramcore_bankmachine7_cmd_valid <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine7_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin
+ if (litedramcore_bankmachine7_row_opened) begin
+ if (litedramcore_bankmachine7_row_hit) begin
+ litedramcore_bankmachine7_cmd_valid <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+assign litedramcore_trrdcon_valid = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & ((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we)));
+assign litedramcore_tfawcon_valid = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & ((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we)));
+assign litedramcore_ras_allowed = (litedramcore_trrdcon_ready & litedramcore_tfawcon_ready);
+assign litedramcore_tccdcon_valid = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_cmd_payload_is_write | litedramcore_choose_req_cmd_payload_is_read));
+assign litedramcore_cas_allowed = litedramcore_tccdcon_ready;
+assign litedramcore_twtrcon_valid = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write);
+assign litedramcore_read_available = ((((((((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_payload_is_read) | (litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_payload_is_read)) | (litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_payload_is_read)) | (litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_payload_is_read)) | (litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_payload_is_read)) | (litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_payload_is_read)) | (litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_payload_is_read)) | (litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_payload_is_read));
+assign litedramcore_write_available = ((((((((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_payload_is_write) | (litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_payload_is_write)) | (litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_payload_is_write)) | (litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_payload_is_write)) | (litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_payload_is_write)) | (litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_payload_is_write)) | (litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_payload_is_write)) | (litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_payload_is_write));
+assign litedramcore_max_time0 = (litedramcore_time0 == 1'd0);
+assign litedramcore_max_time1 = (litedramcore_time1 == 1'd0);
+assign litedramcore_bankmachine0_refresh_req = litedramcore_cmd_valid;
+assign litedramcore_bankmachine1_refresh_req = litedramcore_cmd_valid;
+assign litedramcore_bankmachine2_refresh_req = litedramcore_cmd_valid;
+assign litedramcore_bankmachine3_refresh_req = litedramcore_cmd_valid;
+assign litedramcore_bankmachine4_refresh_req = litedramcore_cmd_valid;
+assign litedramcore_bankmachine5_refresh_req = litedramcore_cmd_valid;
+assign litedramcore_bankmachine6_refresh_req = litedramcore_cmd_valid;
+assign litedramcore_bankmachine7_refresh_req = litedramcore_cmd_valid;
+assign litedramcore_go_to_refresh = (((((((litedramcore_bankmachine0_refresh_gnt & litedramcore_bankmachine1_refresh_gnt) & litedramcore_bankmachine2_refresh_gnt) & litedramcore_bankmachine3_refresh_gnt) & litedramcore_bankmachine4_refresh_gnt) & litedramcore_bankmachine5_refresh_gnt) & litedramcore_bankmachine6_refresh_gnt) & litedramcore_bankmachine7_refresh_gnt);
+assign litedramcore_interface_rdata = {litedramcore_dfi_p1_rddata, litedramcore_dfi_p0_rddata};
+assign {litedramcore_dfi_p1_wrdata, litedramcore_dfi_p0_wrdata} = litedramcore_interface_wdata;
+assign {litedramcore_dfi_p1_wrdata, litedramcore_dfi_p0_wrdata} = litedramcore_interface_wdata;
+assign {litedramcore_dfi_p1_wrdata_mask, litedramcore_dfi_p0_wrdata_mask} = (~litedramcore_interface_wdata_we);
+assign {litedramcore_dfi_p1_wrdata_mask, litedramcore_dfi_p0_wrdata_mask} = (~litedramcore_interface_wdata_we);
+always @(*) begin
+ litedramcore_choose_cmd_valids <= 8'd0;
+ litedramcore_choose_cmd_valids[0] <= (litedramcore_bankmachine0_cmd_valid & (((litedramcore_bankmachine0_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine0_cmd_payload_ras & (~litedramcore_bankmachine0_cmd_payload_cas)) & (~litedramcore_bankmachine0_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine0_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine0_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
+ litedramcore_choose_cmd_valids[1] <= (litedramcore_bankmachine1_cmd_valid & (((litedramcore_bankmachine1_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine1_cmd_payload_ras & (~litedramcore_bankmachine1_cmd_payload_cas)) & (~litedramcore_bankmachine1_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine1_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine1_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
+ litedramcore_choose_cmd_valids[2] <= (litedramcore_bankmachine2_cmd_valid & (((litedramcore_bankmachine2_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine2_cmd_payload_ras & (~litedramcore_bankmachine2_cmd_payload_cas)) & (~litedramcore_bankmachine2_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine2_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine2_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
+ litedramcore_choose_cmd_valids[3] <= (litedramcore_bankmachine3_cmd_valid & (((litedramcore_bankmachine3_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine3_cmd_payload_ras & (~litedramcore_bankmachine3_cmd_payload_cas)) & (~litedramcore_bankmachine3_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine3_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine3_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
+ litedramcore_choose_cmd_valids[4] <= (litedramcore_bankmachine4_cmd_valid & (((litedramcore_bankmachine4_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine4_cmd_payload_ras & (~litedramcore_bankmachine4_cmd_payload_cas)) & (~litedramcore_bankmachine4_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine4_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine4_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
+ litedramcore_choose_cmd_valids[5] <= (litedramcore_bankmachine5_cmd_valid & (((litedramcore_bankmachine5_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine5_cmd_payload_ras & (~litedramcore_bankmachine5_cmd_payload_cas)) & (~litedramcore_bankmachine5_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine5_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine5_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
+ litedramcore_choose_cmd_valids[6] <= (litedramcore_bankmachine6_cmd_valid & (((litedramcore_bankmachine6_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine6_cmd_payload_ras & (~litedramcore_bankmachine6_cmd_payload_cas)) & (~litedramcore_bankmachine6_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine6_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine6_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
+ litedramcore_choose_cmd_valids[7] <= (litedramcore_bankmachine7_cmd_valid & (((litedramcore_bankmachine7_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine7_cmd_payload_ras & (~litedramcore_bankmachine7_cmd_payload_cas)) & (~litedramcore_bankmachine7_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine7_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine7_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
+end
+assign litedramcore_choose_cmd_request = litedramcore_choose_cmd_valids;
+assign litedramcore_choose_cmd_cmd_valid = rhs_array_muxed0;
+assign litedramcore_choose_cmd_cmd_payload_a = rhs_array_muxed1;
+assign litedramcore_choose_cmd_cmd_payload_ba = rhs_array_muxed2;
+assign litedramcore_choose_cmd_cmd_payload_is_read = rhs_array_muxed3;
+assign litedramcore_choose_cmd_cmd_payload_is_write = rhs_array_muxed4;
+assign litedramcore_choose_cmd_cmd_payload_is_cmd = rhs_array_muxed5;
+always @(*) begin
+ litedramcore_choose_cmd_cmd_payload_cas <= 1'd0;
+ if (litedramcore_choose_cmd_cmd_valid) begin
+ litedramcore_choose_cmd_cmd_payload_cas <= t_array_muxed0;
+ end
+end
+always @(*) begin
+ litedramcore_choose_cmd_cmd_payload_ras <= 1'd0;
+ if (litedramcore_choose_cmd_cmd_valid) begin
+ litedramcore_choose_cmd_cmd_payload_ras <= t_array_muxed1;
+ end
+end
+always @(*) begin
+ litedramcore_choose_cmd_cmd_payload_we <= 1'd0;
+ if (litedramcore_choose_cmd_cmd_valid) begin
+ litedramcore_choose_cmd_cmd_payload_we <= t_array_muxed2;
+ end
+end
+always @(*) begin
+ litedramcore_bankmachine0_cmd_ready <= 1'd0;
+ if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 1'd0))) begin
+ litedramcore_bankmachine0_cmd_ready <= 1'd1;
+ end
+ if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 1'd0))) begin
+ litedramcore_bankmachine0_cmd_ready <= 1'd1;
+ end
+end
+always @(*) begin
+ litedramcore_bankmachine1_cmd_ready <= 1'd0;
+ if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 1'd1))) begin
+ litedramcore_bankmachine1_cmd_ready <= 1'd1;
+ end
+ if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 1'd1))) begin
+ litedramcore_bankmachine1_cmd_ready <= 1'd1;
+ end
+end
+always @(*) begin
+ litedramcore_bankmachine2_cmd_ready <= 1'd0;
+ if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 2'd2))) begin
+ litedramcore_bankmachine2_cmd_ready <= 1'd1;
+ end
+ if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 2'd2))) begin
+ litedramcore_bankmachine2_cmd_ready <= 1'd1;
+ end
+end
+always @(*) begin
+ litedramcore_bankmachine3_cmd_ready <= 1'd0;
+ if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 2'd3))) begin
+ litedramcore_bankmachine3_cmd_ready <= 1'd1;
+ end
+ if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 2'd3))) begin
+ litedramcore_bankmachine3_cmd_ready <= 1'd1;
+ end
+end
+always @(*) begin
+ litedramcore_bankmachine4_cmd_ready <= 1'd0;
+ if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd4))) begin
+ litedramcore_bankmachine4_cmd_ready <= 1'd1;
+ end
+ if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd4))) begin
+ litedramcore_bankmachine4_cmd_ready <= 1'd1;
+ end
+end
+always @(*) begin
+ litedramcore_bankmachine5_cmd_ready <= 1'd0;
+ if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd5))) begin
+ litedramcore_bankmachine5_cmd_ready <= 1'd1;
+ end
+ if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd5))) begin
+ litedramcore_bankmachine5_cmd_ready <= 1'd1;
+ end
+end
+always @(*) begin
+ litedramcore_bankmachine6_cmd_ready <= 1'd0;
+ if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd6))) begin
+ litedramcore_bankmachine6_cmd_ready <= 1'd1;
+ end
+ if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd6))) begin
+ litedramcore_bankmachine6_cmd_ready <= 1'd1;
+ end
+end
+always @(*) begin
+ litedramcore_bankmachine7_cmd_ready <= 1'd0;
+ if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd7))) begin
+ litedramcore_bankmachine7_cmd_ready <= 1'd1;
+ end
+ if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd7))) begin
+ litedramcore_bankmachine7_cmd_ready <= 1'd1;
+ end
+end
+assign litedramcore_choose_cmd_ce = (litedramcore_choose_cmd_cmd_ready | (~litedramcore_choose_cmd_cmd_valid));
+always @(*) begin
+ litedramcore_choose_req_valids <= 8'd0;
+ litedramcore_choose_req_valids[0] <= (litedramcore_bankmachine0_cmd_valid & (((litedramcore_bankmachine0_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine0_cmd_payload_ras & (~litedramcore_bankmachine0_cmd_payload_cas)) & (~litedramcore_bankmachine0_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine0_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine0_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
+ litedramcore_choose_req_valids[1] <= (litedramcore_bankmachine1_cmd_valid & (((litedramcore_bankmachine1_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine1_cmd_payload_ras & (~litedramcore_bankmachine1_cmd_payload_cas)) & (~litedramcore_bankmachine1_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine1_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine1_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
+ litedramcore_choose_req_valids[2] <= (litedramcore_bankmachine2_cmd_valid & (((litedramcore_bankmachine2_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine2_cmd_payload_ras & (~litedramcore_bankmachine2_cmd_payload_cas)) & (~litedramcore_bankmachine2_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine2_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine2_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
+ litedramcore_choose_req_valids[3] <= (litedramcore_bankmachine3_cmd_valid & (((litedramcore_bankmachine3_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine3_cmd_payload_ras & (~litedramcore_bankmachine3_cmd_payload_cas)) & (~litedramcore_bankmachine3_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine3_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine3_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
+ litedramcore_choose_req_valids[4] <= (litedramcore_bankmachine4_cmd_valid & (((litedramcore_bankmachine4_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine4_cmd_payload_ras & (~litedramcore_bankmachine4_cmd_payload_cas)) & (~litedramcore_bankmachine4_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine4_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine4_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
+ litedramcore_choose_req_valids[5] <= (litedramcore_bankmachine5_cmd_valid & (((litedramcore_bankmachine5_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine5_cmd_payload_ras & (~litedramcore_bankmachine5_cmd_payload_cas)) & (~litedramcore_bankmachine5_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine5_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine5_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
+ litedramcore_choose_req_valids[6] <= (litedramcore_bankmachine6_cmd_valid & (((litedramcore_bankmachine6_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine6_cmd_payload_ras & (~litedramcore_bankmachine6_cmd_payload_cas)) & (~litedramcore_bankmachine6_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine6_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine6_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
+ litedramcore_choose_req_valids[7] <= (litedramcore_bankmachine7_cmd_valid & (((litedramcore_bankmachine7_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine7_cmd_payload_ras & (~litedramcore_bankmachine7_cmd_payload_cas)) & (~litedramcore_bankmachine7_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine7_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine7_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
+end
+assign litedramcore_choose_req_request = litedramcore_choose_req_valids;
+assign litedramcore_choose_req_cmd_valid = rhs_array_muxed6;
+assign litedramcore_choose_req_cmd_payload_a = rhs_array_muxed7;
+assign litedramcore_choose_req_cmd_payload_ba = rhs_array_muxed8;
+assign litedramcore_choose_req_cmd_payload_is_read = rhs_array_muxed9;
+assign litedramcore_choose_req_cmd_payload_is_write = rhs_array_muxed10;
+assign litedramcore_choose_req_cmd_payload_is_cmd = rhs_array_muxed11;
+always @(*) begin
+ litedramcore_choose_req_cmd_payload_cas <= 1'd0;
+ if (litedramcore_choose_req_cmd_valid) begin
+ litedramcore_choose_req_cmd_payload_cas <= t_array_muxed3;
+ end
+end
+always @(*) begin
+ litedramcore_choose_req_cmd_payload_ras <= 1'd0;
+ if (litedramcore_choose_req_cmd_valid) begin
+ litedramcore_choose_req_cmd_payload_ras <= t_array_muxed4;
+ end
+end
+always @(*) begin
+ litedramcore_choose_req_cmd_payload_we <= 1'd0;
+ if (litedramcore_choose_req_cmd_valid) begin
+ litedramcore_choose_req_cmd_payload_we <= t_array_muxed5;
+ end
+end
+assign litedramcore_choose_req_ce = (litedramcore_choose_req_cmd_ready | (~litedramcore_choose_req_cmd_valid));
+assign litedramcore_dfi_p0_reset_n = 1'd1;
+assign litedramcore_dfi_p0_cke = {1{litedramcore_steerer0}};
+assign litedramcore_dfi_p0_odt = {1{litedramcore_steerer1}};
+assign litedramcore_dfi_p1_reset_n = 1'd1;
+assign litedramcore_dfi_p1_cke = {1{litedramcore_steerer2}};
+assign litedramcore_dfi_p1_odt = {1{litedramcore_steerer3}};
+assign litedramcore_tfawcon_count = ((litedramcore_tfawcon_window[0] + litedramcore_tfawcon_window[1]) + litedramcore_tfawcon_window[2]);
+always @(*) begin
+ litedramcore_multiplexer_next_state <= 4'd0;
+ litedramcore_multiplexer_next_state <= litedramcore_multiplexer_state;
+ case (litedramcore_multiplexer_state)
+ 1'd1: begin
+ if (litedramcore_read_available) begin
+ if (((~litedramcore_write_available) | litedramcore_max_time1)) begin
+ litedramcore_multiplexer_next_state <= 2'd3;
+ end
+ end
+ if (litedramcore_go_to_refresh) begin
+ litedramcore_multiplexer_next_state <= 2'd2;
+ end
+ end
+ 2'd2: begin
+ if (litedramcore_cmd_last) begin
+ litedramcore_multiplexer_next_state <= 1'd0;
+ end
+ end
+ 2'd3: begin
+ if (litedramcore_twtrcon_ready) begin
+ litedramcore_multiplexer_next_state <= 1'd0;
+ end
+ end
+ 3'd4: begin
+ litedramcore_multiplexer_next_state <= 3'd5;
+ end
+ 3'd5: begin
+ litedramcore_multiplexer_next_state <= 3'd6;
+ end
+ 3'd6: begin
+ litedramcore_multiplexer_next_state <= 3'd7;
+ end
+ 3'd7: begin
+ litedramcore_multiplexer_next_state <= 4'd8;
+ end
+ 4'd8: begin
+ litedramcore_multiplexer_next_state <= 4'd9;
+ end
+ 4'd9: begin
+ litedramcore_multiplexer_next_state <= 4'd10;
+ end
+ 4'd10: begin
+ litedramcore_multiplexer_next_state <= 4'd11;
+ end
+ 4'd11: begin
+ litedramcore_multiplexer_next_state <= 4'd12;
+ end
+ 4'd12: begin
+ litedramcore_multiplexer_next_state <= 4'd13;
+ end
+ 4'd13: begin
+ litedramcore_multiplexer_next_state <= 4'd14;
+ end
+ 4'd14: begin
+ litedramcore_multiplexer_next_state <= 4'd15;
+ end
+ 4'd15: begin
+ litedramcore_multiplexer_next_state <= 1'd1;
+ end
+ default: begin
+ if (litedramcore_write_available) begin
+ if (((~litedramcore_read_available) | litedramcore_max_time0)) begin
+ litedramcore_multiplexer_next_state <= 3'd4;
+ end
+ end
+ if (litedramcore_go_to_refresh) begin
+ litedramcore_multiplexer_next_state <= 2'd2;
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_choose_req_cmd_ready <= 1'd0;
+ case (litedramcore_multiplexer_state)
+ 1'd1: begin
+ if (1'd0) begin
+ litedramcore_choose_req_cmd_ready <= (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed));
+ end else begin
+ litedramcore_choose_req_cmd_ready <= litedramcore_cas_allowed;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ 4'd9: begin
+ end
+ 4'd10: begin
+ end
+ 4'd11: begin
+ end
+ 4'd12: begin
+ end
+ 4'd13: begin
+ end
+ 4'd14: begin
+ end
+ 4'd15: begin
+ end
+ default: begin
+ if (1'd0) begin
+ litedramcore_choose_req_cmd_ready <= (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed));
+ end else begin
+ litedramcore_choose_req_cmd_ready <= litedramcore_cas_allowed;
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_en1 <= 1'd0;
+ case (litedramcore_multiplexer_state)
+ 1'd1: begin
+ litedramcore_en1 <= 1'd1;
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ 4'd9: begin
+ end
+ 4'd10: begin
+ end
+ 4'd11: begin
+ end
+ 4'd12: begin
+ end
+ 4'd13: begin
+ end
+ 4'd14: begin
+ end
+ 4'd15: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_steerer_sel0 <= 2'd0;
+ case (litedramcore_multiplexer_state)
+ 1'd1: begin
+ litedramcore_steerer_sel0 <= 1'd0;
+ if (1'd0) begin
+ litedramcore_steerer_sel0 <= 2'd2;
+ end
+ if (1'd1) begin
+ litedramcore_steerer_sel0 <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ litedramcore_steerer_sel0 <= 2'd3;
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ 4'd9: begin
+ end
+ 4'd10: begin
+ end
+ 4'd11: begin
+ end
+ 4'd12: begin
+ end
+ 4'd13: begin
+ end
+ 4'd14: begin
+ end
+ 4'd15: begin
+ end
+ default: begin
+ litedramcore_steerer_sel0 <= 1'd0;
+ if (1'd1) begin
+ litedramcore_steerer_sel0 <= 2'd2;
+ end
+ if (1'd0) begin
+ litedramcore_steerer_sel0 <= 1'd1;
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_steerer_sel1 <= 2'd0;
+ case (litedramcore_multiplexer_state)
+ 1'd1: begin
+ litedramcore_steerer_sel1 <= 1'd0;
+ if (1'd1) begin
+ litedramcore_steerer_sel1 <= 2'd2;
+ end
+ if (1'd0) begin
+ litedramcore_steerer_sel1 <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ 4'd9: begin
+ end
+ 4'd10: begin
+ end
+ 4'd11: begin
+ end
+ 4'd12: begin
+ end
+ 4'd13: begin
+ end
+ 4'd14: begin
+ end
+ 4'd15: begin
+ end
+ default: begin
+ litedramcore_steerer_sel1 <= 1'd0;
+ if (1'd0) begin
+ litedramcore_steerer_sel1 <= 2'd2;
+ end
+ if (1'd1) begin
+ litedramcore_steerer_sel1 <= 1'd1;
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_choose_cmd_want_activates <= 1'd0;
+ case (litedramcore_multiplexer_state)
+ 1'd1: begin
+ if (1'd0) begin
+ end else begin
+ litedramcore_choose_cmd_want_activates <= litedramcore_ras_allowed;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ 4'd9: begin
+ end
+ 4'd10: begin
+ end
+ 4'd11: begin
+ end
+ 4'd12: begin
+ end
+ 4'd13: begin
+ end
+ 4'd14: begin
+ end
+ 4'd15: begin
+ end
+ default: begin
+ if (1'd0) begin
+ end else begin
+ litedramcore_choose_cmd_want_activates <= litedramcore_ras_allowed;
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_cmd_ready <= 1'd0;
+ case (litedramcore_multiplexer_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ litedramcore_cmd_ready <= 1'd1;
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ 4'd9: begin
+ end
+ 4'd10: begin
+ end
+ 4'd11: begin
+ end
+ 4'd12: begin
+ end
+ 4'd13: begin
+ end
+ 4'd14: begin
+ end
+ 4'd15: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_choose_cmd_cmd_ready <= 1'd0;
+ case (litedramcore_multiplexer_state)
+ 1'd1: begin
+ if (1'd0) begin
+ end else begin
+ litedramcore_choose_cmd_cmd_ready <= ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed);
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ 4'd9: begin
+ end
+ 4'd10: begin
+ end
+ 4'd11: begin
+ end
+ 4'd12: begin
+ end
+ 4'd13: begin
+ end
+ 4'd14: begin
+ end
+ 4'd15: begin
+ end
+ default: begin
+ if (1'd0) begin
+ end else begin
+ litedramcore_choose_cmd_cmd_ready <= ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed);
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_choose_req_want_reads <= 1'd0;
+ case (litedramcore_multiplexer_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ 4'd9: begin
+ end
+ 4'd10: begin
+ end
+ 4'd11: begin
+ end
+ 4'd12: begin
+ end
+ 4'd13: begin
+ end
+ 4'd14: begin
+ end
+ 4'd15: begin
+ end
+ default: begin
+ litedramcore_choose_req_want_reads <= 1'd1;
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_choose_req_want_writes <= 1'd0;
+ case (litedramcore_multiplexer_state)
+ 1'd1: begin
+ litedramcore_choose_req_want_writes <= 1'd1;
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ 4'd9: begin
+ end
+ 4'd10: begin
+ end
+ 4'd11: begin
+ end
+ 4'd12: begin
+ end
+ 4'd13: begin
+ end
+ 4'd14: begin
+ end
+ 4'd15: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_en0 <= 1'd0;
+ case (litedramcore_multiplexer_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ 4'd9: begin
+ end
+ 4'd10: begin
+ end
+ 4'd11: begin
+ end
+ 4'd12: begin
+ end
+ 4'd13: begin
+ end
+ 4'd14: begin
+ end
+ 4'd15: begin
+ end
+ default: begin
+ litedramcore_en0 <= 1'd1;
+ end
+ endcase
+end
+assign litedramcore_roundrobin0_request = {(((user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((litedramcore_locked0 | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)};
+assign litedramcore_roundrobin0_ce = ((~litedramcore_interface_bank0_valid) & (~litedramcore_interface_bank0_lock));
+assign litedramcore_interface_bank0_addr = rhs_array_muxed12;
+assign litedramcore_interface_bank0_we = rhs_array_muxed13;
+assign litedramcore_interface_bank0_valid = rhs_array_muxed14;
+assign litedramcore_roundrobin1_request = {(((user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((litedramcore_locked1 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)};
+assign litedramcore_roundrobin1_ce = ((~litedramcore_interface_bank1_valid) & (~litedramcore_interface_bank1_lock));
+assign litedramcore_interface_bank1_addr = rhs_array_muxed15;
+assign litedramcore_interface_bank1_we = rhs_array_muxed16;
+assign litedramcore_interface_bank1_valid = rhs_array_muxed17;
+assign litedramcore_roundrobin2_request = {(((user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((litedramcore_locked2 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)};
+assign litedramcore_roundrobin2_ce = ((~litedramcore_interface_bank2_valid) & (~litedramcore_interface_bank2_lock));
+assign litedramcore_interface_bank2_addr = rhs_array_muxed18;
+assign litedramcore_interface_bank2_we = rhs_array_muxed19;
+assign litedramcore_interface_bank2_valid = rhs_array_muxed20;
+assign litedramcore_roundrobin3_request = {(((user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((litedramcore_locked3 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)};
+assign litedramcore_roundrobin3_ce = ((~litedramcore_interface_bank3_valid) & (~litedramcore_interface_bank3_lock));
+assign litedramcore_interface_bank3_addr = rhs_array_muxed21;
+assign litedramcore_interface_bank3_we = rhs_array_muxed22;
+assign litedramcore_interface_bank3_valid = rhs_array_muxed23;
+assign litedramcore_roundrobin4_request = {(((user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((litedramcore_locked4 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)};
+assign litedramcore_roundrobin4_ce = ((~litedramcore_interface_bank4_valid) & (~litedramcore_interface_bank4_lock));
+assign litedramcore_interface_bank4_addr = rhs_array_muxed24;
+assign litedramcore_interface_bank4_we = rhs_array_muxed25;
+assign litedramcore_interface_bank4_valid = rhs_array_muxed26;
+assign litedramcore_roundrobin5_request = {(((user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((litedramcore_locked5 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)};
+assign litedramcore_roundrobin5_ce = ((~litedramcore_interface_bank5_valid) & (~litedramcore_interface_bank5_lock));
+assign litedramcore_interface_bank5_addr = rhs_array_muxed27;
+assign litedramcore_interface_bank5_we = rhs_array_muxed28;
+assign litedramcore_interface_bank5_valid = rhs_array_muxed29;
+assign litedramcore_roundrobin6_request = {(((user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((litedramcore_locked6 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)};
+assign litedramcore_roundrobin6_ce = ((~litedramcore_interface_bank6_valid) & (~litedramcore_interface_bank6_lock));
+assign litedramcore_interface_bank6_addr = rhs_array_muxed30;
+assign litedramcore_interface_bank6_we = rhs_array_muxed31;
+assign litedramcore_interface_bank6_valid = rhs_array_muxed32;
+assign litedramcore_roundrobin7_request = {(((user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((litedramcore_locked7 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))))) & user_port_cmd_valid)};
+assign litedramcore_roundrobin7_ce = ((~litedramcore_interface_bank7_valid) & (~litedramcore_interface_bank7_lock));
+assign litedramcore_interface_bank7_addr = rhs_array_muxed33;
+assign litedramcore_interface_bank7_we = rhs_array_muxed34;
+assign litedramcore_interface_bank7_valid = rhs_array_muxed35;
+assign user_port_cmd_ready = ((((((((1'd0 | (((litedramcore_roundrobin0_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((litedramcore_locked0 | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank0_ready)) | (((litedramcore_roundrobin1_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((litedramcore_locked1 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank1_ready)) | (((litedramcore_roundrobin2_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((litedramcore_locked2 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank2_ready)) | (((litedramcore_roundrobin3_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((litedramcore_locked3 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank3_ready)) | (((litedramcore_roundrobin4_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((litedramcore_locked4 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank4_ready)) | (((litedramcore_roundrobin5_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((litedramcore_locked5 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank5_ready)) | (((litedramcore_roundrobin6_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((litedramcore_locked6 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank6_ready)) | (((litedramcore_roundrobin7_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((litedramcore_locked7 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0)))))) & litedramcore_interface_bank7_ready));
+assign user_port_wdata_ready = litedramcore_new_master_wdata_ready3;
+assign user_port_rdata_valid = litedramcore_new_master_rdata_valid13;
+always @(*) begin
+ litedramcore_interface_wdata <= 256'd0;
+ case ({litedramcore_new_master_wdata_ready3})
+ 1'd1: begin
+ litedramcore_interface_wdata <= user_port_wdata_payload_data;
+ end
+ default: begin
+ litedramcore_interface_wdata <= 1'd0;
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_interface_wdata_we <= 32'd0;
+ case ({litedramcore_new_master_wdata_ready3})
+ 1'd1: begin
+ litedramcore_interface_wdata_we <= user_port_wdata_payload_we;
+ end
+ default: begin
+ litedramcore_interface_wdata_we <= 1'd0;
+ end
+ endcase
+end
+assign user_port_rdata_payload_data = litedramcore_interface_rdata;
+assign litedramcore_roundrobin0_grant = 1'd0;
+assign litedramcore_roundrobin1_grant = 1'd0;
+assign litedramcore_roundrobin2_grant = 1'd0;
+assign litedramcore_roundrobin3_grant = 1'd0;
+assign litedramcore_roundrobin4_grant = 1'd0;
+assign litedramcore_roundrobin5_grant = 1'd0;
+assign litedramcore_roundrobin6_grant = 1'd0;
+assign litedramcore_roundrobin7_grant = 1'd0;
+always @(*) begin
+ next_state <= 2'd0;
+ next_state <= state;
+ case (state)
+ 1'd1: begin
+ next_state <= 2'd2;
+ end
+ 2'd2: begin
+ next_state <= 1'd0;
+ end
+ default: begin
+ if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
+ next_state <= 1'd1;
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_dat_w_next_value0 <= 32'd0;
+ case (state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ default: begin
+ litedramcore_dat_w_next_value0 <= litedramcore_wishbone_dat_w;
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_wishbone_dat_r <= 32'd0;
+ case (state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ litedramcore_wishbone_dat_r <= litedramcore_dat_r;
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_dat_w_next_value_ce0 <= 1'd0;
+ case (state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ default: begin
+ litedramcore_dat_w_next_value_ce0 <= 1'd1;
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_adr_next_value1 <= 14'd0;
+ case (state)
+ 1'd1: begin
+ litedramcore_adr_next_value1 <= 1'd0;
+ end
+ 2'd2: begin
+ end
+ default: begin
+ if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
+ litedramcore_adr_next_value1 <= litedramcore_wishbone_adr;
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_adr_next_value_ce1 <= 1'd0;
+ case (state)
+ 1'd1: begin
+ litedramcore_adr_next_value_ce1 <= 1'd1;
+ end
+ 2'd2: begin
+ end
+ default: begin
+ if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
+ litedramcore_adr_next_value_ce1 <= 1'd1;
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_wishbone_ack <= 1'd0;
+ case (state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ litedramcore_wishbone_ack <= 1'd1;
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_we_next_value2 <= 1'd0;
+ case (state)
+ 1'd1: begin
+ litedramcore_we_next_value2 <= 1'd0;
+ end
+ 2'd2: begin
+ end
+ default: begin
+ if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
+ litedramcore_we_next_value2 <= (litedramcore_wishbone_we & (litedramcore_wishbone_sel != 1'd0));
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_we_next_value_ce2 <= 1'd0;
+ case (state)
+ 1'd1: begin
+ litedramcore_we_next_value_ce2 <= 1'd1;
+ end
+ 2'd2: begin
+ end
+ default: begin
+ if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
+ litedramcore_we_next_value_ce2 <= 1'd1;
+ end
+ end
+ endcase
+end
+assign litedramcore_wishbone_adr = wb_bus_adr;
+assign litedramcore_wishbone_dat_w = wb_bus_dat_w;
+assign wb_bus_dat_r = litedramcore_wishbone_dat_r;
+assign litedramcore_wishbone_sel = wb_bus_sel;
+assign litedramcore_wishbone_cyc = wb_bus_cyc;
+assign litedramcore_wishbone_stb = wb_bus_stb;
+assign wb_bus_ack = litedramcore_wishbone_ack;
+assign litedramcore_wishbone_we = wb_bus_we;
+assign litedramcore_wishbone_cti = wb_bus_cti;
+assign litedramcore_wishbone_bte = wb_bus_bte;
+assign wb_bus_err = litedramcore_wishbone_err;
+assign csrbank0_sel = (interface0_bank_bus_adr[13:9] == 1'd0);
+assign csrbank0_init_done0_r = interface0_bank_bus_dat_w[0];
+always @(*) begin
+ csrbank0_init_done0_we <= 1'd0;
+ if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd0))) begin
+ csrbank0_init_done0_we <= (~interface0_bank_bus_we);
+ end
+end
+always @(*) begin
+ csrbank0_init_done0_re <= 1'd0;
+ if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd0))) begin
+ csrbank0_init_done0_re <= interface0_bank_bus_we;
+ end
+end
+assign csrbank0_init_error0_r = interface0_bank_bus_dat_w[0];
+always @(*) begin
+ csrbank0_init_error0_re <= 1'd0;
+ if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd1))) begin
+ csrbank0_init_error0_re <= interface0_bank_bus_we;
+ end
+end
+always @(*) begin
+ csrbank0_init_error0_we <= 1'd0;
+ if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd1))) begin
+ csrbank0_init_error0_we <= (~interface0_bank_bus_we);
+ end
+end
+assign csrbank0_init_done0_w = init_done_storage;
+assign csrbank0_init_error0_w = init_error_storage;
+assign csrbank1_sel = (interface1_bank_bus_adr[13:9] == 1'd1);
+assign csrbank1_dly_sel0_r = interface1_bank_bus_dat_w[3:0];
+always @(*) begin
+ csrbank1_dly_sel0_re <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd0))) begin
+ csrbank1_dly_sel0_re <= interface1_bank_bus_we;
+ end
+end
+always @(*) begin
+ csrbank1_dly_sel0_we <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd0))) begin
+ csrbank1_dly_sel0_we <= (~interface1_bank_bus_we);
+ end
+end
+assign ddrphy_rdly_dq_rst_r = interface1_bank_bus_dat_w[0];
+always @(*) begin
+ ddrphy_rdly_dq_rst_we <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd1))) begin
+ ddrphy_rdly_dq_rst_we <= (~interface1_bank_bus_we);
+ end
+end
+always @(*) begin
+ ddrphy_rdly_dq_rst_re <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd1))) begin
+ ddrphy_rdly_dq_rst_re <= interface1_bank_bus_we;
+ end
+end
+assign ddrphy_rdly_dq_inc_r = interface1_bank_bus_dat_w[0];
+always @(*) begin
+ ddrphy_rdly_dq_inc_we <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd2))) begin
+ ddrphy_rdly_dq_inc_we <= (~interface1_bank_bus_we);
+ end
+end
+always @(*) begin
+ ddrphy_rdly_dq_inc_re <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd2))) begin
+ ddrphy_rdly_dq_inc_re <= interface1_bank_bus_we;
+ end
+end
+assign ddrphy_rdly_dq_bitslip_rst_r = interface1_bank_bus_dat_w[0];
+always @(*) begin
+ ddrphy_rdly_dq_bitslip_rst_we <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd3))) begin
+ ddrphy_rdly_dq_bitslip_rst_we <= (~interface1_bank_bus_we);
+ end
+end
+always @(*) begin
+ ddrphy_rdly_dq_bitslip_rst_re <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd3))) begin
+ ddrphy_rdly_dq_bitslip_rst_re <= interface1_bank_bus_we;
+ end
+end
+assign ddrphy_rdly_dq_bitslip_r = interface1_bank_bus_dat_w[0];
+always @(*) begin
+ ddrphy_rdly_dq_bitslip_re <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd4))) begin
+ ddrphy_rdly_dq_bitslip_re <= interface1_bank_bus_we;
+ end
+end
+always @(*) begin
+ ddrphy_rdly_dq_bitslip_we <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd4))) begin
+ ddrphy_rdly_dq_bitslip_we <= (~interface1_bank_bus_we);
+ end
+end
+assign ddrphy_burstdet_clr_r = interface1_bank_bus_dat_w[0];
+always @(*) begin
+ ddrphy_burstdet_clr_re <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd5))) begin
+ ddrphy_burstdet_clr_re <= interface1_bank_bus_we;
+ end
+end
+always @(*) begin
+ ddrphy_burstdet_clr_we <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd5))) begin
+ ddrphy_burstdet_clr_we <= (~interface1_bank_bus_we);
+ end
+end
+assign csrbank1_burstdet_seen_r = interface1_bank_bus_dat_w[3:0];
+always @(*) begin
+ csrbank1_burstdet_seen_re <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd6))) begin
+ csrbank1_burstdet_seen_re <= interface1_bank_bus_we;
+ end
+end
+always @(*) begin
+ csrbank1_burstdet_seen_we <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd6))) begin
+ csrbank1_burstdet_seen_we <= (~interface1_bank_bus_we);
+ end
+end
+assign csrbank1_dly_sel0_w = ddrphy_dly_sel_storage[3:0];
+assign csrbank1_burstdet_seen_w = ddrphy_burstdet_seen_status[3:0];
+assign ddrphy_burstdet_seen_we = csrbank1_burstdet_seen_we;
+assign csrbank2_sel = (interface2_bank_bus_adr[13:9] == 2'd2);
+assign csrbank2_dfii_control0_r = interface2_bank_bus_dat_w[3:0];
+always @(*) begin
+ csrbank2_dfii_control0_we <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd0))) begin
+ csrbank2_dfii_control0_we <= (~interface2_bank_bus_we);
+ end
+end
+always @(*) begin
+ csrbank2_dfii_control0_re <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd0))) begin
+ csrbank2_dfii_control0_re <= interface2_bank_bus_we;
+ end
+end
+assign csrbank2_dfii_pi0_command0_r = interface2_bank_bus_dat_w[5:0];
+always @(*) begin
+ csrbank2_dfii_pi0_command0_re <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd1))) begin
+ csrbank2_dfii_pi0_command0_re <= interface2_bank_bus_we;
+ end
+end
+always @(*) begin
+ csrbank2_dfii_pi0_command0_we <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd1))) begin
+ csrbank2_dfii_pi0_command0_we <= (~interface2_bank_bus_we);
+ end
+end
+assign litedramcore_phaseinjector0_command_issue_r = interface2_bank_bus_dat_w[0];
+always @(*) begin
+ litedramcore_phaseinjector0_command_issue_re <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd2))) begin
+ litedramcore_phaseinjector0_command_issue_re <= interface2_bank_bus_we;
+ end
+end
+always @(*) begin
+ litedramcore_phaseinjector0_command_issue_we <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd2))) begin
+ litedramcore_phaseinjector0_command_issue_we <= (~interface2_bank_bus_we);
+ end
+end
+assign csrbank2_dfii_pi0_address0_r = interface2_bank_bus_dat_w[14:0];
+always @(*) begin
+ csrbank2_dfii_pi0_address0_re <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd3))) begin
+ csrbank2_dfii_pi0_address0_re <= interface2_bank_bus_we;
+ end
+end
+always @(*) begin
+ csrbank2_dfii_pi0_address0_we <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd3))) begin
+ csrbank2_dfii_pi0_address0_we <= (~interface2_bank_bus_we);
+ end
+end
+assign csrbank2_dfii_pi0_baddress0_r = interface2_bank_bus_dat_w[2:0];
+always @(*) begin
+ csrbank2_dfii_pi0_baddress0_we <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd4))) begin
+ csrbank2_dfii_pi0_baddress0_we <= (~interface2_bank_bus_we);
+ end
+end
+always @(*) begin
+ csrbank2_dfii_pi0_baddress0_re <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd4))) begin
+ csrbank2_dfii_pi0_baddress0_re <= interface2_bank_bus_we;
+ end
+end
+assign csrbank2_dfii_pi0_wrdata3_r = interface2_bank_bus_dat_w[31:0];
+always @(*) begin
+ csrbank2_dfii_pi0_wrdata3_re <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd5))) begin
+ csrbank2_dfii_pi0_wrdata3_re <= interface2_bank_bus_we;
+ end
+end
+always @(*) begin
+ csrbank2_dfii_pi0_wrdata3_we <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd5))) begin
+ csrbank2_dfii_pi0_wrdata3_we <= (~interface2_bank_bus_we);
+ end
+end
+assign csrbank2_dfii_pi0_wrdata2_r = interface2_bank_bus_dat_w[31:0];
+always @(*) begin
+ csrbank2_dfii_pi0_wrdata2_we <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd6))) begin
+ csrbank2_dfii_pi0_wrdata2_we <= (~interface2_bank_bus_we);
+ end
+end
+always @(*) begin
+ csrbank2_dfii_pi0_wrdata2_re <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd6))) begin
+ csrbank2_dfii_pi0_wrdata2_re <= interface2_bank_bus_we;
+ end
+end
+assign csrbank2_dfii_pi0_wrdata1_r = interface2_bank_bus_dat_w[31:0];
+always @(*) begin
+ csrbank2_dfii_pi0_wrdata1_we <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd7))) begin
+ csrbank2_dfii_pi0_wrdata1_we <= (~interface2_bank_bus_we);
+ end
+end
+always @(*) begin
+ csrbank2_dfii_pi0_wrdata1_re <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd7))) begin
+ csrbank2_dfii_pi0_wrdata1_re <= interface2_bank_bus_we;
+ end
+end
+assign csrbank2_dfii_pi0_wrdata0_r = interface2_bank_bus_dat_w[31:0];
+always @(*) begin
+ csrbank2_dfii_pi0_wrdata0_re <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd8))) begin
+ csrbank2_dfii_pi0_wrdata0_re <= interface2_bank_bus_we;
+ end
+end
+always @(*) begin
+ csrbank2_dfii_pi0_wrdata0_we <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd8))) begin
+ csrbank2_dfii_pi0_wrdata0_we <= (~interface2_bank_bus_we);
+ end
+end
+assign csrbank2_dfii_pi0_rddata3_r = interface2_bank_bus_dat_w[31:0];
+always @(*) begin
+ csrbank2_dfii_pi0_rddata3_we <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd9))) begin
+ csrbank2_dfii_pi0_rddata3_we <= (~interface2_bank_bus_we);
+ end
+end
+always @(*) begin
+ csrbank2_dfii_pi0_rddata3_re <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd9))) begin
+ csrbank2_dfii_pi0_rddata3_re <= interface2_bank_bus_we;
+ end
+end
+assign csrbank2_dfii_pi0_rddata2_r = interface2_bank_bus_dat_w[31:0];
+always @(*) begin
+ csrbank2_dfii_pi0_rddata2_we <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd10))) begin
+ csrbank2_dfii_pi0_rddata2_we <= (~interface2_bank_bus_we);
+ end
+end
+always @(*) begin
+ csrbank2_dfii_pi0_rddata2_re <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd10))) begin
+ csrbank2_dfii_pi0_rddata2_re <= interface2_bank_bus_we;
+ end
+end
+assign csrbank2_dfii_pi0_rddata1_r = interface2_bank_bus_dat_w[31:0];
+always @(*) begin
+ csrbank2_dfii_pi0_rddata1_re <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd11))) begin
+ csrbank2_dfii_pi0_rddata1_re <= interface2_bank_bus_we;
+ end
+end
+always @(*) begin
+ csrbank2_dfii_pi0_rddata1_we <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd11))) begin
+ csrbank2_dfii_pi0_rddata1_we <= (~interface2_bank_bus_we);
+ end
+end
+assign csrbank2_dfii_pi0_rddata0_r = interface2_bank_bus_dat_w[31:0];
+always @(*) begin
+ csrbank2_dfii_pi0_rddata0_re <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd12))) begin
+ csrbank2_dfii_pi0_rddata0_re <= interface2_bank_bus_we;
+ end
+end
+always @(*) begin
+ csrbank2_dfii_pi0_rddata0_we <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd12))) begin
+ csrbank2_dfii_pi0_rddata0_we <= (~interface2_bank_bus_we);
+ end
+end
+assign csrbank2_dfii_pi1_command0_r = interface2_bank_bus_dat_w[5:0];
+always @(*) begin
+ csrbank2_dfii_pi1_command0_we <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd13))) begin
+ csrbank2_dfii_pi1_command0_we <= (~interface2_bank_bus_we);
+ end
+end
+always @(*) begin
+ csrbank2_dfii_pi1_command0_re <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd13))) begin
+ csrbank2_dfii_pi1_command0_re <= interface2_bank_bus_we;
+ end
+end
+assign litedramcore_phaseinjector1_command_issue_r = interface2_bank_bus_dat_w[0];
+always @(*) begin
+ litedramcore_phaseinjector1_command_issue_we <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd14))) begin
+ litedramcore_phaseinjector1_command_issue_we <= (~interface2_bank_bus_we);
+ end
+end
+always @(*) begin
+ litedramcore_phaseinjector1_command_issue_re <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd14))) begin
+ litedramcore_phaseinjector1_command_issue_re <= interface2_bank_bus_we;
+ end
+end
+assign csrbank2_dfii_pi1_address0_r = interface2_bank_bus_dat_w[14:0];
+always @(*) begin
+ csrbank2_dfii_pi1_address0_re <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd15))) begin
+ csrbank2_dfii_pi1_address0_re <= interface2_bank_bus_we;
+ end
+end
+always @(*) begin
+ csrbank2_dfii_pi1_address0_we <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd15))) begin
+ csrbank2_dfii_pi1_address0_we <= (~interface2_bank_bus_we);
+ end
+end
+assign csrbank2_dfii_pi1_baddress0_r = interface2_bank_bus_dat_w[2:0];
+always @(*) begin
+ csrbank2_dfii_pi1_baddress0_re <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd16))) begin
+ csrbank2_dfii_pi1_baddress0_re <= interface2_bank_bus_we;
+ end
+end
+always @(*) begin
+ csrbank2_dfii_pi1_baddress0_we <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd16))) begin
+ csrbank2_dfii_pi1_baddress0_we <= (~interface2_bank_bus_we);
+ end
+end
+assign csrbank2_dfii_pi1_wrdata3_r = interface2_bank_bus_dat_w[31:0];
+always @(*) begin
+ csrbank2_dfii_pi1_wrdata3_we <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd17))) begin
+ csrbank2_dfii_pi1_wrdata3_we <= (~interface2_bank_bus_we);
+ end
+end
+always @(*) begin
+ csrbank2_dfii_pi1_wrdata3_re <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd17))) begin
+ csrbank2_dfii_pi1_wrdata3_re <= interface2_bank_bus_we;
+ end
+end
+assign csrbank2_dfii_pi1_wrdata2_r = interface2_bank_bus_dat_w[31:0];
+always @(*) begin
+ csrbank2_dfii_pi1_wrdata2_re <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd18))) begin
+ csrbank2_dfii_pi1_wrdata2_re <= interface2_bank_bus_we;
+ end
+end
+always @(*) begin
+ csrbank2_dfii_pi1_wrdata2_we <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd18))) begin
+ csrbank2_dfii_pi1_wrdata2_we <= (~interface2_bank_bus_we);
+ end
+end
+assign csrbank2_dfii_pi1_wrdata1_r = interface2_bank_bus_dat_w[31:0];
+always @(*) begin
+ csrbank2_dfii_pi1_wrdata1_we <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd19))) begin
+ csrbank2_dfii_pi1_wrdata1_we <= (~interface2_bank_bus_we);
+ end
+end
+always @(*) begin
+ csrbank2_dfii_pi1_wrdata1_re <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd19))) begin
+ csrbank2_dfii_pi1_wrdata1_re <= interface2_bank_bus_we;
+ end
+end
+assign csrbank2_dfii_pi1_wrdata0_r = interface2_bank_bus_dat_w[31:0];
+always @(*) begin
+ csrbank2_dfii_pi1_wrdata0_we <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd20))) begin
+ csrbank2_dfii_pi1_wrdata0_we <= (~interface2_bank_bus_we);
+ end
+end
+always @(*) begin
+ csrbank2_dfii_pi1_wrdata0_re <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd20))) begin
+ csrbank2_dfii_pi1_wrdata0_re <= interface2_bank_bus_we;
+ end
+end
+assign csrbank2_dfii_pi1_rddata3_r = interface2_bank_bus_dat_w[31:0];
+always @(*) begin
+ csrbank2_dfii_pi1_rddata3_re <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd21))) begin
+ csrbank2_dfii_pi1_rddata3_re <= interface2_bank_bus_we;
+ end
+end
+always @(*) begin
+ csrbank2_dfii_pi1_rddata3_we <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd21))) begin
+ csrbank2_dfii_pi1_rddata3_we <= (~interface2_bank_bus_we);
+ end
+end
+assign csrbank2_dfii_pi1_rddata2_r = interface2_bank_bus_dat_w[31:0];
+always @(*) begin
+ csrbank2_dfii_pi1_rddata2_we <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd22))) begin
+ csrbank2_dfii_pi1_rddata2_we <= (~interface2_bank_bus_we);
+ end
+end
+always @(*) begin
+ csrbank2_dfii_pi1_rddata2_re <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd22))) begin
+ csrbank2_dfii_pi1_rddata2_re <= interface2_bank_bus_we;
+ end
+end
+assign csrbank2_dfii_pi1_rddata1_r = interface2_bank_bus_dat_w[31:0];
+always @(*) begin
+ csrbank2_dfii_pi1_rddata1_we <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd23))) begin
+ csrbank2_dfii_pi1_rddata1_we <= (~interface2_bank_bus_we);
+ end
+end
+always @(*) begin
+ csrbank2_dfii_pi1_rddata1_re <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd23))) begin
+ csrbank2_dfii_pi1_rddata1_re <= interface2_bank_bus_we;
+ end
+end
+assign csrbank2_dfii_pi1_rddata0_r = interface2_bank_bus_dat_w[31:0];
+always @(*) begin
+ csrbank2_dfii_pi1_rddata0_re <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd24))) begin
+ csrbank2_dfii_pi1_rddata0_re <= interface2_bank_bus_we;
+ end
+end
+always @(*) begin
+ csrbank2_dfii_pi1_rddata0_we <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd24))) begin
+ csrbank2_dfii_pi1_rddata0_we <= (~interface2_bank_bus_we);
+ end
+end
+assign litedramcore_sel = litedramcore_storage[0];
+assign litedramcore_cke = litedramcore_storage[1];
+assign litedramcore_odt = litedramcore_storage[2];
+assign litedramcore_reset_n = litedramcore_storage[3];
+assign csrbank2_dfii_control0_w = litedramcore_storage[3:0];
+assign csrbank2_dfii_pi0_command0_w = litedramcore_phaseinjector0_command_storage[5:0];
+assign csrbank2_dfii_pi0_address0_w = litedramcore_phaseinjector0_address_storage[14:0];
+assign csrbank2_dfii_pi0_baddress0_w = litedramcore_phaseinjector0_baddress_storage[2:0];
+assign csrbank2_dfii_pi0_wrdata3_w = litedramcore_phaseinjector0_wrdata_storage[127:96];
+assign csrbank2_dfii_pi0_wrdata2_w = litedramcore_phaseinjector0_wrdata_storage[95:64];
+assign csrbank2_dfii_pi0_wrdata1_w = litedramcore_phaseinjector0_wrdata_storage[63:32];
+assign csrbank2_dfii_pi0_wrdata0_w = litedramcore_phaseinjector0_wrdata_storage[31:0];
+assign csrbank2_dfii_pi0_rddata3_w = litedramcore_phaseinjector0_rddata_status[127:96];
+assign csrbank2_dfii_pi0_rddata2_w = litedramcore_phaseinjector0_rddata_status[95:64];
+assign csrbank2_dfii_pi0_rddata1_w = litedramcore_phaseinjector0_rddata_status[63:32];
+assign csrbank2_dfii_pi0_rddata0_w = litedramcore_phaseinjector0_rddata_status[31:0];
+assign litedramcore_phaseinjector0_rddata_we = csrbank2_dfii_pi0_rddata0_we;
+assign csrbank2_dfii_pi1_command0_w = litedramcore_phaseinjector1_command_storage[5:0];
+assign csrbank2_dfii_pi1_address0_w = litedramcore_phaseinjector1_address_storage[14:0];
+assign csrbank2_dfii_pi1_baddress0_w = litedramcore_phaseinjector1_baddress_storage[2:0];
+assign csrbank2_dfii_pi1_wrdata3_w = litedramcore_phaseinjector1_wrdata_storage[127:96];
+assign csrbank2_dfii_pi1_wrdata2_w = litedramcore_phaseinjector1_wrdata_storage[95:64];
+assign csrbank2_dfii_pi1_wrdata1_w = litedramcore_phaseinjector1_wrdata_storage[63:32];
+assign csrbank2_dfii_pi1_wrdata0_w = litedramcore_phaseinjector1_wrdata_storage[31:0];
+assign csrbank2_dfii_pi1_rddata3_w = litedramcore_phaseinjector1_rddata_status[127:96];
+assign csrbank2_dfii_pi1_rddata2_w = litedramcore_phaseinjector1_rddata_status[95:64];
+assign csrbank2_dfii_pi1_rddata1_w = litedramcore_phaseinjector1_rddata_status[63:32];
+assign csrbank2_dfii_pi1_rddata0_w = litedramcore_phaseinjector1_rddata_status[31:0];
+assign litedramcore_phaseinjector1_rddata_we = csrbank2_dfii_pi1_rddata0_we;
+assign csr_interconnect_adr = litedramcore_adr;
+assign csr_interconnect_we = litedramcore_we;
+assign csr_interconnect_dat_w = litedramcore_dat_w;
+assign litedramcore_dat_r = csr_interconnect_dat_r;
+assign interface0_bank_bus_adr = csr_interconnect_adr;
+assign interface1_bank_bus_adr = csr_interconnect_adr;
+assign interface2_bank_bus_adr = csr_interconnect_adr;
+assign interface0_bank_bus_we = csr_interconnect_we;
+assign interface1_bank_bus_we = csr_interconnect_we;
+assign interface2_bank_bus_we = csr_interconnect_we;
+assign interface0_bank_bus_dat_w = csr_interconnect_dat_w;
+assign interface1_bank_bus_dat_w = csr_interconnect_dat_w;
+assign interface2_bank_bus_dat_w = csr_interconnect_dat_w;
+assign csr_interconnect_dat_r = ((interface0_bank_bus_dat_r | interface1_bank_bus_dat_r) | interface2_bank_bus_dat_r);
+always @(*) begin
+ rhs_array_muxed0 <= 1'd0;
+ case (litedramcore_choose_cmd_grant)
+ 1'd0: begin
+ rhs_array_muxed0 <= litedramcore_choose_cmd_valids[0];
+ end
+ 1'd1: begin
+ rhs_array_muxed0 <= litedramcore_choose_cmd_valids[1];
+ end
+ 2'd2: begin
+ rhs_array_muxed0 <= litedramcore_choose_cmd_valids[2];
+ end
+ 2'd3: begin
+ rhs_array_muxed0 <= litedramcore_choose_cmd_valids[3];
+ end
+ 3'd4: begin
+ rhs_array_muxed0 <= litedramcore_choose_cmd_valids[4];
+ end
+ 3'd5: begin
+ rhs_array_muxed0 <= litedramcore_choose_cmd_valids[5];
+ end
+ 3'd6: begin
+ rhs_array_muxed0 <= litedramcore_choose_cmd_valids[6];
+ end
+ default: begin
+ rhs_array_muxed0 <= litedramcore_choose_cmd_valids[7];
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed1 <= 15'd0;
+ case (litedramcore_choose_cmd_grant)
+ 1'd0: begin
+ rhs_array_muxed1 <= litedramcore_bankmachine0_cmd_payload_a;
+ end
+ 1'd1: begin
+ rhs_array_muxed1 <= litedramcore_bankmachine1_cmd_payload_a;
+ end
+ 2'd2: begin
+ rhs_array_muxed1 <= litedramcore_bankmachine2_cmd_payload_a;
+ end
+ 2'd3: begin
+ rhs_array_muxed1 <= litedramcore_bankmachine3_cmd_payload_a;
+ end
+ 3'd4: begin
+ rhs_array_muxed1 <= litedramcore_bankmachine4_cmd_payload_a;
+ end
+ 3'd5: begin
+ rhs_array_muxed1 <= litedramcore_bankmachine5_cmd_payload_a;
+ end
+ 3'd6: begin
+ rhs_array_muxed1 <= litedramcore_bankmachine6_cmd_payload_a;
+ end
+ default: begin
+ rhs_array_muxed1 <= litedramcore_bankmachine7_cmd_payload_a;
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed2 <= 3'd0;
+ case (litedramcore_choose_cmd_grant)
+ 1'd0: begin
+ rhs_array_muxed2 <= litedramcore_bankmachine0_cmd_payload_ba;
+ end
+ 1'd1: begin
+ rhs_array_muxed2 <= litedramcore_bankmachine1_cmd_payload_ba;
+ end
+ 2'd2: begin
+ rhs_array_muxed2 <= litedramcore_bankmachine2_cmd_payload_ba;
+ end
+ 2'd3: begin
+ rhs_array_muxed2 <= litedramcore_bankmachine3_cmd_payload_ba;
+ end
+ 3'd4: begin
+ rhs_array_muxed2 <= litedramcore_bankmachine4_cmd_payload_ba;
+ end
+ 3'd5: begin
+ rhs_array_muxed2 <= litedramcore_bankmachine5_cmd_payload_ba;
+ end
+ 3'd6: begin
+ rhs_array_muxed2 <= litedramcore_bankmachine6_cmd_payload_ba;
+ end
+ default: begin
+ rhs_array_muxed2 <= litedramcore_bankmachine7_cmd_payload_ba;
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed3 <= 1'd0;
+ case (litedramcore_choose_cmd_grant)
+ 1'd0: begin
+ rhs_array_muxed3 <= litedramcore_bankmachine0_cmd_payload_is_read;
+ end
+ 1'd1: begin
+ rhs_array_muxed3 <= litedramcore_bankmachine1_cmd_payload_is_read;
+ end
+ 2'd2: begin
+ rhs_array_muxed3 <= litedramcore_bankmachine2_cmd_payload_is_read;
+ end
+ 2'd3: begin
+ rhs_array_muxed3 <= litedramcore_bankmachine3_cmd_payload_is_read;
+ end
+ 3'd4: begin
+ rhs_array_muxed3 <= litedramcore_bankmachine4_cmd_payload_is_read;
+ end
+ 3'd5: begin
+ rhs_array_muxed3 <= litedramcore_bankmachine5_cmd_payload_is_read;
+ end
+ 3'd6: begin
+ rhs_array_muxed3 <= litedramcore_bankmachine6_cmd_payload_is_read;
+ end
+ default: begin
+ rhs_array_muxed3 <= litedramcore_bankmachine7_cmd_payload_is_read;
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed4 <= 1'd0;
+ case (litedramcore_choose_cmd_grant)
+ 1'd0: begin
+ rhs_array_muxed4 <= litedramcore_bankmachine0_cmd_payload_is_write;
+ end
+ 1'd1: begin
+ rhs_array_muxed4 <= litedramcore_bankmachine1_cmd_payload_is_write;
+ end
+ 2'd2: begin
+ rhs_array_muxed4 <= litedramcore_bankmachine2_cmd_payload_is_write;
+ end
+ 2'd3: begin
+ rhs_array_muxed4 <= litedramcore_bankmachine3_cmd_payload_is_write;
+ end
+ 3'd4: begin
+ rhs_array_muxed4 <= litedramcore_bankmachine4_cmd_payload_is_write;
+ end
+ 3'd5: begin
+ rhs_array_muxed4 <= litedramcore_bankmachine5_cmd_payload_is_write;
+ end
+ 3'd6: begin
+ rhs_array_muxed4 <= litedramcore_bankmachine6_cmd_payload_is_write;
+ end
+ default: begin
+ rhs_array_muxed4 <= litedramcore_bankmachine7_cmd_payload_is_write;
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed5 <= 1'd0;
+ case (litedramcore_choose_cmd_grant)
+ 1'd0: begin
+ rhs_array_muxed5 <= litedramcore_bankmachine0_cmd_payload_is_cmd;
+ end
+ 1'd1: begin
+ rhs_array_muxed5 <= litedramcore_bankmachine1_cmd_payload_is_cmd;
+ end
+ 2'd2: begin
+ rhs_array_muxed5 <= litedramcore_bankmachine2_cmd_payload_is_cmd;
+ end
+ 2'd3: begin
+ rhs_array_muxed5 <= litedramcore_bankmachine3_cmd_payload_is_cmd;
+ end
+ 3'd4: begin
+ rhs_array_muxed5 <= litedramcore_bankmachine4_cmd_payload_is_cmd;
+ end
+ 3'd5: begin
+ rhs_array_muxed5 <= litedramcore_bankmachine5_cmd_payload_is_cmd;
+ end
+ 3'd6: begin
+ rhs_array_muxed5 <= litedramcore_bankmachine6_cmd_payload_is_cmd;
+ end
+ default: begin
+ rhs_array_muxed5 <= litedramcore_bankmachine7_cmd_payload_is_cmd;
+ end
+ endcase
+end
+always @(*) begin
+ t_array_muxed0 <= 1'd0;
+ case (litedramcore_choose_cmd_grant)
+ 1'd0: begin
+ t_array_muxed0 <= litedramcore_bankmachine0_cmd_payload_cas;
+ end
+ 1'd1: begin
+ t_array_muxed0 <= litedramcore_bankmachine1_cmd_payload_cas;
+ end
+ 2'd2: begin
+ t_array_muxed0 <= litedramcore_bankmachine2_cmd_payload_cas;
+ end
+ 2'd3: begin
+ t_array_muxed0 <= litedramcore_bankmachine3_cmd_payload_cas;
+ end
+ 3'd4: begin
+ t_array_muxed0 <= litedramcore_bankmachine4_cmd_payload_cas;
+ end
+ 3'd5: begin
+ t_array_muxed0 <= litedramcore_bankmachine5_cmd_payload_cas;
+ end
+ 3'd6: begin
+ t_array_muxed0 <= litedramcore_bankmachine6_cmd_payload_cas;
+ end
+ default: begin
+ t_array_muxed0 <= litedramcore_bankmachine7_cmd_payload_cas;
+ end
+ endcase
+end
+always @(*) begin
+ t_array_muxed1 <= 1'd0;
+ case (litedramcore_choose_cmd_grant)
+ 1'd0: begin
+ t_array_muxed1 <= litedramcore_bankmachine0_cmd_payload_ras;
+ end
+ 1'd1: begin
+ t_array_muxed1 <= litedramcore_bankmachine1_cmd_payload_ras;
+ end
+ 2'd2: begin
+ t_array_muxed1 <= litedramcore_bankmachine2_cmd_payload_ras;
+ end
+ 2'd3: begin
+ t_array_muxed1 <= litedramcore_bankmachine3_cmd_payload_ras;
+ end
+ 3'd4: begin
+ t_array_muxed1 <= litedramcore_bankmachine4_cmd_payload_ras;
+ end
+ 3'd5: begin
+ t_array_muxed1 <= litedramcore_bankmachine5_cmd_payload_ras;
+ end
+ 3'd6: begin
+ t_array_muxed1 <= litedramcore_bankmachine6_cmd_payload_ras;
+ end
+ default: begin
+ t_array_muxed1 <= litedramcore_bankmachine7_cmd_payload_ras;
+ end
+ endcase
+end
+always @(*) begin
+ t_array_muxed2 <= 1'd0;
+ case (litedramcore_choose_cmd_grant)
+ 1'd0: begin
+ t_array_muxed2 <= litedramcore_bankmachine0_cmd_payload_we;
+ end
+ 1'd1: begin
+ t_array_muxed2 <= litedramcore_bankmachine1_cmd_payload_we;
+ end
+ 2'd2: begin
+ t_array_muxed2 <= litedramcore_bankmachine2_cmd_payload_we;
+ end
+ 2'd3: begin
+ t_array_muxed2 <= litedramcore_bankmachine3_cmd_payload_we;
+ end
+ 3'd4: begin
+ t_array_muxed2 <= litedramcore_bankmachine4_cmd_payload_we;
+ end
+ 3'd5: begin
+ t_array_muxed2 <= litedramcore_bankmachine5_cmd_payload_we;
+ end
+ 3'd6: begin
+ t_array_muxed2 <= litedramcore_bankmachine6_cmd_payload_we;
+ end
+ default: begin
+ t_array_muxed2 <= litedramcore_bankmachine7_cmd_payload_we;
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed6 <= 1'd0;
+ case (litedramcore_choose_req_grant)
+ 1'd0: begin
+ rhs_array_muxed6 <= litedramcore_choose_req_valids[0];
+ end
+ 1'd1: begin
+ rhs_array_muxed6 <= litedramcore_choose_req_valids[1];
+ end
+ 2'd2: begin
+ rhs_array_muxed6 <= litedramcore_choose_req_valids[2];
+ end
+ 2'd3: begin
+ rhs_array_muxed6 <= litedramcore_choose_req_valids[3];
+ end
+ 3'd4: begin
+ rhs_array_muxed6 <= litedramcore_choose_req_valids[4];
+ end
+ 3'd5: begin
+ rhs_array_muxed6 <= litedramcore_choose_req_valids[5];
+ end
+ 3'd6: begin
+ rhs_array_muxed6 <= litedramcore_choose_req_valids[6];
+ end
+ default: begin
+ rhs_array_muxed6 <= litedramcore_choose_req_valids[7];
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed7 <= 15'd0;
+ case (litedramcore_choose_req_grant)
+ 1'd0: begin
+ rhs_array_muxed7 <= litedramcore_bankmachine0_cmd_payload_a;
+ end
+ 1'd1: begin
+ rhs_array_muxed7 <= litedramcore_bankmachine1_cmd_payload_a;
+ end
+ 2'd2: begin
+ rhs_array_muxed7 <= litedramcore_bankmachine2_cmd_payload_a;
+ end
+ 2'd3: begin
+ rhs_array_muxed7 <= litedramcore_bankmachine3_cmd_payload_a;
+ end
+ 3'd4: begin
+ rhs_array_muxed7 <= litedramcore_bankmachine4_cmd_payload_a;
+ end
+ 3'd5: begin
+ rhs_array_muxed7 <= litedramcore_bankmachine5_cmd_payload_a;
+ end
+ 3'd6: begin
+ rhs_array_muxed7 <= litedramcore_bankmachine6_cmd_payload_a;
+ end
+ default: begin
+ rhs_array_muxed7 <= litedramcore_bankmachine7_cmd_payload_a;
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed8 <= 3'd0;
+ case (litedramcore_choose_req_grant)
+ 1'd0: begin
+ rhs_array_muxed8 <= litedramcore_bankmachine0_cmd_payload_ba;
+ end
+ 1'd1: begin
+ rhs_array_muxed8 <= litedramcore_bankmachine1_cmd_payload_ba;
+ end
+ 2'd2: begin
+ rhs_array_muxed8 <= litedramcore_bankmachine2_cmd_payload_ba;
+ end
+ 2'd3: begin
+ rhs_array_muxed8 <= litedramcore_bankmachine3_cmd_payload_ba;
+ end
+ 3'd4: begin
+ rhs_array_muxed8 <= litedramcore_bankmachine4_cmd_payload_ba;
+ end
+ 3'd5: begin
+ rhs_array_muxed8 <= litedramcore_bankmachine5_cmd_payload_ba;
+ end
+ 3'd6: begin
+ rhs_array_muxed8 <= litedramcore_bankmachine6_cmd_payload_ba;
+ end
+ default: begin
+ rhs_array_muxed8 <= litedramcore_bankmachine7_cmd_payload_ba;
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed9 <= 1'd0;
+ case (litedramcore_choose_req_grant)
+ 1'd0: begin
+ rhs_array_muxed9 <= litedramcore_bankmachine0_cmd_payload_is_read;
+ end
+ 1'd1: begin
+ rhs_array_muxed9 <= litedramcore_bankmachine1_cmd_payload_is_read;
+ end
+ 2'd2: begin
+ rhs_array_muxed9 <= litedramcore_bankmachine2_cmd_payload_is_read;
+ end
+ 2'd3: begin
+ rhs_array_muxed9 <= litedramcore_bankmachine3_cmd_payload_is_read;
+ end
+ 3'd4: begin
+ rhs_array_muxed9 <= litedramcore_bankmachine4_cmd_payload_is_read;
+ end
+ 3'd5: begin
+ rhs_array_muxed9 <= litedramcore_bankmachine5_cmd_payload_is_read;
+ end
+ 3'd6: begin
+ rhs_array_muxed9 <= litedramcore_bankmachine6_cmd_payload_is_read;
+ end
+ default: begin
+ rhs_array_muxed9 <= litedramcore_bankmachine7_cmd_payload_is_read;
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed10 <= 1'd0;
+ case (litedramcore_choose_req_grant)
+ 1'd0: begin
+ rhs_array_muxed10 <= litedramcore_bankmachine0_cmd_payload_is_write;
+ end
+ 1'd1: begin
+ rhs_array_muxed10 <= litedramcore_bankmachine1_cmd_payload_is_write;
+ end
+ 2'd2: begin
+ rhs_array_muxed10 <= litedramcore_bankmachine2_cmd_payload_is_write;
+ end
+ 2'd3: begin
+ rhs_array_muxed10 <= litedramcore_bankmachine3_cmd_payload_is_write;
+ end
+ 3'd4: begin
+ rhs_array_muxed10 <= litedramcore_bankmachine4_cmd_payload_is_write;
+ end
+ 3'd5: begin
+ rhs_array_muxed10 <= litedramcore_bankmachine5_cmd_payload_is_write;
+ end
+ 3'd6: begin
+ rhs_array_muxed10 <= litedramcore_bankmachine6_cmd_payload_is_write;
+ end
+ default: begin
+ rhs_array_muxed10 <= litedramcore_bankmachine7_cmd_payload_is_write;
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed11 <= 1'd0;
+ case (litedramcore_choose_req_grant)
+ 1'd0: begin
+ rhs_array_muxed11 <= litedramcore_bankmachine0_cmd_payload_is_cmd;
+ end
+ 1'd1: begin
+ rhs_array_muxed11 <= litedramcore_bankmachine1_cmd_payload_is_cmd;
+ end
+ 2'd2: begin
+ rhs_array_muxed11 <= litedramcore_bankmachine2_cmd_payload_is_cmd;
+ end
+ 2'd3: begin
+ rhs_array_muxed11 <= litedramcore_bankmachine3_cmd_payload_is_cmd;
+ end
+ 3'd4: begin
+ rhs_array_muxed11 <= litedramcore_bankmachine4_cmd_payload_is_cmd;
+ end
+ 3'd5: begin
+ rhs_array_muxed11 <= litedramcore_bankmachine5_cmd_payload_is_cmd;
+ end
+ 3'd6: begin
+ rhs_array_muxed11 <= litedramcore_bankmachine6_cmd_payload_is_cmd;
+ end
+ default: begin
+ rhs_array_muxed11 <= litedramcore_bankmachine7_cmd_payload_is_cmd;
+ end
+ endcase
+end
+always @(*) begin
+ t_array_muxed3 <= 1'd0;
+ case (litedramcore_choose_req_grant)
+ 1'd0: begin
+ t_array_muxed3 <= litedramcore_bankmachine0_cmd_payload_cas;
+ end
+ 1'd1: begin
+ t_array_muxed3 <= litedramcore_bankmachine1_cmd_payload_cas;
+ end
+ 2'd2: begin
+ t_array_muxed3 <= litedramcore_bankmachine2_cmd_payload_cas;
+ end
+ 2'd3: begin
+ t_array_muxed3 <= litedramcore_bankmachine3_cmd_payload_cas;
+ end
+ 3'd4: begin
+ t_array_muxed3 <= litedramcore_bankmachine4_cmd_payload_cas;
+ end
+ 3'd5: begin
+ t_array_muxed3 <= litedramcore_bankmachine5_cmd_payload_cas;
+ end
+ 3'd6: begin
+ t_array_muxed3 <= litedramcore_bankmachine6_cmd_payload_cas;
+ end
+ default: begin
+ t_array_muxed3 <= litedramcore_bankmachine7_cmd_payload_cas;
+ end
+ endcase
+end
+always @(*) begin
+ t_array_muxed4 <= 1'd0;
+ case (litedramcore_choose_req_grant)
+ 1'd0: begin
+ t_array_muxed4 <= litedramcore_bankmachine0_cmd_payload_ras;
+ end
+ 1'd1: begin
+ t_array_muxed4 <= litedramcore_bankmachine1_cmd_payload_ras;
+ end
+ 2'd2: begin
+ t_array_muxed4 <= litedramcore_bankmachine2_cmd_payload_ras;
+ end
+ 2'd3: begin
+ t_array_muxed4 <= litedramcore_bankmachine3_cmd_payload_ras;
+ end
+ 3'd4: begin
+ t_array_muxed4 <= litedramcore_bankmachine4_cmd_payload_ras;
+ end
+ 3'd5: begin
+ t_array_muxed4 <= litedramcore_bankmachine5_cmd_payload_ras;
+ end
+ 3'd6: begin
+ t_array_muxed4 <= litedramcore_bankmachine6_cmd_payload_ras;
+ end
+ default: begin
+ t_array_muxed4 <= litedramcore_bankmachine7_cmd_payload_ras;
+ end
+ endcase
+end
+always @(*) begin
+ t_array_muxed5 <= 1'd0;
+ case (litedramcore_choose_req_grant)
+ 1'd0: begin
+ t_array_muxed5 <= litedramcore_bankmachine0_cmd_payload_we;
+ end
+ 1'd1: begin
+ t_array_muxed5 <= litedramcore_bankmachine1_cmd_payload_we;
+ end
+ 2'd2: begin
+ t_array_muxed5 <= litedramcore_bankmachine2_cmd_payload_we;
+ end
+ 2'd3: begin
+ t_array_muxed5 <= litedramcore_bankmachine3_cmd_payload_we;
+ end
+ 3'd4: begin
+ t_array_muxed5 <= litedramcore_bankmachine4_cmd_payload_we;
+ end
+ 3'd5: begin
+ t_array_muxed5 <= litedramcore_bankmachine5_cmd_payload_we;
+ end
+ 3'd6: begin
+ t_array_muxed5 <= litedramcore_bankmachine6_cmd_payload_we;
+ end
+ default: begin
+ t_array_muxed5 <= litedramcore_bankmachine7_cmd_payload_we;
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed12 <= 22'd0;
+ case (litedramcore_roundrobin0_grant)
+ default: begin
+ rhs_array_muxed12 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]};
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed13 <= 1'd0;
+ case (litedramcore_roundrobin0_grant)
+ default: begin
+ rhs_array_muxed13 <= user_port_cmd_payload_we;
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed14 <= 1'd0;
+ case (litedramcore_roundrobin0_grant)
+ default: begin
+ rhs_array_muxed14 <= (((user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((litedramcore_locked0 | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed15 <= 22'd0;
+ case (litedramcore_roundrobin1_grant)
+ default: begin
+ rhs_array_muxed15 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]};
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed16 <= 1'd0;
+ case (litedramcore_roundrobin1_grant)
+ default: begin
+ rhs_array_muxed16 <= user_port_cmd_payload_we;
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed17 <= 1'd0;
+ case (litedramcore_roundrobin1_grant)
+ default: begin
+ rhs_array_muxed17 <= (((user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((litedramcore_locked1 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed18 <= 22'd0;
+ case (litedramcore_roundrobin2_grant)
+ default: begin
+ rhs_array_muxed18 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]};
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed19 <= 1'd0;
+ case (litedramcore_roundrobin2_grant)
+ default: begin
+ rhs_array_muxed19 <= user_port_cmd_payload_we;
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed20 <= 1'd0;
+ case (litedramcore_roundrobin2_grant)
+ default: begin
+ rhs_array_muxed20 <= (((user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((litedramcore_locked2 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed21 <= 22'd0;
+ case (litedramcore_roundrobin3_grant)
+ default: begin
+ rhs_array_muxed21 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]};
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed22 <= 1'd0;
+ case (litedramcore_roundrobin3_grant)
+ default: begin
+ rhs_array_muxed22 <= user_port_cmd_payload_we;
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed23 <= 1'd0;
+ case (litedramcore_roundrobin3_grant)
+ default: begin
+ rhs_array_muxed23 <= (((user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((litedramcore_locked3 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed24 <= 22'd0;
+ case (litedramcore_roundrobin4_grant)
+ default: begin
+ rhs_array_muxed24 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]};
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed25 <= 1'd0;
+ case (litedramcore_roundrobin4_grant)
+ default: begin
+ rhs_array_muxed25 <= user_port_cmd_payload_we;
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed26 <= 1'd0;
+ case (litedramcore_roundrobin4_grant)
+ default: begin
+ rhs_array_muxed26 <= (((user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((litedramcore_locked4 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed27 <= 22'd0;
+ case (litedramcore_roundrobin5_grant)
+ default: begin
+ rhs_array_muxed27 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]};
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed28 <= 1'd0;
+ case (litedramcore_roundrobin5_grant)
+ default: begin
+ rhs_array_muxed28 <= user_port_cmd_payload_we;
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed29 <= 1'd0;
+ case (litedramcore_roundrobin5_grant)
+ default: begin
+ rhs_array_muxed29 <= (((user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((litedramcore_locked5 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed30 <= 22'd0;
+ case (litedramcore_roundrobin6_grant)
+ default: begin
+ rhs_array_muxed30 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]};
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed31 <= 1'd0;
+ case (litedramcore_roundrobin6_grant)
+ default: begin
+ rhs_array_muxed31 <= user_port_cmd_payload_we;
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed32 <= 1'd0;
+ case (litedramcore_roundrobin6_grant)
+ default: begin
+ rhs_array_muxed32 <= (((user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((litedramcore_locked6 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed33 <= 22'd0;
+ case (litedramcore_roundrobin7_grant)
+ default: begin
+ rhs_array_muxed33 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]};
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed34 <= 1'd0;
+ case (litedramcore_roundrobin7_grant)
+ default: begin
+ rhs_array_muxed34 <= user_port_cmd_payload_we;
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed35 <= 1'd0;
+ case (litedramcore_roundrobin7_grant)
+ default: begin
+ rhs_array_muxed35 <= (((user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((litedramcore_locked7 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))))) & user_port_cmd_valid);
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed0 <= 3'd0;
+ case (litedramcore_steerer_sel0)
+ 1'd0: begin
+ array_muxed0 <= litedramcore_nop_ba[2:0];
+ end
+ 1'd1: begin
+ array_muxed0 <= litedramcore_choose_cmd_cmd_payload_ba[2:0];
+ end
+ 2'd2: begin
+ array_muxed0 <= litedramcore_choose_req_cmd_payload_ba[2:0];
+ end
+ default: begin
+ array_muxed0 <= litedramcore_cmd_payload_ba[2:0];
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed1 <= 15'd0;
+ case (litedramcore_steerer_sel0)
+ 1'd0: begin
+ array_muxed1 <= litedramcore_nop_a;
+ end
+ 1'd1: begin
+ array_muxed1 <= litedramcore_choose_cmd_cmd_payload_a;
+ end
+ 2'd2: begin
+ array_muxed1 <= litedramcore_choose_req_cmd_payload_a;
+ end
+ default: begin
+ array_muxed1 <= litedramcore_cmd_payload_a;
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed2 <= 1'd0;
+ case (litedramcore_steerer_sel0)
+ 1'd0: begin
+ array_muxed2 <= 1'd0;
+ end
+ 1'd1: begin
+ array_muxed2 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas);
+ end
+ 2'd2: begin
+ array_muxed2 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas);
+ end
+ default: begin
+ array_muxed2 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas);
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed3 <= 1'd0;
+ case (litedramcore_steerer_sel0)
+ 1'd0: begin
+ array_muxed3 <= 1'd0;
+ end
+ 1'd1: begin
+ array_muxed3 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras);
+ end
+ 2'd2: begin
+ array_muxed3 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras);
+ end
+ default: begin
+ array_muxed3 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras);
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed4 <= 1'd0;
+ case (litedramcore_steerer_sel0)
+ 1'd0: begin
+ array_muxed4 <= 1'd0;
+ end
+ 1'd1: begin
+ array_muxed4 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we);
+ end
+ 2'd2: begin
+ array_muxed4 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we);
+ end
+ default: begin
+ array_muxed4 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we);
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed5 <= 1'd0;
+ case (litedramcore_steerer_sel0)
+ 1'd0: begin
+ array_muxed5 <= 1'd0;
+ end
+ 1'd1: begin
+ array_muxed5 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read);
+ end
+ 2'd2: begin
+ array_muxed5 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read);
+ end
+ default: begin
+ array_muxed5 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read);
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed6 <= 1'd0;
+ case (litedramcore_steerer_sel0)
+ 1'd0: begin
+ array_muxed6 <= 1'd0;
+ end
+ 1'd1: begin
+ array_muxed6 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write);
+ end
+ 2'd2: begin
+ array_muxed6 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write);
+ end
+ default: begin
+ array_muxed6 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write);
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed7 <= 3'd0;
+ case (litedramcore_steerer_sel1)
+ 1'd0: begin
+ array_muxed7 <= litedramcore_nop_ba[2:0];
+ end
+ 1'd1: begin
+ array_muxed7 <= litedramcore_choose_cmd_cmd_payload_ba[2:0];
+ end
+ 2'd2: begin
+ array_muxed7 <= litedramcore_choose_req_cmd_payload_ba[2:0];
+ end
+ default: begin
+ array_muxed7 <= litedramcore_cmd_payload_ba[2:0];
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed8 <= 15'd0;
+ case (litedramcore_steerer_sel1)
+ 1'd0: begin
+ array_muxed8 <= litedramcore_nop_a;
+ end
+ 1'd1: begin
+ array_muxed8 <= litedramcore_choose_cmd_cmd_payload_a;
+ end
+ 2'd2: begin
+ array_muxed8 <= litedramcore_choose_req_cmd_payload_a;
+ end
+ default: begin
+ array_muxed8 <= litedramcore_cmd_payload_a;
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed9 <= 1'd0;
+ case (litedramcore_steerer_sel1)
+ 1'd0: begin
+ array_muxed9 <= 1'd0;
+ end
+ 1'd1: begin
+ array_muxed9 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas);
+ end
+ 2'd2: begin
+ array_muxed9 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas);
+ end
+ default: begin
+ array_muxed9 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas);
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed10 <= 1'd0;
+ case (litedramcore_steerer_sel1)
+ 1'd0: begin
+ array_muxed10 <= 1'd0;
+ end
+ 1'd1: begin
+ array_muxed10 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras);
+ end
+ 2'd2: begin
+ array_muxed10 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras);
+ end
+ default: begin
+ array_muxed10 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras);
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed11 <= 1'd0;
+ case (litedramcore_steerer_sel1)
+ 1'd0: begin
+ array_muxed11 <= 1'd0;
+ end
+ 1'd1: begin
+ array_muxed11 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we);
+ end
+ 2'd2: begin
+ array_muxed11 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we);
+ end
+ default: begin
+ array_muxed11 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we);
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed12 <= 1'd0;
+ case (litedramcore_steerer_sel1)
+ 1'd0: begin
+ array_muxed12 <= 1'd0;
+ end
+ 1'd1: begin
+ array_muxed12 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read);
+ end
+ 2'd2: begin
+ array_muxed12 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read);
+ end
+ default: begin
+ array_muxed12 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read);
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed13 <= 1'd0;
+ case (litedramcore_steerer_sel1)
+ 1'd0: begin
+ array_muxed13 <= 1'd0;
+ end
+ 1'd1: begin
+ array_muxed13 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write);
+ end
+ 2'd2: begin
+ array_muxed13 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write);
+ end
+ default: begin
+ array_muxed13 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write);
+ end
+ endcase
+end
+assign ddrphy_lock1 = regs1;
+
+
+//------------------------------------------------------------------------------
+// Synchronous Logic
+//------------------------------------------------------------------------------
+
+always @(posedge init_clk) begin
+ ddrphy_lock_d <= ddrphy_lock1;
+ if ((ddrphy_counter == 4'd8)) begin
+ ddrphy_freeze <= 1'd1;
+ end
+ if ((ddrphy_counter == 5'd16)) begin
+ ddrphy_stop1 <= 1'd1;
+ end
+ if ((ddrphy_counter == 5'd24)) begin
+ ddrphy_reset1 <= 1'd1;
+ end
+ if ((ddrphy_counter == 6'd32)) begin
+ ddrphy_reset1 <= 1'd0;
+ end
+ if ((ddrphy_counter == 6'd40)) begin
+ ddrphy_stop1 <= 1'd0;
+ end
+ if ((ddrphy_counter == 6'd48)) begin
+ ddrphy_freeze <= 1'd0;
+ end
+ if ((ddrphy_counter == 6'd56)) begin
+ ddrphy_pause1 <= 1'd1;
+ end
+ if ((ddrphy_counter == 7'd64)) begin
+ ddrphy_update <= 1'd1;
+ end
+ if ((ddrphy_counter == 7'd72)) begin
+ ddrphy_update <= 1'd0;
+ end
+ if ((ddrphy_counter == 7'd80)) begin
+ ddrphy_pause1 <= 1'd0;
+ end
+ if ((ddrphy_counter == 7'd80)) begin
+ ddrphy_counter <= 1'd0;
+ end else begin
+ if ((ddrphy_counter != 1'd0)) begin
+ ddrphy_counter <= (ddrphy_counter + 1'd1);
+ end else begin
+ if (ddrphy_new_lock) begin
+ ddrphy_counter <= 1'd1;
+ end
+ end
+ end
+ if (init_rst) begin
+ ddrphy_update <= 1'd0;
+ ddrphy_stop1 <= 1'd0;
+ ddrphy_freeze <= 1'd0;
+ ddrphy_pause1 <= 1'd0;
+ ddrphy_reset1 <= 1'd0;
+ ddrphy_lock_d <= 1'd0;
+ ddrphy_counter <= 7'd0;
+ end
+ regs0 <= ddrphy_lock0;
+ regs1 <= regs0;
+end
+
+always @(posedge por_clk) begin
+ if ((~crg_por_done)) begin
+ crg_por_count <= (crg_por_count - 1'd1);
+ end
+end
+
+always @(posedge sys_clk) begin
+ if ((ddrphy_dly_sel_storage[0] & ddrphy_rdly_dq_rst_re)) begin
+ ddrphy_rdly0 <= 1'd0;
+ end
+ if ((ddrphy_dly_sel_storage[0] & ddrphy_rdly_dq_inc_re)) begin
+ ddrphy_rdly0 <= (ddrphy_rdly0 + 1'd1);
+ end
+ ddrphy_burstdet_d0 <= ddrphy_burstdet0;
+ if (ddrphy_burstdet_clr_re) begin
+ ddrphy_burstdet_seen_status[0] <= 1'd0;
+ end
+ if ((ddrphy_burstdet0 & (~ddrphy_burstdet_d0))) begin
+ ddrphy_burstdet_seen_status[0] <= 1'd1;
+ end
+ ddrphy_dm_o_data_d0 <= ddrphy_dm_o_data0;
+ case (ddrphy_bl8_chunk)
+ 1'd0: begin
+ ddrphy_dm_o_data_muxed0 <= ddrphy_dm_o_data0[3:0];
+ end
+ 1'd1: begin
+ ddrphy_dm_o_data_muxed0 <= ddrphy_dm_o_data_d0[7:4];
+ end
+ endcase
+ ddrphy_dq_o_data_d0 <= ddrphy_dq_o_data0;
+ case (ddrphy_bl8_chunk)
+ 1'd0: begin
+ ddrphy_dq_o_data_muxed0 <= ddrphy_dq_o_data0[3:0];
+ end
+ 1'd1: begin
+ ddrphy_dq_o_data_muxed0 <= ddrphy_dq_o_data_d0[7:4];
+ end
+ endcase
+ ddrphy_dq_i_bitslip_o_d0 <= ddrphy_bitslip0_o;
+ ddrphy_dq_o_data_d1 <= ddrphy_dq_o_data1;
+ case (ddrphy_bl8_chunk)
+ 1'd0: begin
+ ddrphy_dq_o_data_muxed1 <= ddrphy_dq_o_data1[3:0];
+ end
+ 1'd1: begin
+ ddrphy_dq_o_data_muxed1 <= ddrphy_dq_o_data_d1[7:4];
+ end
+ endcase
+ ddrphy_dq_i_bitslip_o_d1 <= ddrphy_bitslip1_o;
+ ddrphy_dq_o_data_d2 <= ddrphy_dq_o_data2;
+ case (ddrphy_bl8_chunk)
+ 1'd0: begin
+ ddrphy_dq_o_data_muxed2 <= ddrphy_dq_o_data2[3:0];
+ end
+ 1'd1: begin
+ ddrphy_dq_o_data_muxed2 <= ddrphy_dq_o_data_d2[7:4];
+ end
+ endcase
+ ddrphy_dq_i_bitslip_o_d2 <= ddrphy_bitslip2_o;
+ ddrphy_dq_o_data_d3 <= ddrphy_dq_o_data3;
+ case (ddrphy_bl8_chunk)
+ 1'd0: begin
+ ddrphy_dq_o_data_muxed3 <= ddrphy_dq_o_data3[3:0];
+ end
+ 1'd1: begin
+ ddrphy_dq_o_data_muxed3 <= ddrphy_dq_o_data_d3[7:4];
+ end
+ endcase
+ ddrphy_dq_i_bitslip_o_d3 <= ddrphy_bitslip3_o;
+ ddrphy_dq_o_data_d4 <= ddrphy_dq_o_data4;
+ case (ddrphy_bl8_chunk)
+ 1'd0: begin
+ ddrphy_dq_o_data_muxed4 <= ddrphy_dq_o_data4[3:0];
+ end
+ 1'd1: begin
+ ddrphy_dq_o_data_muxed4 <= ddrphy_dq_o_data_d4[7:4];
+ end
+ endcase
+ ddrphy_dq_i_bitslip_o_d4 <= ddrphy_bitslip4_o;
+ ddrphy_dq_o_data_d5 <= ddrphy_dq_o_data5;
+ case (ddrphy_bl8_chunk)
+ 1'd0: begin
+ ddrphy_dq_o_data_muxed5 <= ddrphy_dq_o_data5[3:0];
+ end
+ 1'd1: begin
+ ddrphy_dq_o_data_muxed5 <= ddrphy_dq_o_data_d5[7:4];
+ end
+ endcase
+ ddrphy_dq_i_bitslip_o_d5 <= ddrphy_bitslip5_o;
+ ddrphy_dq_o_data_d6 <= ddrphy_dq_o_data6;
+ case (ddrphy_bl8_chunk)
+ 1'd0: begin
+ ddrphy_dq_o_data_muxed6 <= ddrphy_dq_o_data6[3:0];
+ end
+ 1'd1: begin
+ ddrphy_dq_o_data_muxed6 <= ddrphy_dq_o_data_d6[7:4];
+ end
+ endcase
+ ddrphy_dq_i_bitslip_o_d6 <= ddrphy_bitslip6_o;
+ ddrphy_dq_o_data_d7 <= ddrphy_dq_o_data7;
+ case (ddrphy_bl8_chunk)
+ 1'd0: begin
+ ddrphy_dq_o_data_muxed7 <= ddrphy_dq_o_data7[3:0];
+ end
+ 1'd1: begin
+ ddrphy_dq_o_data_muxed7 <= ddrphy_dq_o_data_d7[7:4];
+ end
+ endcase
+ ddrphy_dq_i_bitslip_o_d7 <= ddrphy_bitslip7_o;
+ if ((ddrphy_dly_sel_storage[1] & ddrphy_rdly_dq_rst_re)) begin
+ ddrphy_rdly1 <= 1'd0;
+ end
+ if ((ddrphy_dly_sel_storage[1] & ddrphy_rdly_dq_inc_re)) begin
+ ddrphy_rdly1 <= (ddrphy_rdly1 + 1'd1);
+ end
+ ddrphy_burstdet_d1 <= ddrphy_burstdet1;
+ if (ddrphy_burstdet_clr_re) begin
+ ddrphy_burstdet_seen_status[1] <= 1'd0;
+ end
+ if ((ddrphy_burstdet1 & (~ddrphy_burstdet_d1))) begin
+ ddrphy_burstdet_seen_status[1] <= 1'd1;
+ end
+ ddrphy_dm_o_data_d1 <= ddrphy_dm_o_data1;
+ case (ddrphy_bl8_chunk)
+ 1'd0: begin
+ ddrphy_dm_o_data_muxed1 <= ddrphy_dm_o_data1[3:0];
+ end
+ 1'd1: begin
+ ddrphy_dm_o_data_muxed1 <= ddrphy_dm_o_data_d1[7:4];
+ end
+ endcase
+ ddrphy_dq_o_data_d8 <= ddrphy_dq_o_data8;
+ case (ddrphy_bl8_chunk)
+ 1'd0: begin
+ ddrphy_dq_o_data_muxed8 <= ddrphy_dq_o_data8[3:0];
+ end
+ 1'd1: begin
+ ddrphy_dq_o_data_muxed8 <= ddrphy_dq_o_data_d8[7:4];
+ end
+ endcase
+ ddrphy_dq_i_bitslip_o_d8 <= ddrphy_bitslip8_o;
+ ddrphy_dq_o_data_d9 <= ddrphy_dq_o_data9;
+ case (ddrphy_bl8_chunk)
+ 1'd0: begin
+ ddrphy_dq_o_data_muxed9 <= ddrphy_dq_o_data9[3:0];
+ end
+ 1'd1: begin
+ ddrphy_dq_o_data_muxed9 <= ddrphy_dq_o_data_d9[7:4];
+ end
+ endcase
+ ddrphy_dq_i_bitslip_o_d9 <= ddrphy_bitslip9_o;
+ ddrphy_dq_o_data_d10 <= ddrphy_dq_o_data10;
+ case (ddrphy_bl8_chunk)
+ 1'd0: begin
+ ddrphy_dq_o_data_muxed10 <= ddrphy_dq_o_data10[3:0];
+ end
+ 1'd1: begin
+ ddrphy_dq_o_data_muxed10 <= ddrphy_dq_o_data_d10[7:4];
+ end
+ endcase
+ ddrphy_dq_i_bitslip_o_d10 <= ddrphy_bitslip10_o;
+ ddrphy_dq_o_data_d11 <= ddrphy_dq_o_data11;
+ case (ddrphy_bl8_chunk)
+ 1'd0: begin
+ ddrphy_dq_o_data_muxed11 <= ddrphy_dq_o_data11[3:0];
+ end
+ 1'd1: begin
+ ddrphy_dq_o_data_muxed11 <= ddrphy_dq_o_data_d11[7:4];
+ end
+ endcase
+ ddrphy_dq_i_bitslip_o_d11 <= ddrphy_bitslip11_o;
+ ddrphy_dq_o_data_d12 <= ddrphy_dq_o_data12;
+ case (ddrphy_bl8_chunk)
+ 1'd0: begin
+ ddrphy_dq_o_data_muxed12 <= ddrphy_dq_o_data12[3:0];
+ end
+ 1'd1: begin
+ ddrphy_dq_o_data_muxed12 <= ddrphy_dq_o_data_d12[7:4];
+ end
+ endcase
+ ddrphy_dq_i_bitslip_o_d12 <= ddrphy_bitslip12_o;
+ ddrphy_dq_o_data_d13 <= ddrphy_dq_o_data13;
+ case (ddrphy_bl8_chunk)
+ 1'd0: begin
+ ddrphy_dq_o_data_muxed13 <= ddrphy_dq_o_data13[3:0];
+ end
+ 1'd1: begin
+ ddrphy_dq_o_data_muxed13 <= ddrphy_dq_o_data_d13[7:4];
+ end
+ endcase
+ ddrphy_dq_i_bitslip_o_d13 <= ddrphy_bitslip13_o;
+ ddrphy_dq_o_data_d14 <= ddrphy_dq_o_data14;
+ case (ddrphy_bl8_chunk)
+ 1'd0: begin
+ ddrphy_dq_o_data_muxed14 <= ddrphy_dq_o_data14[3:0];
+ end
+ 1'd1: begin
+ ddrphy_dq_o_data_muxed14 <= ddrphy_dq_o_data_d14[7:4];
+ end
+ endcase
+ ddrphy_dq_i_bitslip_o_d14 <= ddrphy_bitslip14_o;
+ ddrphy_dq_o_data_d15 <= ddrphy_dq_o_data15;
+ case (ddrphy_bl8_chunk)
+ 1'd0: begin
+ ddrphy_dq_o_data_muxed15 <= ddrphy_dq_o_data15[3:0];
+ end
+ 1'd1: begin
+ ddrphy_dq_o_data_muxed15 <= ddrphy_dq_o_data_d15[7:4];
+ end
+ endcase
+ ddrphy_dq_i_bitslip_o_d15 <= ddrphy_bitslip15_o;
+ if ((ddrphy_dly_sel_storage[2] & ddrphy_rdly_dq_rst_re)) begin
+ ddrphy_rdly2 <= 1'd0;
+ end
+ if ((ddrphy_dly_sel_storage[2] & ddrphy_rdly_dq_inc_re)) begin
+ ddrphy_rdly2 <= (ddrphy_rdly2 + 1'd1);
+ end
+ ddrphy_burstdet_d2 <= ddrphy_burstdet2;
+ if (ddrphy_burstdet_clr_re) begin
+ ddrphy_burstdet_seen_status[2] <= 1'd0;
+ end
+ if ((ddrphy_burstdet2 & (~ddrphy_burstdet_d2))) begin
+ ddrphy_burstdet_seen_status[2] <= 1'd1;
+ end
+ ddrphy_dm_o_data_d2 <= ddrphy_dm_o_data2;
+ case (ddrphy_bl8_chunk)
+ 1'd0: begin
+ ddrphy_dm_o_data_muxed2 <= ddrphy_dm_o_data2[3:0];
+ end
+ 1'd1: begin
+ ddrphy_dm_o_data_muxed2 <= ddrphy_dm_o_data_d2[7:4];
+ end
+ endcase
+ ddrphy_dq_o_data_d16 <= ddrphy_dq_o_data16;
+ case (ddrphy_bl8_chunk)
+ 1'd0: begin
+ ddrphy_dq_o_data_muxed16 <= ddrphy_dq_o_data16[3:0];
+ end
+ 1'd1: begin
+ ddrphy_dq_o_data_muxed16 <= ddrphy_dq_o_data_d16[7:4];
+ end
+ endcase
+ ddrphy_dq_i_bitslip_o_d16 <= ddrphy_bitslip16_o;
+ ddrphy_dq_o_data_d17 <= ddrphy_dq_o_data17;
+ case (ddrphy_bl8_chunk)
+ 1'd0: begin
+ ddrphy_dq_o_data_muxed17 <= ddrphy_dq_o_data17[3:0];
+ end
+ 1'd1: begin
+ ddrphy_dq_o_data_muxed17 <= ddrphy_dq_o_data_d17[7:4];
+ end
+ endcase
+ ddrphy_dq_i_bitslip_o_d17 <= ddrphy_bitslip17_o;
+ ddrphy_dq_o_data_d18 <= ddrphy_dq_o_data18;
+ case (ddrphy_bl8_chunk)
+ 1'd0: begin
+ ddrphy_dq_o_data_muxed18 <= ddrphy_dq_o_data18[3:0];
+ end
+ 1'd1: begin
+ ddrphy_dq_o_data_muxed18 <= ddrphy_dq_o_data_d18[7:4];
+ end
+ endcase
+ ddrphy_dq_i_bitslip_o_d18 <= ddrphy_bitslip18_o;
+ ddrphy_dq_o_data_d19 <= ddrphy_dq_o_data19;
+ case (ddrphy_bl8_chunk)
+ 1'd0: begin
+ ddrphy_dq_o_data_muxed19 <= ddrphy_dq_o_data19[3:0];
+ end
+ 1'd1: begin
+ ddrphy_dq_o_data_muxed19 <= ddrphy_dq_o_data_d19[7:4];
+ end
+ endcase
+ ddrphy_dq_i_bitslip_o_d19 <= ddrphy_bitslip19_o;
+ ddrphy_dq_o_data_d20 <= ddrphy_dq_o_data20;
+ case (ddrphy_bl8_chunk)
+ 1'd0: begin
+ ddrphy_dq_o_data_muxed20 <= ddrphy_dq_o_data20[3:0];
+ end
+ 1'd1: begin
+ ddrphy_dq_o_data_muxed20 <= ddrphy_dq_o_data_d20[7:4];
+ end
+ endcase
+ ddrphy_dq_i_bitslip_o_d20 <= ddrphy_bitslip20_o;
+ ddrphy_dq_o_data_d21 <= ddrphy_dq_o_data21;
+ case (ddrphy_bl8_chunk)
+ 1'd0: begin
+ ddrphy_dq_o_data_muxed21 <= ddrphy_dq_o_data21[3:0];
+ end
+ 1'd1: begin
+ ddrphy_dq_o_data_muxed21 <= ddrphy_dq_o_data_d21[7:4];
+ end
+ endcase
+ ddrphy_dq_i_bitslip_o_d21 <= ddrphy_bitslip21_o;
+ ddrphy_dq_o_data_d22 <= ddrphy_dq_o_data22;
+ case (ddrphy_bl8_chunk)
+ 1'd0: begin
+ ddrphy_dq_o_data_muxed22 <= ddrphy_dq_o_data22[3:0];
+ end
+ 1'd1: begin
+ ddrphy_dq_o_data_muxed22 <= ddrphy_dq_o_data_d22[7:4];
+ end
+ endcase
+ ddrphy_dq_i_bitslip_o_d22 <= ddrphy_bitslip22_o;
+ ddrphy_dq_o_data_d23 <= ddrphy_dq_o_data23;
+ case (ddrphy_bl8_chunk)
+ 1'd0: begin
+ ddrphy_dq_o_data_muxed23 <= ddrphy_dq_o_data23[3:0];
+ end
+ 1'd1: begin
+ ddrphy_dq_o_data_muxed23 <= ddrphy_dq_o_data_d23[7:4];
+ end
+ endcase
+ ddrphy_dq_i_bitslip_o_d23 <= ddrphy_bitslip23_o;
+ if ((ddrphy_dly_sel_storage[3] & ddrphy_rdly_dq_rst_re)) begin
+ ddrphy_rdly3 <= 1'd0;
+ end
+ if ((ddrphy_dly_sel_storage[3] & ddrphy_rdly_dq_inc_re)) begin
+ ddrphy_rdly3 <= (ddrphy_rdly3 + 1'd1);
+ end
+ ddrphy_burstdet_d3 <= ddrphy_burstdet3;
+ if (ddrphy_burstdet_clr_re) begin
+ ddrphy_burstdet_seen_status[3] <= 1'd0;
+ end
+ if ((ddrphy_burstdet3 & (~ddrphy_burstdet_d3))) begin
+ ddrphy_burstdet_seen_status[3] <= 1'd1;
+ end
+ ddrphy_dm_o_data_d3 <= ddrphy_dm_o_data3;
+ case (ddrphy_bl8_chunk)
+ 1'd0: begin
+ ddrphy_dm_o_data_muxed3 <= ddrphy_dm_o_data3[3:0];
+ end
+ 1'd1: begin
+ ddrphy_dm_o_data_muxed3 <= ddrphy_dm_o_data_d3[7:4];
+ end
+ endcase
+ ddrphy_dq_o_data_d24 <= ddrphy_dq_o_data24;
+ case (ddrphy_bl8_chunk)
+ 1'd0: begin
+ ddrphy_dq_o_data_muxed24 <= ddrphy_dq_o_data24[3:0];
+ end
+ 1'd1: begin
+ ddrphy_dq_o_data_muxed24 <= ddrphy_dq_o_data_d24[7:4];
+ end
+ endcase
+ ddrphy_dq_i_bitslip_o_d24 <= ddrphy_bitslip24_o;
+ ddrphy_dq_o_data_d25 <= ddrphy_dq_o_data25;
+ case (ddrphy_bl8_chunk)
+ 1'd0: begin
+ ddrphy_dq_o_data_muxed25 <= ddrphy_dq_o_data25[3:0];
+ end
+ 1'd1: begin
+ ddrphy_dq_o_data_muxed25 <= ddrphy_dq_o_data_d25[7:4];
+ end
+ endcase
+ ddrphy_dq_i_bitslip_o_d25 <= ddrphy_bitslip25_o;
+ ddrphy_dq_o_data_d26 <= ddrphy_dq_o_data26;
+ case (ddrphy_bl8_chunk)
+ 1'd0: begin
+ ddrphy_dq_o_data_muxed26 <= ddrphy_dq_o_data26[3:0];
+ end
+ 1'd1: begin
+ ddrphy_dq_o_data_muxed26 <= ddrphy_dq_o_data_d26[7:4];
+ end
+ endcase
+ ddrphy_dq_i_bitslip_o_d26 <= ddrphy_bitslip26_o;
+ ddrphy_dq_o_data_d27 <= ddrphy_dq_o_data27;
+ case (ddrphy_bl8_chunk)
+ 1'd0: begin
+ ddrphy_dq_o_data_muxed27 <= ddrphy_dq_o_data27[3:0];
+ end
+ 1'd1: begin
+ ddrphy_dq_o_data_muxed27 <= ddrphy_dq_o_data_d27[7:4];
+ end
+ endcase
+ ddrphy_dq_i_bitslip_o_d27 <= ddrphy_bitslip27_o;
+ ddrphy_dq_o_data_d28 <= ddrphy_dq_o_data28;
+ case (ddrphy_bl8_chunk)
+ 1'd0: begin
+ ddrphy_dq_o_data_muxed28 <= ddrphy_dq_o_data28[3:0];
+ end
+ 1'd1: begin
+ ddrphy_dq_o_data_muxed28 <= ddrphy_dq_o_data_d28[7:4];
+ end
+ endcase
+ ddrphy_dq_i_bitslip_o_d28 <= ddrphy_bitslip28_o;
+ ddrphy_dq_o_data_d29 <= ddrphy_dq_o_data29;
+ case (ddrphy_bl8_chunk)
+ 1'd0: begin
+ ddrphy_dq_o_data_muxed29 <= ddrphy_dq_o_data29[3:0];
+ end
+ 1'd1: begin
+ ddrphy_dq_o_data_muxed29 <= ddrphy_dq_o_data_d29[7:4];
+ end
+ endcase
+ ddrphy_dq_i_bitslip_o_d29 <= ddrphy_bitslip29_o;
+ ddrphy_dq_o_data_d30 <= ddrphy_dq_o_data30;
+ case (ddrphy_bl8_chunk)
+ 1'd0: begin
+ ddrphy_dq_o_data_muxed30 <= ddrphy_dq_o_data30[3:0];
+ end
+ 1'd1: begin
+ ddrphy_dq_o_data_muxed30 <= ddrphy_dq_o_data_d30[7:4];
+ end
+ endcase
+ ddrphy_dq_i_bitslip_o_d30 <= ddrphy_bitslip30_o;
+ ddrphy_dq_o_data_d31 <= ddrphy_dq_o_data31;
+ case (ddrphy_bl8_chunk)
+ 1'd0: begin
+ ddrphy_dq_o_data_muxed31 <= ddrphy_dq_o_data31[3:0];
+ end
+ 1'd1: begin
+ ddrphy_dq_o_data_muxed31 <= ddrphy_dq_o_data_d31[7:4];
+ end
+ endcase
+ ddrphy_dq_i_bitslip_o_d31 <= ddrphy_bitslip31_o;
+ if ((ddrphy_dly_sel_storage[0] & ddrphy_rdly_dq_bitslip_re)) begin
+ ddrphy_bitslip0_value <= (ddrphy_bitslip0_value + 1'd1);
+ end
+ if ((ddrphy_dly_sel_storage[0] & ddrphy_rdly_dq_bitslip_rst_re)) begin
+ ddrphy_bitslip0_value <= 1'd0;
+ end
+ ddrphy_bitslip0_r <= {ddrphy_bitslip0_i, ddrphy_bitslip0_r[7:4]};
+ if ((ddrphy_dly_sel_storage[0] & ddrphy_rdly_dq_bitslip_re)) begin
+ ddrphy_bitslip1_value <= (ddrphy_bitslip1_value + 1'd1);
+ end
+ if ((ddrphy_dly_sel_storage[0] & ddrphy_rdly_dq_bitslip_rst_re)) begin
+ ddrphy_bitslip1_value <= 1'd0;
+ end
+ ddrphy_bitslip1_r <= {ddrphy_bitslip1_i, ddrphy_bitslip1_r[7:4]};
+ if ((ddrphy_dly_sel_storage[0] & ddrphy_rdly_dq_bitslip_re)) begin
+ ddrphy_bitslip2_value <= (ddrphy_bitslip2_value + 1'd1);
+ end
+ if ((ddrphy_dly_sel_storage[0] & ddrphy_rdly_dq_bitslip_rst_re)) begin
+ ddrphy_bitslip2_value <= 1'd0;
+ end
+ ddrphy_bitslip2_r <= {ddrphy_bitslip2_i, ddrphy_bitslip2_r[7:4]};
+ if ((ddrphy_dly_sel_storage[0] & ddrphy_rdly_dq_bitslip_re)) begin
+ ddrphy_bitslip3_value <= (ddrphy_bitslip3_value + 1'd1);
+ end
+ if ((ddrphy_dly_sel_storage[0] & ddrphy_rdly_dq_bitslip_rst_re)) begin
+ ddrphy_bitslip3_value <= 1'd0;
+ end
+ ddrphy_bitslip3_r <= {ddrphy_bitslip3_i, ddrphy_bitslip3_r[7:4]};
+ if ((ddrphy_dly_sel_storage[0] & ddrphy_rdly_dq_bitslip_re)) begin
+ ddrphy_bitslip4_value <= (ddrphy_bitslip4_value + 1'd1);
+ end
+ if ((ddrphy_dly_sel_storage[0] & ddrphy_rdly_dq_bitslip_rst_re)) begin
+ ddrphy_bitslip4_value <= 1'd0;
+ end
+ ddrphy_bitslip4_r <= {ddrphy_bitslip4_i, ddrphy_bitslip4_r[7:4]};
+ if ((ddrphy_dly_sel_storage[0] & ddrphy_rdly_dq_bitslip_re)) begin
+ ddrphy_bitslip5_value <= (ddrphy_bitslip5_value + 1'd1);
+ end
+ if ((ddrphy_dly_sel_storage[0] & ddrphy_rdly_dq_bitslip_rst_re)) begin
+ ddrphy_bitslip5_value <= 1'd0;
+ end
+ ddrphy_bitslip5_r <= {ddrphy_bitslip5_i, ddrphy_bitslip5_r[7:4]};
+ if ((ddrphy_dly_sel_storage[0] & ddrphy_rdly_dq_bitslip_re)) begin
+ ddrphy_bitslip6_value <= (ddrphy_bitslip6_value + 1'd1);
+ end
+ if ((ddrphy_dly_sel_storage[0] & ddrphy_rdly_dq_bitslip_rst_re)) begin
+ ddrphy_bitslip6_value <= 1'd0;
+ end
+ ddrphy_bitslip6_r <= {ddrphy_bitslip6_i, ddrphy_bitslip6_r[7:4]};
+ if ((ddrphy_dly_sel_storage[0] & ddrphy_rdly_dq_bitslip_re)) begin
+ ddrphy_bitslip7_value <= (ddrphy_bitslip7_value + 1'd1);
+ end
+ if ((ddrphy_dly_sel_storage[0] & ddrphy_rdly_dq_bitslip_rst_re)) begin
+ ddrphy_bitslip7_value <= 1'd0;
+ end
+ ddrphy_bitslip7_r <= {ddrphy_bitslip7_i, ddrphy_bitslip7_r[7:4]};
+ if ((ddrphy_dly_sel_storage[1] & ddrphy_rdly_dq_bitslip_re)) begin
+ ddrphy_bitslip8_value <= (ddrphy_bitslip8_value + 1'd1);
+ end
+ if ((ddrphy_dly_sel_storage[1] & ddrphy_rdly_dq_bitslip_rst_re)) begin
+ ddrphy_bitslip8_value <= 1'd0;
+ end
+ ddrphy_bitslip8_r <= {ddrphy_bitslip8_i, ddrphy_bitslip8_r[7:4]};
+ if ((ddrphy_dly_sel_storage[1] & ddrphy_rdly_dq_bitslip_re)) begin
+ ddrphy_bitslip9_value <= (ddrphy_bitslip9_value + 1'd1);
+ end
+ if ((ddrphy_dly_sel_storage[1] & ddrphy_rdly_dq_bitslip_rst_re)) begin
+ ddrphy_bitslip9_value <= 1'd0;
+ end
+ ddrphy_bitslip9_r <= {ddrphy_bitslip9_i, ddrphy_bitslip9_r[7:4]};
+ if ((ddrphy_dly_sel_storage[1] & ddrphy_rdly_dq_bitslip_re)) begin
+ ddrphy_bitslip10_value <= (ddrphy_bitslip10_value + 1'd1);
+ end
+ if ((ddrphy_dly_sel_storage[1] & ddrphy_rdly_dq_bitslip_rst_re)) begin
+ ddrphy_bitslip10_value <= 1'd0;
+ end
+ ddrphy_bitslip10_r <= {ddrphy_bitslip10_i, ddrphy_bitslip10_r[7:4]};
+ if ((ddrphy_dly_sel_storage[1] & ddrphy_rdly_dq_bitslip_re)) begin
+ ddrphy_bitslip11_value <= (ddrphy_bitslip11_value + 1'd1);
+ end
+ if ((ddrphy_dly_sel_storage[1] & ddrphy_rdly_dq_bitslip_rst_re)) begin
+ ddrphy_bitslip11_value <= 1'd0;
+ end
+ ddrphy_bitslip11_r <= {ddrphy_bitslip11_i, ddrphy_bitslip11_r[7:4]};
+ if ((ddrphy_dly_sel_storage[1] & ddrphy_rdly_dq_bitslip_re)) begin
+ ddrphy_bitslip12_value <= (ddrphy_bitslip12_value + 1'd1);
+ end
+ if ((ddrphy_dly_sel_storage[1] & ddrphy_rdly_dq_bitslip_rst_re)) begin
+ ddrphy_bitslip12_value <= 1'd0;
+ end
+ ddrphy_bitslip12_r <= {ddrphy_bitslip12_i, ddrphy_bitslip12_r[7:4]};
+ if ((ddrphy_dly_sel_storage[1] & ddrphy_rdly_dq_bitslip_re)) begin
+ ddrphy_bitslip13_value <= (ddrphy_bitslip13_value + 1'd1);
+ end
+ if ((ddrphy_dly_sel_storage[1] & ddrphy_rdly_dq_bitslip_rst_re)) begin
+ ddrphy_bitslip13_value <= 1'd0;
+ end
+ ddrphy_bitslip13_r <= {ddrphy_bitslip13_i, ddrphy_bitslip13_r[7:4]};
+ if ((ddrphy_dly_sel_storage[1] & ddrphy_rdly_dq_bitslip_re)) begin
+ ddrphy_bitslip14_value <= (ddrphy_bitslip14_value + 1'd1);
+ end
+ if ((ddrphy_dly_sel_storage[1] & ddrphy_rdly_dq_bitslip_rst_re)) begin
+ ddrphy_bitslip14_value <= 1'd0;
+ end
+ ddrphy_bitslip14_r <= {ddrphy_bitslip14_i, ddrphy_bitslip14_r[7:4]};
+ if ((ddrphy_dly_sel_storage[1] & ddrphy_rdly_dq_bitslip_re)) begin
+ ddrphy_bitslip15_value <= (ddrphy_bitslip15_value + 1'd1);
+ end
+ if ((ddrphy_dly_sel_storage[1] & ddrphy_rdly_dq_bitslip_rst_re)) begin
+ ddrphy_bitslip15_value <= 1'd0;
+ end
+ ddrphy_bitslip15_r <= {ddrphy_bitslip15_i, ddrphy_bitslip15_r[7:4]};
+ if ((ddrphy_dly_sel_storage[2] & ddrphy_rdly_dq_bitslip_re)) begin
+ ddrphy_bitslip16_value <= (ddrphy_bitslip16_value + 1'd1);
+ end
+ if ((ddrphy_dly_sel_storage[2] & ddrphy_rdly_dq_bitslip_rst_re)) begin
+ ddrphy_bitslip16_value <= 1'd0;
+ end
+ ddrphy_bitslip16_r <= {ddrphy_bitslip16_i, ddrphy_bitslip16_r[7:4]};
+ if ((ddrphy_dly_sel_storage[2] & ddrphy_rdly_dq_bitslip_re)) begin
+ ddrphy_bitslip17_value <= (ddrphy_bitslip17_value + 1'd1);
+ end
+ if ((ddrphy_dly_sel_storage[2] & ddrphy_rdly_dq_bitslip_rst_re)) begin
+ ddrphy_bitslip17_value <= 1'd0;
+ end
+ ddrphy_bitslip17_r <= {ddrphy_bitslip17_i, ddrphy_bitslip17_r[7:4]};
+ if ((ddrphy_dly_sel_storage[2] & ddrphy_rdly_dq_bitslip_re)) begin
+ ddrphy_bitslip18_value <= (ddrphy_bitslip18_value + 1'd1);
+ end
+ if ((ddrphy_dly_sel_storage[2] & ddrphy_rdly_dq_bitslip_rst_re)) begin
+ ddrphy_bitslip18_value <= 1'd0;
+ end
+ ddrphy_bitslip18_r <= {ddrphy_bitslip18_i, ddrphy_bitslip18_r[7:4]};
+ if ((ddrphy_dly_sel_storage[2] & ddrphy_rdly_dq_bitslip_re)) begin
+ ddrphy_bitslip19_value <= (ddrphy_bitslip19_value + 1'd1);
+ end
+ if ((ddrphy_dly_sel_storage[2] & ddrphy_rdly_dq_bitslip_rst_re)) begin
+ ddrphy_bitslip19_value <= 1'd0;
+ end
+ ddrphy_bitslip19_r <= {ddrphy_bitslip19_i, ddrphy_bitslip19_r[7:4]};
+ if ((ddrphy_dly_sel_storage[2] & ddrphy_rdly_dq_bitslip_re)) begin
+ ddrphy_bitslip20_value <= (ddrphy_bitslip20_value + 1'd1);
+ end
+ if ((ddrphy_dly_sel_storage[2] & ddrphy_rdly_dq_bitslip_rst_re)) begin
+ ddrphy_bitslip20_value <= 1'd0;
+ end
+ ddrphy_bitslip20_r <= {ddrphy_bitslip20_i, ddrphy_bitslip20_r[7:4]};
+ if ((ddrphy_dly_sel_storage[2] & ddrphy_rdly_dq_bitslip_re)) begin
+ ddrphy_bitslip21_value <= (ddrphy_bitslip21_value + 1'd1);
+ end
+ if ((ddrphy_dly_sel_storage[2] & ddrphy_rdly_dq_bitslip_rst_re)) begin
+ ddrphy_bitslip21_value <= 1'd0;
+ end
+ ddrphy_bitslip21_r <= {ddrphy_bitslip21_i, ddrphy_bitslip21_r[7:4]};
+ if ((ddrphy_dly_sel_storage[2] & ddrphy_rdly_dq_bitslip_re)) begin
+ ddrphy_bitslip22_value <= (ddrphy_bitslip22_value + 1'd1);
+ end
+ if ((ddrphy_dly_sel_storage[2] & ddrphy_rdly_dq_bitslip_rst_re)) begin
+ ddrphy_bitslip22_value <= 1'd0;
+ end
+ ddrphy_bitslip22_r <= {ddrphy_bitslip22_i, ddrphy_bitslip22_r[7:4]};
+ if ((ddrphy_dly_sel_storage[2] & ddrphy_rdly_dq_bitslip_re)) begin
+ ddrphy_bitslip23_value <= (ddrphy_bitslip23_value + 1'd1);
+ end
+ if ((ddrphy_dly_sel_storage[2] & ddrphy_rdly_dq_bitslip_rst_re)) begin
+ ddrphy_bitslip23_value <= 1'd0;
+ end
+ ddrphy_bitslip23_r <= {ddrphy_bitslip23_i, ddrphy_bitslip23_r[7:4]};
+ if ((ddrphy_dly_sel_storage[3] & ddrphy_rdly_dq_bitslip_re)) begin
+ ddrphy_bitslip24_value <= (ddrphy_bitslip24_value + 1'd1);
+ end
+ if ((ddrphy_dly_sel_storage[3] & ddrphy_rdly_dq_bitslip_rst_re)) begin
+ ddrphy_bitslip24_value <= 1'd0;
+ end
+ ddrphy_bitslip24_r <= {ddrphy_bitslip24_i, ddrphy_bitslip24_r[7:4]};
+ if ((ddrphy_dly_sel_storage[3] & ddrphy_rdly_dq_bitslip_re)) begin
+ ddrphy_bitslip25_value <= (ddrphy_bitslip25_value + 1'd1);
+ end
+ if ((ddrphy_dly_sel_storage[3] & ddrphy_rdly_dq_bitslip_rst_re)) begin
+ ddrphy_bitslip25_value <= 1'd0;
+ end
+ ddrphy_bitslip25_r <= {ddrphy_bitslip25_i, ddrphy_bitslip25_r[7:4]};
+ if ((ddrphy_dly_sel_storage[3] & ddrphy_rdly_dq_bitslip_re)) begin
+ ddrphy_bitslip26_value <= (ddrphy_bitslip26_value + 1'd1);
+ end
+ if ((ddrphy_dly_sel_storage[3] & ddrphy_rdly_dq_bitslip_rst_re)) begin
+ ddrphy_bitslip26_value <= 1'd0;
+ end
+ ddrphy_bitslip26_r <= {ddrphy_bitslip26_i, ddrphy_bitslip26_r[7:4]};
+ if ((ddrphy_dly_sel_storage[3] & ddrphy_rdly_dq_bitslip_re)) begin
+ ddrphy_bitslip27_value <= (ddrphy_bitslip27_value + 1'd1);
+ end
+ if ((ddrphy_dly_sel_storage[3] & ddrphy_rdly_dq_bitslip_rst_re)) begin
+ ddrphy_bitslip27_value <= 1'd0;
+ end
+ ddrphy_bitslip27_r <= {ddrphy_bitslip27_i, ddrphy_bitslip27_r[7:4]};
+ if ((ddrphy_dly_sel_storage[3] & ddrphy_rdly_dq_bitslip_re)) begin
+ ddrphy_bitslip28_value <= (ddrphy_bitslip28_value + 1'd1);
+ end
+ if ((ddrphy_dly_sel_storage[3] & ddrphy_rdly_dq_bitslip_rst_re)) begin
+ ddrphy_bitslip28_value <= 1'd0;
+ end
+ ddrphy_bitslip28_r <= {ddrphy_bitslip28_i, ddrphy_bitslip28_r[7:4]};
+ if ((ddrphy_dly_sel_storage[3] & ddrphy_rdly_dq_bitslip_re)) begin
+ ddrphy_bitslip29_value <= (ddrphy_bitslip29_value + 1'd1);
+ end
+ if ((ddrphy_dly_sel_storage[3] & ddrphy_rdly_dq_bitslip_rst_re)) begin
+ ddrphy_bitslip29_value <= 1'd0;
+ end
+ ddrphy_bitslip29_r <= {ddrphy_bitslip29_i, ddrphy_bitslip29_r[7:4]};
+ if ((ddrphy_dly_sel_storage[3] & ddrphy_rdly_dq_bitslip_re)) begin
+ ddrphy_bitslip30_value <= (ddrphy_bitslip30_value + 1'd1);
+ end
+ if ((ddrphy_dly_sel_storage[3] & ddrphy_rdly_dq_bitslip_rst_re)) begin
+ ddrphy_bitslip30_value <= 1'd0;
+ end
+ ddrphy_bitslip30_r <= {ddrphy_bitslip30_i, ddrphy_bitslip30_r[7:4]};
+ if ((ddrphy_dly_sel_storage[3] & ddrphy_rdly_dq_bitslip_re)) begin
+ ddrphy_bitslip31_value <= (ddrphy_bitslip31_value + 1'd1);
+ end
+ if ((ddrphy_dly_sel_storage[3] & ddrphy_rdly_dq_bitslip_rst_re)) begin
+ ddrphy_bitslip31_value <= 1'd0;
+ end
+ ddrphy_bitslip31_r <= {ddrphy_bitslip31_i, ddrphy_bitslip31_r[7:4]};
+ ddrphy_rddata_en_tappeddelayline0 <= (ddrphy_dfi_p0_rddata_en | ddrphy_dfi_p1_rddata_en);
+ ddrphy_rddata_en_tappeddelayline1 <= ddrphy_rddata_en_tappeddelayline0;
+ ddrphy_rddata_en_tappeddelayline2 <= ddrphy_rddata_en_tappeddelayline1;
+ ddrphy_rddata_en_tappeddelayline3 <= ddrphy_rddata_en_tappeddelayline2;
+ ddrphy_rddata_en_tappeddelayline4 <= ddrphy_rddata_en_tappeddelayline3;
+ ddrphy_rddata_en_tappeddelayline5 <= ddrphy_rddata_en_tappeddelayline4;
+ ddrphy_rddata_en_tappeddelayline6 <= ddrphy_rddata_en_tappeddelayline5;
+ ddrphy_rddata_en_tappeddelayline7 <= ddrphy_rddata_en_tappeddelayline6;
+ ddrphy_rddata_en_tappeddelayline8 <= ddrphy_rddata_en_tappeddelayline7;
+ ddrphy_rddata_en_tappeddelayline9 <= ddrphy_rddata_en_tappeddelayline8;
+ ddrphy_rddata_en_tappeddelayline10 <= ddrphy_rddata_en_tappeddelayline9;
+ ddrphy_rddata_en_tappeddelayline11 <= ddrphy_rddata_en_tappeddelayline10;
+ ddrphy_rddata_en_tappeddelayline12 <= ddrphy_rddata_en_tappeddelayline11;
+ ddrphy_wrdata_en_tappeddelayline0 <= (ddrphy_dfi_p0_wrdata_en | ddrphy_dfi_p1_wrdata_en);
+ ddrphy_wrdata_en_tappeddelayline1 <= ddrphy_wrdata_en_tappeddelayline0;
+ ddrphy_wrdata_en_tappeddelayline2 <= ddrphy_wrdata_en_tappeddelayline1;
+ ddrphy_wrdata_en_tappeddelayline3 <= ddrphy_wrdata_en_tappeddelayline2;
+ ddrphy_wrdata_en_tappeddelayline4 <= ddrphy_wrdata_en_tappeddelayline3;
+ ddrphy_wrdata_en_tappeddelayline5 <= ddrphy_wrdata_en_tappeddelayline4;
+ ddrphy_wrdata_en_tappeddelayline6 <= ddrphy_wrdata_en_tappeddelayline5;
+ if (litedramcore_inti_p0_rddata_valid) begin
+ litedramcore_phaseinjector0_rddata_status <= litedramcore_inti_p0_rddata;
+ end
+ if (litedramcore_inti_p1_rddata_valid) begin
+ litedramcore_phaseinjector1_rddata_status <= litedramcore_inti_p1_rddata;
+ end
+ if ((litedramcore_timer_wait & (~litedramcore_timer_done0))) begin
+ litedramcore_timer_count1 <= (litedramcore_timer_count1 - 1'd1);
+ end else begin
+ litedramcore_timer_count1 <= 9'd374;
+ end
+ litedramcore_postponer_req_o <= 1'd0;
+ if (litedramcore_postponer_req_i) begin
+ litedramcore_postponer_count <= (litedramcore_postponer_count - 1'd1);
+ if ((litedramcore_postponer_count == 1'd0)) begin
+ litedramcore_postponer_count <= 1'd0;
+ litedramcore_postponer_req_o <= 1'd1;
+ end
+ end
+ if (litedramcore_sequencer_start0) begin
+ litedramcore_sequencer_count <= 1'd0;
+ end else begin
+ if (litedramcore_sequencer_done1) begin
+ if ((litedramcore_sequencer_count != 1'd0)) begin
+ litedramcore_sequencer_count <= (litedramcore_sequencer_count - 1'd1);
+ end
+ end
+ end
+ litedramcore_cmd_payload_a <= 1'd0;
+ litedramcore_cmd_payload_ba <= 1'd0;
+ litedramcore_cmd_payload_cas <= 1'd0;
+ litedramcore_cmd_payload_ras <= 1'd0;
+ litedramcore_cmd_payload_we <= 1'd0;
+ litedramcore_sequencer_done1 <= 1'd0;
+ if ((litedramcore_sequencer_start1 & (litedramcore_sequencer_counter == 1'd0))) begin
+ litedramcore_cmd_payload_a <= 11'd1024;
+ litedramcore_cmd_payload_ba <= 1'd0;
+ litedramcore_cmd_payload_cas <= 1'd0;
+ litedramcore_cmd_payload_ras <= 1'd1;
+ litedramcore_cmd_payload_we <= 1'd1;
+ end
+ if ((litedramcore_sequencer_counter == 2'd2)) begin
+ litedramcore_cmd_payload_a <= 11'd1024;
+ litedramcore_cmd_payload_ba <= 1'd0;
+ litedramcore_cmd_payload_cas <= 1'd1;
+ litedramcore_cmd_payload_ras <= 1'd1;
+ litedramcore_cmd_payload_we <= 1'd0;
+ end
+ if ((litedramcore_sequencer_counter == 7'd106)) begin
+ litedramcore_cmd_payload_a <= 1'd0;
+ litedramcore_cmd_payload_ba <= 1'd0;
+ litedramcore_cmd_payload_cas <= 1'd0;
+ litedramcore_cmd_payload_ras <= 1'd0;
+ litedramcore_cmd_payload_we <= 1'd0;
+ litedramcore_sequencer_done1 <= 1'd1;
+ end
+ if ((litedramcore_sequencer_counter == 7'd106)) begin
+ litedramcore_sequencer_counter <= 1'd0;
+ end else begin
+ if ((litedramcore_sequencer_counter != 1'd0)) begin
+ litedramcore_sequencer_counter <= (litedramcore_sequencer_counter + 1'd1);
+ end else begin
+ if (litedramcore_sequencer_start1) begin
+ litedramcore_sequencer_counter <= 1'd1;
+ end
+ end
+ end
+ if ((litedramcore_zqcs_timer_wait & (~litedramcore_zqcs_timer_done0))) begin
+ litedramcore_zqcs_timer_count1 <= (litedramcore_zqcs_timer_count1 - 1'd1);
+ end else begin
+ litedramcore_zqcs_timer_count1 <= 26'd47999999;
+ end
+ litedramcore_zqcs_executer_done <= 1'd0;
+ if ((litedramcore_zqcs_executer_start & (litedramcore_zqcs_executer_counter == 1'd0))) begin
+ litedramcore_cmd_payload_a <= 11'd1024;
+ litedramcore_cmd_payload_ba <= 1'd0;
+ litedramcore_cmd_payload_cas <= 1'd0;
+ litedramcore_cmd_payload_ras <= 1'd1;
+ litedramcore_cmd_payload_we <= 1'd1;
+ end
+ if ((litedramcore_zqcs_executer_counter == 2'd2)) begin
+ litedramcore_cmd_payload_a <= 1'd0;
+ litedramcore_cmd_payload_ba <= 1'd0;
+ litedramcore_cmd_payload_cas <= 1'd0;
+ litedramcore_cmd_payload_ras <= 1'd0;
+ litedramcore_cmd_payload_we <= 1'd1;
+ end
+ if ((litedramcore_zqcs_executer_counter == 6'd34)) begin
+ litedramcore_cmd_payload_a <= 1'd0;
+ litedramcore_cmd_payload_ba <= 1'd0;
+ litedramcore_cmd_payload_cas <= 1'd0;
+ litedramcore_cmd_payload_ras <= 1'd0;
+ litedramcore_cmd_payload_we <= 1'd0;
+ litedramcore_zqcs_executer_done <= 1'd1;
+ end
+ if ((litedramcore_zqcs_executer_counter == 6'd34)) begin
+ litedramcore_zqcs_executer_counter <= 1'd0;
+ end else begin
+ if ((litedramcore_zqcs_executer_counter != 1'd0)) begin
+ litedramcore_zqcs_executer_counter <= (litedramcore_zqcs_executer_counter + 1'd1);
+ end else begin
+ if (litedramcore_zqcs_executer_start) begin
+ litedramcore_zqcs_executer_counter <= 1'd1;
+ end
+ end
+ end
+ litedramcore_refresher_state <= litedramcore_refresher_next_state;
+ if (litedramcore_bankmachine0_row_close) begin
+ litedramcore_bankmachine0_row_opened <= 1'd0;
+ end else begin
+ if (litedramcore_bankmachine0_row_open) begin
+ litedramcore_bankmachine0_row_opened <= 1'd1;
+ litedramcore_bankmachine0_row <= litedramcore_bankmachine0_cmd_buffer_source_payload_addr[21:7];
+ end
+ end
+ if (((litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable) & (~litedramcore_bankmachine0_cmd_buffer_lookahead_replace))) begin
+ litedramcore_bankmachine0_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine0_cmd_buffer_lookahead_produce + 1'd1);
+ end
+ if (litedramcore_bankmachine0_cmd_buffer_lookahead_do_read) begin
+ litedramcore_bankmachine0_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine0_cmd_buffer_lookahead_consume + 1'd1);
+ end
+ if (((litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable) & (~litedramcore_bankmachine0_cmd_buffer_lookahead_replace))) begin
+ if ((~litedramcore_bankmachine0_cmd_buffer_lookahead_do_read)) begin
+ litedramcore_bankmachine0_cmd_buffer_lookahead_level <= (litedramcore_bankmachine0_cmd_buffer_lookahead_level + 1'd1);
+ end
+ end else begin
+ if (litedramcore_bankmachine0_cmd_buffer_lookahead_do_read) begin
+ litedramcore_bankmachine0_cmd_buffer_lookahead_level <= (litedramcore_bankmachine0_cmd_buffer_lookahead_level - 1'd1);
+ end
+ end
+ if (((~litedramcore_bankmachine0_cmd_buffer_source_valid) | litedramcore_bankmachine0_cmd_buffer_source_ready)) begin
+ litedramcore_bankmachine0_cmd_buffer_source_valid <= litedramcore_bankmachine0_cmd_buffer_sink_valid;
+ litedramcore_bankmachine0_cmd_buffer_source_first <= litedramcore_bankmachine0_cmd_buffer_sink_first;
+ litedramcore_bankmachine0_cmd_buffer_source_last <= litedramcore_bankmachine0_cmd_buffer_sink_last;
+ litedramcore_bankmachine0_cmd_buffer_source_payload_we <= litedramcore_bankmachine0_cmd_buffer_sink_payload_we;
+ litedramcore_bankmachine0_cmd_buffer_source_payload_addr <= litedramcore_bankmachine0_cmd_buffer_sink_payload_addr;
+ end
+ if (litedramcore_bankmachine0_twtpcon_valid) begin
+ litedramcore_bankmachine0_twtpcon_count <= 3'd6;
+ if (1'd0) begin
+ litedramcore_bankmachine0_twtpcon_ready <= 1'd1;
+ end else begin
+ litedramcore_bankmachine0_twtpcon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~litedramcore_bankmachine0_twtpcon_ready)) begin
+ litedramcore_bankmachine0_twtpcon_count <= (litedramcore_bankmachine0_twtpcon_count - 1'd1);
+ if ((litedramcore_bankmachine0_twtpcon_count == 1'd1)) begin
+ litedramcore_bankmachine0_twtpcon_ready <= 1'd1;
+ end
+ end
+ end
+ if (litedramcore_bankmachine0_trccon_valid) begin
+ litedramcore_bankmachine0_trccon_count <= 2'd2;
+ if (1'd0) begin
+ litedramcore_bankmachine0_trccon_ready <= 1'd1;
+ end else begin
+ litedramcore_bankmachine0_trccon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~litedramcore_bankmachine0_trccon_ready)) begin
+ litedramcore_bankmachine0_trccon_count <= (litedramcore_bankmachine0_trccon_count - 1'd1);
+ if ((litedramcore_bankmachine0_trccon_count == 1'd1)) begin
+ litedramcore_bankmachine0_trccon_ready <= 1'd1;
+ end
+ end
+ end
+ if (litedramcore_bankmachine0_trascon_valid) begin
+ litedramcore_bankmachine0_trascon_count <= 2'd2;
+ if (1'd0) begin
+ litedramcore_bankmachine0_trascon_ready <= 1'd1;
+ end else begin
+ litedramcore_bankmachine0_trascon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~litedramcore_bankmachine0_trascon_ready)) begin
+ litedramcore_bankmachine0_trascon_count <= (litedramcore_bankmachine0_trascon_count - 1'd1);
+ if ((litedramcore_bankmachine0_trascon_count == 1'd1)) begin
+ litedramcore_bankmachine0_trascon_ready <= 1'd1;
+ end
+ end
+ end
+ litedramcore_bankmachine0_state <= litedramcore_bankmachine0_next_state;
+ if (litedramcore_bankmachine1_row_close) begin
+ litedramcore_bankmachine1_row_opened <= 1'd0;
+ end else begin
+ if (litedramcore_bankmachine1_row_open) begin
+ litedramcore_bankmachine1_row_opened <= 1'd1;
+ litedramcore_bankmachine1_row <= litedramcore_bankmachine1_cmd_buffer_source_payload_addr[21:7];
+ end
+ end
+ if (((litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable) & (~litedramcore_bankmachine1_cmd_buffer_lookahead_replace))) begin
+ litedramcore_bankmachine1_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine1_cmd_buffer_lookahead_produce + 1'd1);
+ end
+ if (litedramcore_bankmachine1_cmd_buffer_lookahead_do_read) begin
+ litedramcore_bankmachine1_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine1_cmd_buffer_lookahead_consume + 1'd1);
+ end
+ if (((litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable) & (~litedramcore_bankmachine1_cmd_buffer_lookahead_replace))) begin
+ if ((~litedramcore_bankmachine1_cmd_buffer_lookahead_do_read)) begin
+ litedramcore_bankmachine1_cmd_buffer_lookahead_level <= (litedramcore_bankmachine1_cmd_buffer_lookahead_level + 1'd1);
+ end
+ end else begin
+ if (litedramcore_bankmachine1_cmd_buffer_lookahead_do_read) begin
+ litedramcore_bankmachine1_cmd_buffer_lookahead_level <= (litedramcore_bankmachine1_cmd_buffer_lookahead_level - 1'd1);
+ end
+ end
+ if (((~litedramcore_bankmachine1_cmd_buffer_source_valid) | litedramcore_bankmachine1_cmd_buffer_source_ready)) begin
+ litedramcore_bankmachine1_cmd_buffer_source_valid <= litedramcore_bankmachine1_cmd_buffer_sink_valid;
+ litedramcore_bankmachine1_cmd_buffer_source_first <= litedramcore_bankmachine1_cmd_buffer_sink_first;
+ litedramcore_bankmachine1_cmd_buffer_source_last <= litedramcore_bankmachine1_cmd_buffer_sink_last;
+ litedramcore_bankmachine1_cmd_buffer_source_payload_we <= litedramcore_bankmachine1_cmd_buffer_sink_payload_we;
+ litedramcore_bankmachine1_cmd_buffer_source_payload_addr <= litedramcore_bankmachine1_cmd_buffer_sink_payload_addr;
+ end
+ if (litedramcore_bankmachine1_twtpcon_valid) begin
+ litedramcore_bankmachine1_twtpcon_count <= 3'd6;
+ if (1'd0) begin
+ litedramcore_bankmachine1_twtpcon_ready <= 1'd1;
+ end else begin
+ litedramcore_bankmachine1_twtpcon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~litedramcore_bankmachine1_twtpcon_ready)) begin
+ litedramcore_bankmachine1_twtpcon_count <= (litedramcore_bankmachine1_twtpcon_count - 1'd1);
+ if ((litedramcore_bankmachine1_twtpcon_count == 1'd1)) begin
+ litedramcore_bankmachine1_twtpcon_ready <= 1'd1;
+ end
+ end
+ end
+ if (litedramcore_bankmachine1_trccon_valid) begin
+ litedramcore_bankmachine1_trccon_count <= 2'd2;
+ if (1'd0) begin
+ litedramcore_bankmachine1_trccon_ready <= 1'd1;
+ end else begin
+ litedramcore_bankmachine1_trccon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~litedramcore_bankmachine1_trccon_ready)) begin
+ litedramcore_bankmachine1_trccon_count <= (litedramcore_bankmachine1_trccon_count - 1'd1);
+ if ((litedramcore_bankmachine1_trccon_count == 1'd1)) begin
+ litedramcore_bankmachine1_trccon_ready <= 1'd1;
+ end
+ end
+ end
+ if (litedramcore_bankmachine1_trascon_valid) begin
+ litedramcore_bankmachine1_trascon_count <= 2'd2;
+ if (1'd0) begin
+ litedramcore_bankmachine1_trascon_ready <= 1'd1;
+ end else begin
+ litedramcore_bankmachine1_trascon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~litedramcore_bankmachine1_trascon_ready)) begin
+ litedramcore_bankmachine1_trascon_count <= (litedramcore_bankmachine1_trascon_count - 1'd1);
+ if ((litedramcore_bankmachine1_trascon_count == 1'd1)) begin
+ litedramcore_bankmachine1_trascon_ready <= 1'd1;
+ end
+ end
+ end
+ litedramcore_bankmachine1_state <= litedramcore_bankmachine1_next_state;
+ if (litedramcore_bankmachine2_row_close) begin
+ litedramcore_bankmachine2_row_opened <= 1'd0;
+ end else begin
+ if (litedramcore_bankmachine2_row_open) begin
+ litedramcore_bankmachine2_row_opened <= 1'd1;
+ litedramcore_bankmachine2_row <= litedramcore_bankmachine2_cmd_buffer_source_payload_addr[21:7];
+ end
+ end
+ if (((litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable) & (~litedramcore_bankmachine2_cmd_buffer_lookahead_replace))) begin
+ litedramcore_bankmachine2_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine2_cmd_buffer_lookahead_produce + 1'd1);
+ end
+ if (litedramcore_bankmachine2_cmd_buffer_lookahead_do_read) begin
+ litedramcore_bankmachine2_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine2_cmd_buffer_lookahead_consume + 1'd1);
+ end
+ if (((litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable) & (~litedramcore_bankmachine2_cmd_buffer_lookahead_replace))) begin
+ if ((~litedramcore_bankmachine2_cmd_buffer_lookahead_do_read)) begin
+ litedramcore_bankmachine2_cmd_buffer_lookahead_level <= (litedramcore_bankmachine2_cmd_buffer_lookahead_level + 1'd1);
+ end
+ end else begin
+ if (litedramcore_bankmachine2_cmd_buffer_lookahead_do_read) begin
+ litedramcore_bankmachine2_cmd_buffer_lookahead_level <= (litedramcore_bankmachine2_cmd_buffer_lookahead_level - 1'd1);
+ end
+ end
+ if (((~litedramcore_bankmachine2_cmd_buffer_source_valid) | litedramcore_bankmachine2_cmd_buffer_source_ready)) begin
+ litedramcore_bankmachine2_cmd_buffer_source_valid <= litedramcore_bankmachine2_cmd_buffer_sink_valid;
+ litedramcore_bankmachine2_cmd_buffer_source_first <= litedramcore_bankmachine2_cmd_buffer_sink_first;
+ litedramcore_bankmachine2_cmd_buffer_source_last <= litedramcore_bankmachine2_cmd_buffer_sink_last;
+ litedramcore_bankmachine2_cmd_buffer_source_payload_we <= litedramcore_bankmachine2_cmd_buffer_sink_payload_we;
+ litedramcore_bankmachine2_cmd_buffer_source_payload_addr <= litedramcore_bankmachine2_cmd_buffer_sink_payload_addr;
+ end
+ if (litedramcore_bankmachine2_twtpcon_valid) begin
+ litedramcore_bankmachine2_twtpcon_count <= 3'd6;
+ if (1'd0) begin
+ litedramcore_bankmachine2_twtpcon_ready <= 1'd1;
+ end else begin
+ litedramcore_bankmachine2_twtpcon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~litedramcore_bankmachine2_twtpcon_ready)) begin
+ litedramcore_bankmachine2_twtpcon_count <= (litedramcore_bankmachine2_twtpcon_count - 1'd1);
+ if ((litedramcore_bankmachine2_twtpcon_count == 1'd1)) begin
+ litedramcore_bankmachine2_twtpcon_ready <= 1'd1;
+ end
+ end
+ end
+ if (litedramcore_bankmachine2_trccon_valid) begin
+ litedramcore_bankmachine2_trccon_count <= 2'd2;
+ if (1'd0) begin
+ litedramcore_bankmachine2_trccon_ready <= 1'd1;
+ end else begin
+ litedramcore_bankmachine2_trccon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~litedramcore_bankmachine2_trccon_ready)) begin
+ litedramcore_bankmachine2_trccon_count <= (litedramcore_bankmachine2_trccon_count - 1'd1);
+ if ((litedramcore_bankmachine2_trccon_count == 1'd1)) begin
+ litedramcore_bankmachine2_trccon_ready <= 1'd1;
+ end
+ end
+ end
+ if (litedramcore_bankmachine2_trascon_valid) begin
+ litedramcore_bankmachine2_trascon_count <= 2'd2;
+ if (1'd0) begin
+ litedramcore_bankmachine2_trascon_ready <= 1'd1;
+ end else begin
+ litedramcore_bankmachine2_trascon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~litedramcore_bankmachine2_trascon_ready)) begin
+ litedramcore_bankmachine2_trascon_count <= (litedramcore_bankmachine2_trascon_count - 1'd1);
+ if ((litedramcore_bankmachine2_trascon_count == 1'd1)) begin
+ litedramcore_bankmachine2_trascon_ready <= 1'd1;
+ end
+ end
+ end
+ litedramcore_bankmachine2_state <= litedramcore_bankmachine2_next_state;
+ if (litedramcore_bankmachine3_row_close) begin
+ litedramcore_bankmachine3_row_opened <= 1'd0;
+ end else begin
+ if (litedramcore_bankmachine3_row_open) begin
+ litedramcore_bankmachine3_row_opened <= 1'd1;
+ litedramcore_bankmachine3_row <= litedramcore_bankmachine3_cmd_buffer_source_payload_addr[21:7];
+ end
+ end
+ if (((litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable) & (~litedramcore_bankmachine3_cmd_buffer_lookahead_replace))) begin
+ litedramcore_bankmachine3_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine3_cmd_buffer_lookahead_produce + 1'd1);
+ end
+ if (litedramcore_bankmachine3_cmd_buffer_lookahead_do_read) begin
+ litedramcore_bankmachine3_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine3_cmd_buffer_lookahead_consume + 1'd1);
+ end
+ if (((litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable) & (~litedramcore_bankmachine3_cmd_buffer_lookahead_replace))) begin
+ if ((~litedramcore_bankmachine3_cmd_buffer_lookahead_do_read)) begin
+ litedramcore_bankmachine3_cmd_buffer_lookahead_level <= (litedramcore_bankmachine3_cmd_buffer_lookahead_level + 1'd1);
+ end
+ end else begin
+ if (litedramcore_bankmachine3_cmd_buffer_lookahead_do_read) begin
+ litedramcore_bankmachine3_cmd_buffer_lookahead_level <= (litedramcore_bankmachine3_cmd_buffer_lookahead_level - 1'd1);
+ end
+ end
+ if (((~litedramcore_bankmachine3_cmd_buffer_source_valid) | litedramcore_bankmachine3_cmd_buffer_source_ready)) begin
+ litedramcore_bankmachine3_cmd_buffer_source_valid <= litedramcore_bankmachine3_cmd_buffer_sink_valid;
+ litedramcore_bankmachine3_cmd_buffer_source_first <= litedramcore_bankmachine3_cmd_buffer_sink_first;
+ litedramcore_bankmachine3_cmd_buffer_source_last <= litedramcore_bankmachine3_cmd_buffer_sink_last;
+ litedramcore_bankmachine3_cmd_buffer_source_payload_we <= litedramcore_bankmachine3_cmd_buffer_sink_payload_we;
+ litedramcore_bankmachine3_cmd_buffer_source_payload_addr <= litedramcore_bankmachine3_cmd_buffer_sink_payload_addr;
+ end
+ if (litedramcore_bankmachine3_twtpcon_valid) begin
+ litedramcore_bankmachine3_twtpcon_count <= 3'd6;
+ if (1'd0) begin
+ litedramcore_bankmachine3_twtpcon_ready <= 1'd1;
+ end else begin
+ litedramcore_bankmachine3_twtpcon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~litedramcore_bankmachine3_twtpcon_ready)) begin
+ litedramcore_bankmachine3_twtpcon_count <= (litedramcore_bankmachine3_twtpcon_count - 1'd1);
+ if ((litedramcore_bankmachine3_twtpcon_count == 1'd1)) begin
+ litedramcore_bankmachine3_twtpcon_ready <= 1'd1;
+ end
+ end
+ end
+ if (litedramcore_bankmachine3_trccon_valid) begin
+ litedramcore_bankmachine3_trccon_count <= 2'd2;
+ if (1'd0) begin
+ litedramcore_bankmachine3_trccon_ready <= 1'd1;
+ end else begin
+ litedramcore_bankmachine3_trccon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~litedramcore_bankmachine3_trccon_ready)) begin
+ litedramcore_bankmachine3_trccon_count <= (litedramcore_bankmachine3_trccon_count - 1'd1);
+ if ((litedramcore_bankmachine3_trccon_count == 1'd1)) begin
+ litedramcore_bankmachine3_trccon_ready <= 1'd1;
+ end
+ end
+ end
+ if (litedramcore_bankmachine3_trascon_valid) begin
+ litedramcore_bankmachine3_trascon_count <= 2'd2;
+ if (1'd0) begin
+ litedramcore_bankmachine3_trascon_ready <= 1'd1;
+ end else begin
+ litedramcore_bankmachine3_trascon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~litedramcore_bankmachine3_trascon_ready)) begin
+ litedramcore_bankmachine3_trascon_count <= (litedramcore_bankmachine3_trascon_count - 1'd1);
+ if ((litedramcore_bankmachine3_trascon_count == 1'd1)) begin
+ litedramcore_bankmachine3_trascon_ready <= 1'd1;
+ end
+ end
+ end
+ litedramcore_bankmachine3_state <= litedramcore_bankmachine3_next_state;
+ if (litedramcore_bankmachine4_row_close) begin
+ litedramcore_bankmachine4_row_opened <= 1'd0;
+ end else begin
+ if (litedramcore_bankmachine4_row_open) begin
+ litedramcore_bankmachine4_row_opened <= 1'd1;
+ litedramcore_bankmachine4_row <= litedramcore_bankmachine4_cmd_buffer_source_payload_addr[21:7];
+ end
+ end
+ if (((litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable) & (~litedramcore_bankmachine4_cmd_buffer_lookahead_replace))) begin
+ litedramcore_bankmachine4_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine4_cmd_buffer_lookahead_produce + 1'd1);
+ end
+ if (litedramcore_bankmachine4_cmd_buffer_lookahead_do_read) begin
+ litedramcore_bankmachine4_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine4_cmd_buffer_lookahead_consume + 1'd1);
+ end
+ if (((litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable) & (~litedramcore_bankmachine4_cmd_buffer_lookahead_replace))) begin
+ if ((~litedramcore_bankmachine4_cmd_buffer_lookahead_do_read)) begin
+ litedramcore_bankmachine4_cmd_buffer_lookahead_level <= (litedramcore_bankmachine4_cmd_buffer_lookahead_level + 1'd1);
+ end
+ end else begin
+ if (litedramcore_bankmachine4_cmd_buffer_lookahead_do_read) begin
+ litedramcore_bankmachine4_cmd_buffer_lookahead_level <= (litedramcore_bankmachine4_cmd_buffer_lookahead_level - 1'd1);
+ end
+ end
+ if (((~litedramcore_bankmachine4_cmd_buffer_source_valid) | litedramcore_bankmachine4_cmd_buffer_source_ready)) begin
+ litedramcore_bankmachine4_cmd_buffer_source_valid <= litedramcore_bankmachine4_cmd_buffer_sink_valid;
+ litedramcore_bankmachine4_cmd_buffer_source_first <= litedramcore_bankmachine4_cmd_buffer_sink_first;
+ litedramcore_bankmachine4_cmd_buffer_source_last <= litedramcore_bankmachine4_cmd_buffer_sink_last;
+ litedramcore_bankmachine4_cmd_buffer_source_payload_we <= litedramcore_bankmachine4_cmd_buffer_sink_payload_we;
+ litedramcore_bankmachine4_cmd_buffer_source_payload_addr <= litedramcore_bankmachine4_cmd_buffer_sink_payload_addr;
+ end
+ if (litedramcore_bankmachine4_twtpcon_valid) begin
+ litedramcore_bankmachine4_twtpcon_count <= 3'd6;
+ if (1'd0) begin
+ litedramcore_bankmachine4_twtpcon_ready <= 1'd1;
+ end else begin
+ litedramcore_bankmachine4_twtpcon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~litedramcore_bankmachine4_twtpcon_ready)) begin
+ litedramcore_bankmachine4_twtpcon_count <= (litedramcore_bankmachine4_twtpcon_count - 1'd1);
+ if ((litedramcore_bankmachine4_twtpcon_count == 1'd1)) begin
+ litedramcore_bankmachine4_twtpcon_ready <= 1'd1;
+ end
+ end
+ end
+ if (litedramcore_bankmachine4_trccon_valid) begin
+ litedramcore_bankmachine4_trccon_count <= 2'd2;
+ if (1'd0) begin
+ litedramcore_bankmachine4_trccon_ready <= 1'd1;
+ end else begin
+ litedramcore_bankmachine4_trccon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~litedramcore_bankmachine4_trccon_ready)) begin
+ litedramcore_bankmachine4_trccon_count <= (litedramcore_bankmachine4_trccon_count - 1'd1);
+ if ((litedramcore_bankmachine4_trccon_count == 1'd1)) begin
+ litedramcore_bankmachine4_trccon_ready <= 1'd1;
+ end
+ end
+ end
+ if (litedramcore_bankmachine4_trascon_valid) begin
+ litedramcore_bankmachine4_trascon_count <= 2'd2;
+ if (1'd0) begin
+ litedramcore_bankmachine4_trascon_ready <= 1'd1;
+ end else begin
+ litedramcore_bankmachine4_trascon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~litedramcore_bankmachine4_trascon_ready)) begin
+ litedramcore_bankmachine4_trascon_count <= (litedramcore_bankmachine4_trascon_count - 1'd1);
+ if ((litedramcore_bankmachine4_trascon_count == 1'd1)) begin
+ litedramcore_bankmachine4_trascon_ready <= 1'd1;
+ end
+ end
+ end
+ litedramcore_bankmachine4_state <= litedramcore_bankmachine4_next_state;
+ if (litedramcore_bankmachine5_row_close) begin
+ litedramcore_bankmachine5_row_opened <= 1'd0;
+ end else begin
+ if (litedramcore_bankmachine5_row_open) begin
+ litedramcore_bankmachine5_row_opened <= 1'd1;
+ litedramcore_bankmachine5_row <= litedramcore_bankmachine5_cmd_buffer_source_payload_addr[21:7];
+ end
+ end
+ if (((litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable) & (~litedramcore_bankmachine5_cmd_buffer_lookahead_replace))) begin
+ litedramcore_bankmachine5_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine5_cmd_buffer_lookahead_produce + 1'd1);
+ end
+ if (litedramcore_bankmachine5_cmd_buffer_lookahead_do_read) begin
+ litedramcore_bankmachine5_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine5_cmd_buffer_lookahead_consume + 1'd1);
+ end
+ if (((litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable) & (~litedramcore_bankmachine5_cmd_buffer_lookahead_replace))) begin
+ if ((~litedramcore_bankmachine5_cmd_buffer_lookahead_do_read)) begin
+ litedramcore_bankmachine5_cmd_buffer_lookahead_level <= (litedramcore_bankmachine5_cmd_buffer_lookahead_level + 1'd1);
+ end
+ end else begin
+ if (litedramcore_bankmachine5_cmd_buffer_lookahead_do_read) begin
+ litedramcore_bankmachine5_cmd_buffer_lookahead_level <= (litedramcore_bankmachine5_cmd_buffer_lookahead_level - 1'd1);
+ end
+ end
+ if (((~litedramcore_bankmachine5_cmd_buffer_source_valid) | litedramcore_bankmachine5_cmd_buffer_source_ready)) begin
+ litedramcore_bankmachine5_cmd_buffer_source_valid <= litedramcore_bankmachine5_cmd_buffer_sink_valid;
+ litedramcore_bankmachine5_cmd_buffer_source_first <= litedramcore_bankmachine5_cmd_buffer_sink_first;
+ litedramcore_bankmachine5_cmd_buffer_source_last <= litedramcore_bankmachine5_cmd_buffer_sink_last;
+ litedramcore_bankmachine5_cmd_buffer_source_payload_we <= litedramcore_bankmachine5_cmd_buffer_sink_payload_we;
+ litedramcore_bankmachine5_cmd_buffer_source_payload_addr <= litedramcore_bankmachine5_cmd_buffer_sink_payload_addr;
+ end
+ if (litedramcore_bankmachine5_twtpcon_valid) begin
+ litedramcore_bankmachine5_twtpcon_count <= 3'd6;
+ if (1'd0) begin
+ litedramcore_bankmachine5_twtpcon_ready <= 1'd1;
+ end else begin
+ litedramcore_bankmachine5_twtpcon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~litedramcore_bankmachine5_twtpcon_ready)) begin
+ litedramcore_bankmachine5_twtpcon_count <= (litedramcore_bankmachine5_twtpcon_count - 1'd1);
+ if ((litedramcore_bankmachine5_twtpcon_count == 1'd1)) begin
+ litedramcore_bankmachine5_twtpcon_ready <= 1'd1;
+ end
+ end
+ end
+ if (litedramcore_bankmachine5_trccon_valid) begin
+ litedramcore_bankmachine5_trccon_count <= 2'd2;
+ if (1'd0) begin
+ litedramcore_bankmachine5_trccon_ready <= 1'd1;
+ end else begin
+ litedramcore_bankmachine5_trccon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~litedramcore_bankmachine5_trccon_ready)) begin
+ litedramcore_bankmachine5_trccon_count <= (litedramcore_bankmachine5_trccon_count - 1'd1);
+ if ((litedramcore_bankmachine5_trccon_count == 1'd1)) begin
+ litedramcore_bankmachine5_trccon_ready <= 1'd1;
+ end
+ end
+ end
+ if (litedramcore_bankmachine5_trascon_valid) begin
+ litedramcore_bankmachine5_trascon_count <= 2'd2;
+ if (1'd0) begin
+ litedramcore_bankmachine5_trascon_ready <= 1'd1;
+ end else begin
+ litedramcore_bankmachine5_trascon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~litedramcore_bankmachine5_trascon_ready)) begin
+ litedramcore_bankmachine5_trascon_count <= (litedramcore_bankmachine5_trascon_count - 1'd1);
+ if ((litedramcore_bankmachine5_trascon_count == 1'd1)) begin
+ litedramcore_bankmachine5_trascon_ready <= 1'd1;
+ end
+ end
+ end
+ litedramcore_bankmachine5_state <= litedramcore_bankmachine5_next_state;
+ if (litedramcore_bankmachine6_row_close) begin
+ litedramcore_bankmachine6_row_opened <= 1'd0;
+ end else begin
+ if (litedramcore_bankmachine6_row_open) begin
+ litedramcore_bankmachine6_row_opened <= 1'd1;
+ litedramcore_bankmachine6_row <= litedramcore_bankmachine6_cmd_buffer_source_payload_addr[21:7];
+ end
+ end
+ if (((litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable) & (~litedramcore_bankmachine6_cmd_buffer_lookahead_replace))) begin
+ litedramcore_bankmachine6_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine6_cmd_buffer_lookahead_produce + 1'd1);
+ end
+ if (litedramcore_bankmachine6_cmd_buffer_lookahead_do_read) begin
+ litedramcore_bankmachine6_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine6_cmd_buffer_lookahead_consume + 1'd1);
+ end
+ if (((litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable) & (~litedramcore_bankmachine6_cmd_buffer_lookahead_replace))) begin
+ if ((~litedramcore_bankmachine6_cmd_buffer_lookahead_do_read)) begin
+ litedramcore_bankmachine6_cmd_buffer_lookahead_level <= (litedramcore_bankmachine6_cmd_buffer_lookahead_level + 1'd1);
+ end
+ end else begin
+ if (litedramcore_bankmachine6_cmd_buffer_lookahead_do_read) begin
+ litedramcore_bankmachine6_cmd_buffer_lookahead_level <= (litedramcore_bankmachine6_cmd_buffer_lookahead_level - 1'd1);
+ end
+ end
+ if (((~litedramcore_bankmachine6_cmd_buffer_source_valid) | litedramcore_bankmachine6_cmd_buffer_source_ready)) begin
+ litedramcore_bankmachine6_cmd_buffer_source_valid <= litedramcore_bankmachine6_cmd_buffer_sink_valid;
+ litedramcore_bankmachine6_cmd_buffer_source_first <= litedramcore_bankmachine6_cmd_buffer_sink_first;
+ litedramcore_bankmachine6_cmd_buffer_source_last <= litedramcore_bankmachine6_cmd_buffer_sink_last;
+ litedramcore_bankmachine6_cmd_buffer_source_payload_we <= litedramcore_bankmachine6_cmd_buffer_sink_payload_we;
+ litedramcore_bankmachine6_cmd_buffer_source_payload_addr <= litedramcore_bankmachine6_cmd_buffer_sink_payload_addr;
+ end
+ if (litedramcore_bankmachine6_twtpcon_valid) begin
+ litedramcore_bankmachine6_twtpcon_count <= 3'd6;
+ if (1'd0) begin
+ litedramcore_bankmachine6_twtpcon_ready <= 1'd1;
+ end else begin
+ litedramcore_bankmachine6_twtpcon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~litedramcore_bankmachine6_twtpcon_ready)) begin
+ litedramcore_bankmachine6_twtpcon_count <= (litedramcore_bankmachine6_twtpcon_count - 1'd1);
+ if ((litedramcore_bankmachine6_twtpcon_count == 1'd1)) begin
+ litedramcore_bankmachine6_twtpcon_ready <= 1'd1;
+ end
+ end
+ end
+ if (litedramcore_bankmachine6_trccon_valid) begin
+ litedramcore_bankmachine6_trccon_count <= 2'd2;
+ if (1'd0) begin
+ litedramcore_bankmachine6_trccon_ready <= 1'd1;
+ end else begin
+ litedramcore_bankmachine6_trccon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~litedramcore_bankmachine6_trccon_ready)) begin
+ litedramcore_bankmachine6_trccon_count <= (litedramcore_bankmachine6_trccon_count - 1'd1);
+ if ((litedramcore_bankmachine6_trccon_count == 1'd1)) begin
+ litedramcore_bankmachine6_trccon_ready <= 1'd1;
+ end
+ end
+ end
+ if (litedramcore_bankmachine6_trascon_valid) begin
+ litedramcore_bankmachine6_trascon_count <= 2'd2;
+ if (1'd0) begin
+ litedramcore_bankmachine6_trascon_ready <= 1'd1;
+ end else begin
+ litedramcore_bankmachine6_trascon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~litedramcore_bankmachine6_trascon_ready)) begin
+ litedramcore_bankmachine6_trascon_count <= (litedramcore_bankmachine6_trascon_count - 1'd1);
+ if ((litedramcore_bankmachine6_trascon_count == 1'd1)) begin
+ litedramcore_bankmachine6_trascon_ready <= 1'd1;
+ end
+ end
+ end
+ litedramcore_bankmachine6_state <= litedramcore_bankmachine6_next_state;
+ if (litedramcore_bankmachine7_row_close) begin
+ litedramcore_bankmachine7_row_opened <= 1'd0;
+ end else begin
+ if (litedramcore_bankmachine7_row_open) begin
+ litedramcore_bankmachine7_row_opened <= 1'd1;
+ litedramcore_bankmachine7_row <= litedramcore_bankmachine7_cmd_buffer_source_payload_addr[21:7];
+ end
+ end
+ if (((litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable) & (~litedramcore_bankmachine7_cmd_buffer_lookahead_replace))) begin
+ litedramcore_bankmachine7_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine7_cmd_buffer_lookahead_produce + 1'd1);
+ end
+ if (litedramcore_bankmachine7_cmd_buffer_lookahead_do_read) begin
+ litedramcore_bankmachine7_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine7_cmd_buffer_lookahead_consume + 1'd1);
+ end
+ if (((litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable) & (~litedramcore_bankmachine7_cmd_buffer_lookahead_replace))) begin
+ if ((~litedramcore_bankmachine7_cmd_buffer_lookahead_do_read)) begin
+ litedramcore_bankmachine7_cmd_buffer_lookahead_level <= (litedramcore_bankmachine7_cmd_buffer_lookahead_level + 1'd1);
+ end
+ end else begin
+ if (litedramcore_bankmachine7_cmd_buffer_lookahead_do_read) begin
+ litedramcore_bankmachine7_cmd_buffer_lookahead_level <= (litedramcore_bankmachine7_cmd_buffer_lookahead_level - 1'd1);
+ end
+ end
+ if (((~litedramcore_bankmachine7_cmd_buffer_source_valid) | litedramcore_bankmachine7_cmd_buffer_source_ready)) begin
+ litedramcore_bankmachine7_cmd_buffer_source_valid <= litedramcore_bankmachine7_cmd_buffer_sink_valid;
+ litedramcore_bankmachine7_cmd_buffer_source_first <= litedramcore_bankmachine7_cmd_buffer_sink_first;
+ litedramcore_bankmachine7_cmd_buffer_source_last <= litedramcore_bankmachine7_cmd_buffer_sink_last;
+ litedramcore_bankmachine7_cmd_buffer_source_payload_we <= litedramcore_bankmachine7_cmd_buffer_sink_payload_we;
+ litedramcore_bankmachine7_cmd_buffer_source_payload_addr <= litedramcore_bankmachine7_cmd_buffer_sink_payload_addr;
+ end
+ if (litedramcore_bankmachine7_twtpcon_valid) begin
+ litedramcore_bankmachine7_twtpcon_count <= 3'd6;
+ if (1'd0) begin
+ litedramcore_bankmachine7_twtpcon_ready <= 1'd1;
+ end else begin
+ litedramcore_bankmachine7_twtpcon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~litedramcore_bankmachine7_twtpcon_ready)) begin
+ litedramcore_bankmachine7_twtpcon_count <= (litedramcore_bankmachine7_twtpcon_count - 1'd1);
+ if ((litedramcore_bankmachine7_twtpcon_count == 1'd1)) begin
+ litedramcore_bankmachine7_twtpcon_ready <= 1'd1;
+ end
+ end
+ end
+ if (litedramcore_bankmachine7_trccon_valid) begin
+ litedramcore_bankmachine7_trccon_count <= 2'd2;
+ if (1'd0) begin
+ litedramcore_bankmachine7_trccon_ready <= 1'd1;
+ end else begin
+ litedramcore_bankmachine7_trccon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~litedramcore_bankmachine7_trccon_ready)) begin
+ litedramcore_bankmachine7_trccon_count <= (litedramcore_bankmachine7_trccon_count - 1'd1);
+ if ((litedramcore_bankmachine7_trccon_count == 1'd1)) begin
+ litedramcore_bankmachine7_trccon_ready <= 1'd1;
+ end
+ end
+ end
+ if (litedramcore_bankmachine7_trascon_valid) begin
+ litedramcore_bankmachine7_trascon_count <= 2'd2;
+ if (1'd0) begin
+ litedramcore_bankmachine7_trascon_ready <= 1'd1;
+ end else begin
+ litedramcore_bankmachine7_trascon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~litedramcore_bankmachine7_trascon_ready)) begin
+ litedramcore_bankmachine7_trascon_count <= (litedramcore_bankmachine7_trascon_count - 1'd1);
+ if ((litedramcore_bankmachine7_trascon_count == 1'd1)) begin
+ litedramcore_bankmachine7_trascon_ready <= 1'd1;
+ end
+ end
+ end
+ litedramcore_bankmachine7_state <= litedramcore_bankmachine7_next_state;
+ if ((~litedramcore_en0)) begin
+ litedramcore_time0 <= 5'd31;
+ end else begin
+ if ((~litedramcore_max_time0)) begin
+ litedramcore_time0 <= (litedramcore_time0 - 1'd1);
+ end
+ end
+ if ((~litedramcore_en1)) begin
+ litedramcore_time1 <= 4'd15;
+ end else begin
+ if ((~litedramcore_max_time1)) begin
+ litedramcore_time1 <= (litedramcore_time1 - 1'd1);
+ end
+ end
+ if (litedramcore_choose_cmd_ce) begin
+ case (litedramcore_choose_cmd_grant)
+ 1'd0: begin
+ if (litedramcore_choose_cmd_request[1]) begin
+ litedramcore_choose_cmd_grant <= 1'd1;
+ end else begin
+ if (litedramcore_choose_cmd_request[2]) begin
+ litedramcore_choose_cmd_grant <= 2'd2;
+ end else begin
+ if (litedramcore_choose_cmd_request[3]) begin
+ litedramcore_choose_cmd_grant <= 2'd3;
+ end else begin
+ if (litedramcore_choose_cmd_request[4]) begin
+ litedramcore_choose_cmd_grant <= 3'd4;
+ end else begin
+ if (litedramcore_choose_cmd_request[5]) begin
+ litedramcore_choose_cmd_grant <= 3'd5;
+ end else begin
+ if (litedramcore_choose_cmd_request[6]) begin
+ litedramcore_choose_cmd_grant <= 3'd6;
+ end else begin
+ if (litedramcore_choose_cmd_request[7]) begin
+ litedramcore_choose_cmd_grant <= 3'd7;
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ 1'd1: begin
+ if (litedramcore_choose_cmd_request[2]) begin
+ litedramcore_choose_cmd_grant <= 2'd2;
+ end else begin
+ if (litedramcore_choose_cmd_request[3]) begin
+ litedramcore_choose_cmd_grant <= 2'd3;
+ end else begin
+ if (litedramcore_choose_cmd_request[4]) begin
+ litedramcore_choose_cmd_grant <= 3'd4;
+ end else begin
+ if (litedramcore_choose_cmd_request[5]) begin
+ litedramcore_choose_cmd_grant <= 3'd5;
+ end else begin
+ if (litedramcore_choose_cmd_request[6]) begin
+ litedramcore_choose_cmd_grant <= 3'd6;
+ end else begin
+ if (litedramcore_choose_cmd_request[7]) begin
+ litedramcore_choose_cmd_grant <= 3'd7;
+ end else begin
+ if (litedramcore_choose_cmd_request[0]) begin
+ litedramcore_choose_cmd_grant <= 1'd0;
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ 2'd2: begin
+ if (litedramcore_choose_cmd_request[3]) begin
+ litedramcore_choose_cmd_grant <= 2'd3;
+ end else begin
+ if (litedramcore_choose_cmd_request[4]) begin
+ litedramcore_choose_cmd_grant <= 3'd4;
+ end else begin
+ if (litedramcore_choose_cmd_request[5]) begin
+ litedramcore_choose_cmd_grant <= 3'd5;
+ end else begin
+ if (litedramcore_choose_cmd_request[6]) begin
+ litedramcore_choose_cmd_grant <= 3'd6;
+ end else begin
+ if (litedramcore_choose_cmd_request[7]) begin
+ litedramcore_choose_cmd_grant <= 3'd7;
+ end else begin
+ if (litedramcore_choose_cmd_request[0]) begin
+ litedramcore_choose_cmd_grant <= 1'd0;
+ end else begin
+ if (litedramcore_choose_cmd_request[1]) begin
+ litedramcore_choose_cmd_grant <= 1'd1;
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ 2'd3: begin
+ if (litedramcore_choose_cmd_request[4]) begin
+ litedramcore_choose_cmd_grant <= 3'd4;
+ end else begin
+ if (litedramcore_choose_cmd_request[5]) begin
+ litedramcore_choose_cmd_grant <= 3'd5;
+ end else begin
+ if (litedramcore_choose_cmd_request[6]) begin
+ litedramcore_choose_cmd_grant <= 3'd6;
+ end else begin
+ if (litedramcore_choose_cmd_request[7]) begin
+ litedramcore_choose_cmd_grant <= 3'd7;
+ end else begin
+ if (litedramcore_choose_cmd_request[0]) begin
+ litedramcore_choose_cmd_grant <= 1'd0;
+ end else begin
+ if (litedramcore_choose_cmd_request[1]) begin
+ litedramcore_choose_cmd_grant <= 1'd1;
+ end else begin
+ if (litedramcore_choose_cmd_request[2]) begin
+ litedramcore_choose_cmd_grant <= 2'd2;
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ 3'd4: begin
+ if (litedramcore_choose_cmd_request[5]) begin
+ litedramcore_choose_cmd_grant <= 3'd5;
+ end else begin
+ if (litedramcore_choose_cmd_request[6]) begin
+ litedramcore_choose_cmd_grant <= 3'd6;
+ end else begin
+ if (litedramcore_choose_cmd_request[7]) begin
+ litedramcore_choose_cmd_grant <= 3'd7;
+ end else begin
+ if (litedramcore_choose_cmd_request[0]) begin
+ litedramcore_choose_cmd_grant <= 1'd0;
+ end else begin
+ if (litedramcore_choose_cmd_request[1]) begin
+ litedramcore_choose_cmd_grant <= 1'd1;
+ end else begin
+ if (litedramcore_choose_cmd_request[2]) begin
+ litedramcore_choose_cmd_grant <= 2'd2;
+ end else begin
+ if (litedramcore_choose_cmd_request[3]) begin
+ litedramcore_choose_cmd_grant <= 2'd3;
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ 3'd5: begin
+ if (litedramcore_choose_cmd_request[6]) begin
+ litedramcore_choose_cmd_grant <= 3'd6;
+ end else begin
+ if (litedramcore_choose_cmd_request[7]) begin
+ litedramcore_choose_cmd_grant <= 3'd7;
+ end else begin
+ if (litedramcore_choose_cmd_request[0]) begin
+ litedramcore_choose_cmd_grant <= 1'd0;
+ end else begin
+ if (litedramcore_choose_cmd_request[1]) begin
+ litedramcore_choose_cmd_grant <= 1'd1;
+ end else begin
+ if (litedramcore_choose_cmd_request[2]) begin
+ litedramcore_choose_cmd_grant <= 2'd2;
+ end else begin
+ if (litedramcore_choose_cmd_request[3]) begin
+ litedramcore_choose_cmd_grant <= 2'd3;
+ end else begin
+ if (litedramcore_choose_cmd_request[4]) begin
+ litedramcore_choose_cmd_grant <= 3'd4;
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ 3'd6: begin
+ if (litedramcore_choose_cmd_request[7]) begin
+ litedramcore_choose_cmd_grant <= 3'd7;
+ end else begin
+ if (litedramcore_choose_cmd_request[0]) begin
+ litedramcore_choose_cmd_grant <= 1'd0;
+ end else begin
+ if (litedramcore_choose_cmd_request[1]) begin
+ litedramcore_choose_cmd_grant <= 1'd1;
+ end else begin
+ if (litedramcore_choose_cmd_request[2]) begin
+ litedramcore_choose_cmd_grant <= 2'd2;
+ end else begin
+ if (litedramcore_choose_cmd_request[3]) begin
+ litedramcore_choose_cmd_grant <= 2'd3;
+ end else begin
+ if (litedramcore_choose_cmd_request[4]) begin
+ litedramcore_choose_cmd_grant <= 3'd4;
+ end else begin
+ if (litedramcore_choose_cmd_request[5]) begin
+ litedramcore_choose_cmd_grant <= 3'd5;
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ 3'd7: begin
+ if (litedramcore_choose_cmd_request[0]) begin
+ litedramcore_choose_cmd_grant <= 1'd0;
+ end else begin
+ if (litedramcore_choose_cmd_request[1]) begin
+ litedramcore_choose_cmd_grant <= 1'd1;
+ end else begin
+ if (litedramcore_choose_cmd_request[2]) begin
+ litedramcore_choose_cmd_grant <= 2'd2;
+ end else begin
+ if (litedramcore_choose_cmd_request[3]) begin
+ litedramcore_choose_cmd_grant <= 2'd3;
+ end else begin
+ if (litedramcore_choose_cmd_request[4]) begin
+ litedramcore_choose_cmd_grant <= 3'd4;
+ end else begin
+ if (litedramcore_choose_cmd_request[5]) begin
+ litedramcore_choose_cmd_grant <= 3'd5;
+ end else begin
+ if (litedramcore_choose_cmd_request[6]) begin
+ litedramcore_choose_cmd_grant <= 3'd6;
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ endcase
+ end
+ if (litedramcore_choose_req_ce) begin
+ case (litedramcore_choose_req_grant)
+ 1'd0: begin
+ if (litedramcore_choose_req_request[1]) begin
+ litedramcore_choose_req_grant <= 1'd1;
+ end else begin
+ if (litedramcore_choose_req_request[2]) begin
+ litedramcore_choose_req_grant <= 2'd2;
+ end else begin
+ if (litedramcore_choose_req_request[3]) begin
+ litedramcore_choose_req_grant <= 2'd3;
+ end else begin
+ if (litedramcore_choose_req_request[4]) begin
+ litedramcore_choose_req_grant <= 3'd4;
+ end else begin
+ if (litedramcore_choose_req_request[5]) begin
+ litedramcore_choose_req_grant <= 3'd5;
+ end else begin
+ if (litedramcore_choose_req_request[6]) begin
+ litedramcore_choose_req_grant <= 3'd6;
+ end else begin
+ if (litedramcore_choose_req_request[7]) begin
+ litedramcore_choose_req_grant <= 3'd7;
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ 1'd1: begin
+ if (litedramcore_choose_req_request[2]) begin
+ litedramcore_choose_req_grant <= 2'd2;
+ end else begin
+ if (litedramcore_choose_req_request[3]) begin
+ litedramcore_choose_req_grant <= 2'd3;
+ end else begin
+ if (litedramcore_choose_req_request[4]) begin
+ litedramcore_choose_req_grant <= 3'd4;
+ end else begin
+ if (litedramcore_choose_req_request[5]) begin
+ litedramcore_choose_req_grant <= 3'd5;
+ end else begin
+ if (litedramcore_choose_req_request[6]) begin
+ litedramcore_choose_req_grant <= 3'd6;
+ end else begin
+ if (litedramcore_choose_req_request[7]) begin
+ litedramcore_choose_req_grant <= 3'd7;
+ end else begin
+ if (litedramcore_choose_req_request[0]) begin
+ litedramcore_choose_req_grant <= 1'd0;
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ 2'd2: begin
+ if (litedramcore_choose_req_request[3]) begin
+ litedramcore_choose_req_grant <= 2'd3;
+ end else begin
+ if (litedramcore_choose_req_request[4]) begin
+ litedramcore_choose_req_grant <= 3'd4;
+ end else begin
+ if (litedramcore_choose_req_request[5]) begin
+ litedramcore_choose_req_grant <= 3'd5;
+ end else begin
+ if (litedramcore_choose_req_request[6]) begin
+ litedramcore_choose_req_grant <= 3'd6;
+ end else begin
+ if (litedramcore_choose_req_request[7]) begin
+ litedramcore_choose_req_grant <= 3'd7;
+ end else begin
+ if (litedramcore_choose_req_request[0]) begin
+ litedramcore_choose_req_grant <= 1'd0;
+ end else begin
+ if (litedramcore_choose_req_request[1]) begin
+ litedramcore_choose_req_grant <= 1'd1;
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ 2'd3: begin
+ if (litedramcore_choose_req_request[4]) begin
+ litedramcore_choose_req_grant <= 3'd4;
+ end else begin
+ if (litedramcore_choose_req_request[5]) begin
+ litedramcore_choose_req_grant <= 3'd5;
+ end else begin
+ if (litedramcore_choose_req_request[6]) begin
+ litedramcore_choose_req_grant <= 3'd6;
+ end else begin
+ if (litedramcore_choose_req_request[7]) begin
+ litedramcore_choose_req_grant <= 3'd7;
+ end else begin
+ if (litedramcore_choose_req_request[0]) begin
+ litedramcore_choose_req_grant <= 1'd0;
+ end else begin
+ if (litedramcore_choose_req_request[1]) begin
+ litedramcore_choose_req_grant <= 1'd1;
+ end else begin
+ if (litedramcore_choose_req_request[2]) begin
+ litedramcore_choose_req_grant <= 2'd2;
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ 3'd4: begin
+ if (litedramcore_choose_req_request[5]) begin
+ litedramcore_choose_req_grant <= 3'd5;
+ end else begin
+ if (litedramcore_choose_req_request[6]) begin
+ litedramcore_choose_req_grant <= 3'd6;
+ end else begin
+ if (litedramcore_choose_req_request[7]) begin
+ litedramcore_choose_req_grant <= 3'd7;
+ end else begin
+ if (litedramcore_choose_req_request[0]) begin
+ litedramcore_choose_req_grant <= 1'd0;
+ end else begin
+ if (litedramcore_choose_req_request[1]) begin
+ litedramcore_choose_req_grant <= 1'd1;
+ end else begin
+ if (litedramcore_choose_req_request[2]) begin
+ litedramcore_choose_req_grant <= 2'd2;
+ end else begin
+ if (litedramcore_choose_req_request[3]) begin
+ litedramcore_choose_req_grant <= 2'd3;
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ 3'd5: begin
+ if (litedramcore_choose_req_request[6]) begin
+ litedramcore_choose_req_grant <= 3'd6;
+ end else begin
+ if (litedramcore_choose_req_request[7]) begin
+ litedramcore_choose_req_grant <= 3'd7;
+ end else begin
+ if (litedramcore_choose_req_request[0]) begin
+ litedramcore_choose_req_grant <= 1'd0;
+ end else begin
+ if (litedramcore_choose_req_request[1]) begin
+ litedramcore_choose_req_grant <= 1'd1;
+ end else begin
+ if (litedramcore_choose_req_request[2]) begin
+ litedramcore_choose_req_grant <= 2'd2;
+ end else begin
+ if (litedramcore_choose_req_request[3]) begin
+ litedramcore_choose_req_grant <= 2'd3;
+ end else begin
+ if (litedramcore_choose_req_request[4]) begin
+ litedramcore_choose_req_grant <= 3'd4;
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ 3'd6: begin
+ if (litedramcore_choose_req_request[7]) begin
+ litedramcore_choose_req_grant <= 3'd7;
+ end else begin
+ if (litedramcore_choose_req_request[0]) begin
+ litedramcore_choose_req_grant <= 1'd0;
+ end else begin
+ if (litedramcore_choose_req_request[1]) begin
+ litedramcore_choose_req_grant <= 1'd1;
+ end else begin
+ if (litedramcore_choose_req_request[2]) begin
+ litedramcore_choose_req_grant <= 2'd2;
+ end else begin
+ if (litedramcore_choose_req_request[3]) begin
+ litedramcore_choose_req_grant <= 2'd3;
+ end else begin
+ if (litedramcore_choose_req_request[4]) begin
+ litedramcore_choose_req_grant <= 3'd4;
+ end else begin
+ if (litedramcore_choose_req_request[5]) begin
+ litedramcore_choose_req_grant <= 3'd5;
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ 3'd7: begin
+ if (litedramcore_choose_req_request[0]) begin
+ litedramcore_choose_req_grant <= 1'd0;
+ end else begin
+ if (litedramcore_choose_req_request[1]) begin
+ litedramcore_choose_req_grant <= 1'd1;
+ end else begin
+ if (litedramcore_choose_req_request[2]) begin
+ litedramcore_choose_req_grant <= 2'd2;
+ end else begin
+ if (litedramcore_choose_req_request[3]) begin
+ litedramcore_choose_req_grant <= 2'd3;
+ end else begin
+ if (litedramcore_choose_req_request[4]) begin
+ litedramcore_choose_req_grant <= 3'd4;
+ end else begin
+ if (litedramcore_choose_req_request[5]) begin
+ litedramcore_choose_req_grant <= 3'd5;
+ end else begin
+ if (litedramcore_choose_req_request[6]) begin
+ litedramcore_choose_req_grant <= 3'd6;
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ endcase
+ end
+ litedramcore_dfi_p0_cs_n <= 1'd0;
+ litedramcore_dfi_p0_bank <= array_muxed0;
+ litedramcore_dfi_p0_address <= array_muxed1;
+ litedramcore_dfi_p0_cas_n <= (~array_muxed2);
+ litedramcore_dfi_p0_ras_n <= (~array_muxed3);
+ litedramcore_dfi_p0_we_n <= (~array_muxed4);
+ litedramcore_dfi_p0_rddata_en <= array_muxed5;
+ litedramcore_dfi_p0_wrdata_en <= array_muxed6;
+ litedramcore_dfi_p1_cs_n <= 1'd0;
+ litedramcore_dfi_p1_bank <= array_muxed7;
+ litedramcore_dfi_p1_address <= array_muxed8;
+ litedramcore_dfi_p1_cas_n <= (~array_muxed9);
+ litedramcore_dfi_p1_ras_n <= (~array_muxed10);
+ litedramcore_dfi_p1_we_n <= (~array_muxed11);
+ litedramcore_dfi_p1_rddata_en <= array_muxed12;
+ litedramcore_dfi_p1_wrdata_en <= array_muxed13;
+ if (litedramcore_trrdcon_valid) begin
+ litedramcore_trrdcon_count <= 1'd1;
+ if (1'd0) begin
+ litedramcore_trrdcon_ready <= 1'd1;
+ end else begin
+ litedramcore_trrdcon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~litedramcore_trrdcon_ready)) begin
+ litedramcore_trrdcon_count <= (litedramcore_trrdcon_count - 1'd1);
+ if ((litedramcore_trrdcon_count == 1'd1)) begin
+ litedramcore_trrdcon_ready <= 1'd1;
+ end
+ end
+ end
+ litedramcore_tfawcon_window <= {litedramcore_tfawcon_window, litedramcore_tfawcon_valid};
+ if ((litedramcore_tfawcon_count < 3'd4)) begin
+ if ((litedramcore_tfawcon_count == 2'd3)) begin
+ litedramcore_tfawcon_ready <= (~litedramcore_tfawcon_valid);
+ end else begin
+ litedramcore_tfawcon_ready <= 1'd1;
+ end
+ end
+ if (litedramcore_tccdcon_valid) begin
+ litedramcore_tccdcon_count <= 1'd1;
+ if (1'd0) begin
+ litedramcore_tccdcon_ready <= 1'd1;
+ end else begin
+ litedramcore_tccdcon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~litedramcore_tccdcon_ready)) begin
+ litedramcore_tccdcon_count <= (litedramcore_tccdcon_count - 1'd1);
+ if ((litedramcore_tccdcon_count == 1'd1)) begin
+ litedramcore_tccdcon_ready <= 1'd1;
+ end
+ end
+ end
+ if (litedramcore_twtrcon_valid) begin
+ litedramcore_twtrcon_count <= 3'd6;
+ if (1'd0) begin
+ litedramcore_twtrcon_ready <= 1'd1;
+ end else begin
+ litedramcore_twtrcon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~litedramcore_twtrcon_ready)) begin
+ litedramcore_twtrcon_count <= (litedramcore_twtrcon_count - 1'd1);
+ if ((litedramcore_twtrcon_count == 1'd1)) begin
+ litedramcore_twtrcon_ready <= 1'd1;
+ end
+ end
+ end
+ litedramcore_multiplexer_state <= litedramcore_multiplexer_next_state;
+ litedramcore_new_master_wdata_ready0 <= ((((((((1'd0 | ((litedramcore_roundrobin0_grant == 1'd0) & litedramcore_interface_bank0_wdata_ready)) | ((litedramcore_roundrobin1_grant == 1'd0) & litedramcore_interface_bank1_wdata_ready)) | ((litedramcore_roundrobin2_grant == 1'd0) & litedramcore_interface_bank2_wdata_ready)) | ((litedramcore_roundrobin3_grant == 1'd0) & litedramcore_interface_bank3_wdata_ready)) | ((litedramcore_roundrobin4_grant == 1'd0) & litedramcore_interface_bank4_wdata_ready)) | ((litedramcore_roundrobin5_grant == 1'd0) & litedramcore_interface_bank5_wdata_ready)) | ((litedramcore_roundrobin6_grant == 1'd0) & litedramcore_interface_bank6_wdata_ready)) | ((litedramcore_roundrobin7_grant == 1'd0) & litedramcore_interface_bank7_wdata_ready));
+ litedramcore_new_master_wdata_ready1 <= litedramcore_new_master_wdata_ready0;
+ litedramcore_new_master_wdata_ready2 <= litedramcore_new_master_wdata_ready1;
+ litedramcore_new_master_wdata_ready3 <= litedramcore_new_master_wdata_ready2;
+ litedramcore_new_master_rdata_valid0 <= ((((((((1'd0 | ((litedramcore_roundrobin0_grant == 1'd0) & litedramcore_interface_bank0_rdata_valid)) | ((litedramcore_roundrobin1_grant == 1'd0) & litedramcore_interface_bank1_rdata_valid)) | ((litedramcore_roundrobin2_grant == 1'd0) & litedramcore_interface_bank2_rdata_valid)) | ((litedramcore_roundrobin3_grant == 1'd0) & litedramcore_interface_bank3_rdata_valid)) | ((litedramcore_roundrobin4_grant == 1'd0) & litedramcore_interface_bank4_rdata_valid)) | ((litedramcore_roundrobin5_grant == 1'd0) & litedramcore_interface_bank5_rdata_valid)) | ((litedramcore_roundrobin6_grant == 1'd0) & litedramcore_interface_bank6_rdata_valid)) | ((litedramcore_roundrobin7_grant == 1'd0) & litedramcore_interface_bank7_rdata_valid));
+ litedramcore_new_master_rdata_valid1 <= litedramcore_new_master_rdata_valid0;
+ litedramcore_new_master_rdata_valid2 <= litedramcore_new_master_rdata_valid1;
+ litedramcore_new_master_rdata_valid3 <= litedramcore_new_master_rdata_valid2;
+ litedramcore_new_master_rdata_valid4 <= litedramcore_new_master_rdata_valid3;
+ litedramcore_new_master_rdata_valid5 <= litedramcore_new_master_rdata_valid4;
+ litedramcore_new_master_rdata_valid6 <= litedramcore_new_master_rdata_valid5;
+ litedramcore_new_master_rdata_valid7 <= litedramcore_new_master_rdata_valid6;
+ litedramcore_new_master_rdata_valid8 <= litedramcore_new_master_rdata_valid7;
+ litedramcore_new_master_rdata_valid9 <= litedramcore_new_master_rdata_valid8;
+ litedramcore_new_master_rdata_valid10 <= litedramcore_new_master_rdata_valid9;
+ litedramcore_new_master_rdata_valid11 <= litedramcore_new_master_rdata_valid10;
+ litedramcore_new_master_rdata_valid12 <= litedramcore_new_master_rdata_valid11;
+ litedramcore_new_master_rdata_valid13 <= litedramcore_new_master_rdata_valid12;
+ state <= next_state;
+ if (litedramcore_dat_w_next_value_ce0) begin
+ litedramcore_dat_w <= litedramcore_dat_w_next_value0;
+ end
+ if (litedramcore_adr_next_value_ce1) begin
+ litedramcore_adr <= litedramcore_adr_next_value1;
+ end
+ if (litedramcore_we_next_value_ce2) begin
+ litedramcore_we <= litedramcore_we_next_value2;
+ end
+ interface0_bank_bus_dat_r <= 1'd0;
+ if (csrbank0_sel) begin
+ case (interface0_bank_bus_adr[8:0])
+ 1'd0: begin
+ interface0_bank_bus_dat_r <= csrbank0_init_done0_w;
+ end
+ 1'd1: begin
+ interface0_bank_bus_dat_r <= csrbank0_init_error0_w;
+ end
+ endcase
+ end
+ if (csrbank0_init_done0_re) begin
+ init_done_storage <= csrbank0_init_done0_r;
+ end
+ init_done_re <= csrbank0_init_done0_re;
+ if (csrbank0_init_error0_re) begin
+ init_error_storage <= csrbank0_init_error0_r;
+ end
+ init_error_re <= csrbank0_init_error0_re;
+ interface1_bank_bus_dat_r <= 1'd0;
+ if (csrbank1_sel) begin
+ case (interface1_bank_bus_adr[8:0])
+ 1'd0: begin
+ interface1_bank_bus_dat_r <= csrbank1_dly_sel0_w;
+ end
+ 1'd1: begin
+ interface1_bank_bus_dat_r <= ddrphy_rdly_dq_rst_w;
+ end
+ 2'd2: begin
+ interface1_bank_bus_dat_r <= ddrphy_rdly_dq_inc_w;
+ end
+ 2'd3: begin
+ interface1_bank_bus_dat_r <= ddrphy_rdly_dq_bitslip_rst_w;
+ end
+ 3'd4: begin
+ interface1_bank_bus_dat_r <= ddrphy_rdly_dq_bitslip_w;
+ end
+ 3'd5: begin
+ interface1_bank_bus_dat_r <= ddrphy_burstdet_clr_w;
+ end
+ 3'd6: begin
+ interface1_bank_bus_dat_r <= csrbank1_burstdet_seen_w;
+ end
+ endcase
+ end
+ if (csrbank1_dly_sel0_re) begin
+ ddrphy_dly_sel_storage[3:0] <= csrbank1_dly_sel0_r;
+ end
+ ddrphy_dly_sel_re <= csrbank1_dly_sel0_re;
+ ddrphy_burstdet_seen_re <= csrbank1_burstdet_seen_re;
+ interface2_bank_bus_dat_r <= 1'd0;
+ if (csrbank2_sel) begin
+ case (interface2_bank_bus_adr[8:0])
+ 1'd0: begin
+ interface2_bank_bus_dat_r <= csrbank2_dfii_control0_w;
+ end
+ 1'd1: begin
+ interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_command0_w;
+ end
+ 2'd2: begin
+ interface2_bank_bus_dat_r <= litedramcore_phaseinjector0_command_issue_w;
+ end
+ 2'd3: begin
+ interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_address0_w;
+ end
+ 3'd4: begin
+ interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_baddress0_w;
+ end
+ 3'd5: begin
+ interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_wrdata3_w;
+ end
+ 3'd6: begin
+ interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_wrdata2_w;
+ end
+ 3'd7: begin
+ interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_wrdata1_w;
+ end
+ 4'd8: begin
+ interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_wrdata0_w;
+ end
+ 4'd9: begin
+ interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_rddata3_w;
+ end
+ 4'd10: begin
+ interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_rddata2_w;
+ end
+ 4'd11: begin
+ interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_rddata1_w;
+ end
+ 4'd12: begin
+ interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_rddata0_w;
+ end
+ 4'd13: begin
+ interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_command0_w;
+ end
+ 4'd14: begin
+ interface2_bank_bus_dat_r <= litedramcore_phaseinjector1_command_issue_w;
+ end
+ 4'd15: begin
+ interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_address0_w;
+ end
+ 5'd16: begin
+ interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_baddress0_w;
+ end
+ 5'd17: begin
+ interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_wrdata3_w;
+ end
+ 5'd18: begin
+ interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_wrdata2_w;
+ end
+ 5'd19: begin
+ interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_wrdata1_w;
+ end
+ 5'd20: begin
+ interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_wrdata0_w;
+ end
+ 5'd21: begin
+ interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_rddata3_w;
+ end
+ 5'd22: begin
+ interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_rddata2_w;
+ end
+ 5'd23: begin
+ interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_rddata1_w;
+ end
+ 5'd24: begin
+ interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_rddata0_w;
+ end
+ endcase
+ end
+ if (csrbank2_dfii_control0_re) begin
+ litedramcore_storage[3:0] <= csrbank2_dfii_control0_r;
+ end
+ litedramcore_re <= csrbank2_dfii_control0_re;
+ if (csrbank2_dfii_pi0_command0_re) begin
+ litedramcore_phaseinjector0_command_storage[5:0] <= csrbank2_dfii_pi0_command0_r;
+ end
+ litedramcore_phaseinjector0_command_re <= csrbank2_dfii_pi0_command0_re;
+ if (csrbank2_dfii_pi0_address0_re) begin
+ litedramcore_phaseinjector0_address_storage[14:0] <= csrbank2_dfii_pi0_address0_r;
+ end
+ litedramcore_phaseinjector0_address_re <= csrbank2_dfii_pi0_address0_re;
+ if (csrbank2_dfii_pi0_baddress0_re) begin
+ litedramcore_phaseinjector0_baddress_storage[2:0] <= csrbank2_dfii_pi0_baddress0_r;
+ end
+ litedramcore_phaseinjector0_baddress_re <= csrbank2_dfii_pi0_baddress0_re;
+ if (csrbank2_dfii_pi0_wrdata3_re) begin
+ litedramcore_phaseinjector0_wrdata_storage[127:96] <= csrbank2_dfii_pi0_wrdata3_r;
+ end
+ if (csrbank2_dfii_pi0_wrdata2_re) begin
+ litedramcore_phaseinjector0_wrdata_storage[95:64] <= csrbank2_dfii_pi0_wrdata2_r;
+ end
+ if (csrbank2_dfii_pi0_wrdata1_re) begin
+ litedramcore_phaseinjector0_wrdata_storage[63:32] <= csrbank2_dfii_pi0_wrdata1_r;
+ end
+ if (csrbank2_dfii_pi0_wrdata0_re) begin
+ litedramcore_phaseinjector0_wrdata_storage[31:0] <= csrbank2_dfii_pi0_wrdata0_r;
+ end
+ litedramcore_phaseinjector0_wrdata_re <= csrbank2_dfii_pi0_wrdata0_re;
+ litedramcore_phaseinjector0_rddata_re <= csrbank2_dfii_pi0_rddata0_re;
+ if (csrbank2_dfii_pi1_command0_re) begin
+ litedramcore_phaseinjector1_command_storage[5:0] <= csrbank2_dfii_pi1_command0_r;
+ end
+ litedramcore_phaseinjector1_command_re <= csrbank2_dfii_pi1_command0_re;
+ if (csrbank2_dfii_pi1_address0_re) begin
+ litedramcore_phaseinjector1_address_storage[14:0] <= csrbank2_dfii_pi1_address0_r;
+ end
+ litedramcore_phaseinjector1_address_re <= csrbank2_dfii_pi1_address0_re;
+ if (csrbank2_dfii_pi1_baddress0_re) begin
+ litedramcore_phaseinjector1_baddress_storage[2:0] <= csrbank2_dfii_pi1_baddress0_r;
+ end
+ litedramcore_phaseinjector1_baddress_re <= csrbank2_dfii_pi1_baddress0_re;
+ if (csrbank2_dfii_pi1_wrdata3_re) begin
+ litedramcore_phaseinjector1_wrdata_storage[127:96] <= csrbank2_dfii_pi1_wrdata3_r;
+ end
+ if (csrbank2_dfii_pi1_wrdata2_re) begin
+ litedramcore_phaseinjector1_wrdata_storage[95:64] <= csrbank2_dfii_pi1_wrdata2_r;
+ end
+ if (csrbank2_dfii_pi1_wrdata1_re) begin
+ litedramcore_phaseinjector1_wrdata_storage[63:32] <= csrbank2_dfii_pi1_wrdata1_r;
+ end
+ if (csrbank2_dfii_pi1_wrdata0_re) begin
+ litedramcore_phaseinjector1_wrdata_storage[31:0] <= csrbank2_dfii_pi1_wrdata0_r;
+ end
+ litedramcore_phaseinjector1_wrdata_re <= csrbank2_dfii_pi1_wrdata0_re;
+ litedramcore_phaseinjector1_rddata_re <= csrbank2_dfii_pi1_rddata0_re;
+ if (sys_rst) begin
+ ddrphy_dly_sel_storage <= 4'd0;
+ ddrphy_dly_sel_re <= 1'd0;
+ ddrphy_burstdet_seen_status <= 4'd0;
+ ddrphy_burstdet_seen_re <= 1'd0;
+ ddrphy_rdly0 <= 7'd0;
+ ddrphy_burstdet_d0 <= 1'd0;
+ ddrphy_dm_o_data_d0 <= 8'd0;
+ ddrphy_dm_o_data_muxed0 <= 4'd0;
+ ddrphy_dq_o_data_d0 <= 8'd0;
+ ddrphy_dq_o_data_muxed0 <= 4'd0;
+ ddrphy_bitslip0_value <= 2'd0;
+ ddrphy_dq_i_bitslip_o_d0 <= 4'd0;
+ ddrphy_dq_o_data_d1 <= 8'd0;
+ ddrphy_dq_o_data_muxed1 <= 4'd0;
+ ddrphy_bitslip1_value <= 2'd0;
+ ddrphy_dq_i_bitslip_o_d1 <= 4'd0;
+ ddrphy_dq_o_data_d2 <= 8'd0;
+ ddrphy_dq_o_data_muxed2 <= 4'd0;
+ ddrphy_bitslip2_value <= 2'd0;
+ ddrphy_dq_i_bitslip_o_d2 <= 4'd0;
+ ddrphy_dq_o_data_d3 <= 8'd0;
+ ddrphy_dq_o_data_muxed3 <= 4'd0;
+ ddrphy_bitslip3_value <= 2'd0;
+ ddrphy_dq_i_bitslip_o_d3 <= 4'd0;
+ ddrphy_dq_o_data_d4 <= 8'd0;
+ ddrphy_dq_o_data_muxed4 <= 4'd0;
+ ddrphy_bitslip4_value <= 2'd0;
+ ddrphy_dq_i_bitslip_o_d4 <= 4'd0;
+ ddrphy_dq_o_data_d5 <= 8'd0;
+ ddrphy_dq_o_data_muxed5 <= 4'd0;
+ ddrphy_bitslip5_value <= 2'd0;
+ ddrphy_dq_i_bitslip_o_d5 <= 4'd0;
+ ddrphy_dq_o_data_d6 <= 8'd0;
+ ddrphy_dq_o_data_muxed6 <= 4'd0;
+ ddrphy_bitslip6_value <= 2'd0;
+ ddrphy_dq_i_bitslip_o_d6 <= 4'd0;
+ ddrphy_dq_o_data_d7 <= 8'd0;
+ ddrphy_dq_o_data_muxed7 <= 4'd0;
+ ddrphy_bitslip7_value <= 2'd0;
+ ddrphy_dq_i_bitslip_o_d7 <= 4'd0;
+ ddrphy_rdly1 <= 7'd0;
+ ddrphy_burstdet_d1 <= 1'd0;
+ ddrphy_dm_o_data_d1 <= 8'd0;
+ ddrphy_dm_o_data_muxed1 <= 4'd0;
+ ddrphy_dq_o_data_d8 <= 8'd0;
+ ddrphy_dq_o_data_muxed8 <= 4'd0;
+ ddrphy_bitslip8_value <= 2'd0;
+ ddrphy_dq_i_bitslip_o_d8 <= 4'd0;
+ ddrphy_dq_o_data_d9 <= 8'd0;
+ ddrphy_dq_o_data_muxed9 <= 4'd0;
+ ddrphy_bitslip9_value <= 2'd0;
+ ddrphy_dq_i_bitslip_o_d9 <= 4'd0;
+ ddrphy_dq_o_data_d10 <= 8'd0;
+ ddrphy_dq_o_data_muxed10 <= 4'd0;
+ ddrphy_bitslip10_value <= 2'd0;
+ ddrphy_dq_i_bitslip_o_d10 <= 4'd0;
+ ddrphy_dq_o_data_d11 <= 8'd0;
+ ddrphy_dq_o_data_muxed11 <= 4'd0;
+ ddrphy_bitslip11_value <= 2'd0;
+ ddrphy_dq_i_bitslip_o_d11 <= 4'd0;
+ ddrphy_dq_o_data_d12 <= 8'd0;
+ ddrphy_dq_o_data_muxed12 <= 4'd0;
+ ddrphy_bitslip12_value <= 2'd0;
+ ddrphy_dq_i_bitslip_o_d12 <= 4'd0;
+ ddrphy_dq_o_data_d13 <= 8'd0;
+ ddrphy_dq_o_data_muxed13 <= 4'd0;
+ ddrphy_bitslip13_value <= 2'd0;
+ ddrphy_dq_i_bitslip_o_d13 <= 4'd0;
+ ddrphy_dq_o_data_d14 <= 8'd0;
+ ddrphy_dq_o_data_muxed14 <= 4'd0;
+ ddrphy_bitslip14_value <= 2'd0;
+ ddrphy_dq_i_bitslip_o_d14 <= 4'd0;
+ ddrphy_dq_o_data_d15 <= 8'd0;
+ ddrphy_dq_o_data_muxed15 <= 4'd0;
+ ddrphy_bitslip15_value <= 2'd0;
+ ddrphy_dq_i_bitslip_o_d15 <= 4'd0;
+ ddrphy_rdly2 <= 7'd0;
+ ddrphy_burstdet_d2 <= 1'd0;
+ ddrphy_dm_o_data_d2 <= 8'd0;
+ ddrphy_dm_o_data_muxed2 <= 4'd0;
+ ddrphy_dq_o_data_d16 <= 8'd0;
+ ddrphy_dq_o_data_muxed16 <= 4'd0;
+ ddrphy_bitslip16_value <= 2'd0;
+ ddrphy_dq_i_bitslip_o_d16 <= 4'd0;
+ ddrphy_dq_o_data_d17 <= 8'd0;
+ ddrphy_dq_o_data_muxed17 <= 4'd0;
+ ddrphy_bitslip17_value <= 2'd0;
+ ddrphy_dq_i_bitslip_o_d17 <= 4'd0;
+ ddrphy_dq_o_data_d18 <= 8'd0;
+ ddrphy_dq_o_data_muxed18 <= 4'd0;
+ ddrphy_bitslip18_value <= 2'd0;
+ ddrphy_dq_i_bitslip_o_d18 <= 4'd0;
+ ddrphy_dq_o_data_d19 <= 8'd0;
+ ddrphy_dq_o_data_muxed19 <= 4'd0;
+ ddrphy_bitslip19_value <= 2'd0;
+ ddrphy_dq_i_bitslip_o_d19 <= 4'd0;
+ ddrphy_dq_o_data_d20 <= 8'd0;
+ ddrphy_dq_o_data_muxed20 <= 4'd0;
+ ddrphy_bitslip20_value <= 2'd0;
+ ddrphy_dq_i_bitslip_o_d20 <= 4'd0;
+ ddrphy_dq_o_data_d21 <= 8'd0;
+ ddrphy_dq_o_data_muxed21 <= 4'd0;
+ ddrphy_bitslip21_value <= 2'd0;
+ ddrphy_dq_i_bitslip_o_d21 <= 4'd0;
+ ddrphy_dq_o_data_d22 <= 8'd0;
+ ddrphy_dq_o_data_muxed22 <= 4'd0;
+ ddrphy_bitslip22_value <= 2'd0;
+ ddrphy_dq_i_bitslip_o_d22 <= 4'd0;
+ ddrphy_dq_o_data_d23 <= 8'd0;
+ ddrphy_dq_o_data_muxed23 <= 4'd0;
+ ddrphy_bitslip23_value <= 2'd0;
+ ddrphy_dq_i_bitslip_o_d23 <= 4'd0;
+ ddrphy_rdly3 <= 7'd0;
+ ddrphy_burstdet_d3 <= 1'd0;
+ ddrphy_dm_o_data_d3 <= 8'd0;
+ ddrphy_dm_o_data_muxed3 <= 4'd0;
+ ddrphy_dq_o_data_d24 <= 8'd0;
+ ddrphy_dq_o_data_muxed24 <= 4'd0;
+ ddrphy_bitslip24_value <= 2'd0;
+ ddrphy_dq_i_bitslip_o_d24 <= 4'd0;
+ ddrphy_dq_o_data_d25 <= 8'd0;
+ ddrphy_dq_o_data_muxed25 <= 4'd0;
+ ddrphy_bitslip25_value <= 2'd0;
+ ddrphy_dq_i_bitslip_o_d25 <= 4'd0;
+ ddrphy_dq_o_data_d26 <= 8'd0;
+ ddrphy_dq_o_data_muxed26 <= 4'd0;
+ ddrphy_bitslip26_value <= 2'd0;
+ ddrphy_dq_i_bitslip_o_d26 <= 4'd0;
+ ddrphy_dq_o_data_d27 <= 8'd0;
+ ddrphy_dq_o_data_muxed27 <= 4'd0;
+ ddrphy_bitslip27_value <= 2'd0;
+ ddrphy_dq_i_bitslip_o_d27 <= 4'd0;
+ ddrphy_dq_o_data_d28 <= 8'd0;
+ ddrphy_dq_o_data_muxed28 <= 4'd0;
+ ddrphy_bitslip28_value <= 2'd0;
+ ddrphy_dq_i_bitslip_o_d28 <= 4'd0;
+ ddrphy_dq_o_data_d29 <= 8'd0;
+ ddrphy_dq_o_data_muxed29 <= 4'd0;
+ ddrphy_bitslip29_value <= 2'd0;
+ ddrphy_dq_i_bitslip_o_d29 <= 4'd0;
+ ddrphy_dq_o_data_d30 <= 8'd0;
+ ddrphy_dq_o_data_muxed30 <= 4'd0;
+ ddrphy_bitslip30_value <= 2'd0;
+ ddrphy_dq_i_bitslip_o_d30 <= 4'd0;
+ ddrphy_dq_o_data_d31 <= 8'd0;
+ ddrphy_dq_o_data_muxed31 <= 4'd0;
+ ddrphy_bitslip31_value <= 2'd0;
+ ddrphy_dq_i_bitslip_o_d31 <= 4'd0;
+ ddrphy_rddata_en_tappeddelayline0 <= 1'd0;
+ ddrphy_rddata_en_tappeddelayline1 <= 1'd0;
+ ddrphy_rddata_en_tappeddelayline2 <= 1'd0;
+ ddrphy_rddata_en_tappeddelayline3 <= 1'd0;
+ ddrphy_rddata_en_tappeddelayline4 <= 1'd0;
+ ddrphy_rddata_en_tappeddelayline5 <= 1'd0;
+ ddrphy_rddata_en_tappeddelayline6 <= 1'd0;
+ ddrphy_rddata_en_tappeddelayline7 <= 1'd0;
+ ddrphy_rddata_en_tappeddelayline8 <= 1'd0;
+ ddrphy_rddata_en_tappeddelayline9 <= 1'd0;
+ ddrphy_rddata_en_tappeddelayline10 <= 1'd0;
+ ddrphy_rddata_en_tappeddelayline11 <= 1'd0;
+ ddrphy_rddata_en_tappeddelayline12 <= 1'd0;
+ ddrphy_wrdata_en_tappeddelayline0 <= 1'd0;
+ ddrphy_wrdata_en_tappeddelayline1 <= 1'd0;
+ ddrphy_wrdata_en_tappeddelayline2 <= 1'd0;
+ ddrphy_wrdata_en_tappeddelayline3 <= 1'd0;
+ ddrphy_wrdata_en_tappeddelayline4 <= 1'd0;
+ ddrphy_wrdata_en_tappeddelayline5 <= 1'd0;
+ ddrphy_wrdata_en_tappeddelayline6 <= 1'd0;
+ litedramcore_storage <= 4'd1;
+ litedramcore_re <= 1'd0;
+ litedramcore_phaseinjector0_command_storage <= 6'd0;
+ litedramcore_phaseinjector0_command_re <= 1'd0;
+ litedramcore_phaseinjector0_address_re <= 1'd0;
+ litedramcore_phaseinjector0_baddress_re <= 1'd0;
+ litedramcore_phaseinjector0_wrdata_re <= 1'd0;
+ litedramcore_phaseinjector0_rddata_status <= 128'd0;
+ litedramcore_phaseinjector0_rddata_re <= 1'd0;
+ litedramcore_phaseinjector1_command_storage <= 6'd0;
+ litedramcore_phaseinjector1_command_re <= 1'd0;
+ litedramcore_phaseinjector1_address_re <= 1'd0;
+ litedramcore_phaseinjector1_baddress_re <= 1'd0;
+ litedramcore_phaseinjector1_wrdata_re <= 1'd0;
+ litedramcore_phaseinjector1_rddata_status <= 128'd0;
+ litedramcore_phaseinjector1_rddata_re <= 1'd0;
+ litedramcore_dfi_p0_address <= 15'd0;
+ litedramcore_dfi_p0_bank <= 3'd0;
+ litedramcore_dfi_p0_cas_n <= 1'd1;
+ litedramcore_dfi_p0_cs_n <= 1'd1;
+ litedramcore_dfi_p0_ras_n <= 1'd1;
+ litedramcore_dfi_p0_we_n <= 1'd1;
+ litedramcore_dfi_p0_wrdata_en <= 1'd0;
+ litedramcore_dfi_p0_rddata_en <= 1'd0;
+ litedramcore_dfi_p1_address <= 15'd0;
+ litedramcore_dfi_p1_bank <= 3'd0;
+ litedramcore_dfi_p1_cas_n <= 1'd1;
+ litedramcore_dfi_p1_cs_n <= 1'd1;
+ litedramcore_dfi_p1_ras_n <= 1'd1;
+ litedramcore_dfi_p1_we_n <= 1'd1;
+ litedramcore_dfi_p1_wrdata_en <= 1'd0;
+ litedramcore_dfi_p1_rddata_en <= 1'd0;
+ litedramcore_cmd_payload_a <= 15'd0;
+ litedramcore_cmd_payload_ba <= 3'd0;
+ litedramcore_cmd_payload_cas <= 1'd0;
+ litedramcore_cmd_payload_ras <= 1'd0;
+ litedramcore_cmd_payload_we <= 1'd0;
+ litedramcore_timer_count1 <= 9'd374;
+ litedramcore_postponer_req_o <= 1'd0;
+ litedramcore_postponer_count <= 1'd0;
+ litedramcore_sequencer_done1 <= 1'd0;
+ litedramcore_sequencer_counter <= 7'd0;
+ litedramcore_sequencer_count <= 1'd0;
+ litedramcore_zqcs_timer_count1 <= 26'd47999999;
+ litedramcore_zqcs_executer_done <= 1'd0;
+ litedramcore_zqcs_executer_counter <= 6'd0;
+ litedramcore_bankmachine0_cmd_buffer_lookahead_level <= 5'd0;
+ litedramcore_bankmachine0_cmd_buffer_lookahead_produce <= 4'd0;
+ litedramcore_bankmachine0_cmd_buffer_lookahead_consume <= 4'd0;
+ litedramcore_bankmachine0_cmd_buffer_source_valid <= 1'd0;
+ litedramcore_bankmachine0_cmd_buffer_source_payload_we <= 1'd0;
+ litedramcore_bankmachine0_cmd_buffer_source_payload_addr <= 22'd0;
+ litedramcore_bankmachine0_row <= 15'd0;
+ litedramcore_bankmachine0_row_opened <= 1'd0;
+ litedramcore_bankmachine0_twtpcon_ready <= 1'd0;
+ litedramcore_bankmachine0_twtpcon_count <= 3'd0;
+ litedramcore_bankmachine0_trccon_ready <= 1'd0;
+ litedramcore_bankmachine0_trccon_count <= 2'd0;
+ litedramcore_bankmachine0_trascon_ready <= 1'd0;
+ litedramcore_bankmachine0_trascon_count <= 2'd0;
+ litedramcore_bankmachine1_cmd_buffer_lookahead_level <= 5'd0;
+ litedramcore_bankmachine1_cmd_buffer_lookahead_produce <= 4'd0;
+ litedramcore_bankmachine1_cmd_buffer_lookahead_consume <= 4'd0;
+ litedramcore_bankmachine1_cmd_buffer_source_valid <= 1'd0;
+ litedramcore_bankmachine1_cmd_buffer_source_payload_we <= 1'd0;
+ litedramcore_bankmachine1_cmd_buffer_source_payload_addr <= 22'd0;
+ litedramcore_bankmachine1_row <= 15'd0;
+ litedramcore_bankmachine1_row_opened <= 1'd0;
+ litedramcore_bankmachine1_twtpcon_ready <= 1'd0;
+ litedramcore_bankmachine1_twtpcon_count <= 3'd0;
+ litedramcore_bankmachine1_trccon_ready <= 1'd0;
+ litedramcore_bankmachine1_trccon_count <= 2'd0;
+ litedramcore_bankmachine1_trascon_ready <= 1'd0;
+ litedramcore_bankmachine1_trascon_count <= 2'd0;
+ litedramcore_bankmachine2_cmd_buffer_lookahead_level <= 5'd0;
+ litedramcore_bankmachine2_cmd_buffer_lookahead_produce <= 4'd0;
+ litedramcore_bankmachine2_cmd_buffer_lookahead_consume <= 4'd0;
+ litedramcore_bankmachine2_cmd_buffer_source_valid <= 1'd0;
+ litedramcore_bankmachine2_cmd_buffer_source_payload_we <= 1'd0;
+ litedramcore_bankmachine2_cmd_buffer_source_payload_addr <= 22'd0;
+ litedramcore_bankmachine2_row <= 15'd0;
+ litedramcore_bankmachine2_row_opened <= 1'd0;
+ litedramcore_bankmachine2_twtpcon_ready <= 1'd0;
+ litedramcore_bankmachine2_twtpcon_count <= 3'd0;
+ litedramcore_bankmachine2_trccon_ready <= 1'd0;
+ litedramcore_bankmachine2_trccon_count <= 2'd0;
+ litedramcore_bankmachine2_trascon_ready <= 1'd0;
+ litedramcore_bankmachine2_trascon_count <= 2'd0;
+ litedramcore_bankmachine3_cmd_buffer_lookahead_level <= 5'd0;
+ litedramcore_bankmachine3_cmd_buffer_lookahead_produce <= 4'd0;
+ litedramcore_bankmachine3_cmd_buffer_lookahead_consume <= 4'd0;
+ litedramcore_bankmachine3_cmd_buffer_source_valid <= 1'd0;
+ litedramcore_bankmachine3_cmd_buffer_source_payload_we <= 1'd0;
+ litedramcore_bankmachine3_cmd_buffer_source_payload_addr <= 22'd0;
+ litedramcore_bankmachine3_row <= 15'd0;
+ litedramcore_bankmachine3_row_opened <= 1'd0;
+ litedramcore_bankmachine3_twtpcon_ready <= 1'd0;
+ litedramcore_bankmachine3_twtpcon_count <= 3'd0;
+ litedramcore_bankmachine3_trccon_ready <= 1'd0;
+ litedramcore_bankmachine3_trccon_count <= 2'd0;
+ litedramcore_bankmachine3_trascon_ready <= 1'd0;
+ litedramcore_bankmachine3_trascon_count <= 2'd0;
+ litedramcore_bankmachine4_cmd_buffer_lookahead_level <= 5'd0;
+ litedramcore_bankmachine4_cmd_buffer_lookahead_produce <= 4'd0;
+ litedramcore_bankmachine4_cmd_buffer_lookahead_consume <= 4'd0;
+ litedramcore_bankmachine4_cmd_buffer_source_valid <= 1'd0;
+ litedramcore_bankmachine4_cmd_buffer_source_payload_we <= 1'd0;
+ litedramcore_bankmachine4_cmd_buffer_source_payload_addr <= 22'd0;
+ litedramcore_bankmachine4_row <= 15'd0;
+ litedramcore_bankmachine4_row_opened <= 1'd0;
+ litedramcore_bankmachine4_twtpcon_ready <= 1'd0;
+ litedramcore_bankmachine4_twtpcon_count <= 3'd0;
+ litedramcore_bankmachine4_trccon_ready <= 1'd0;
+ litedramcore_bankmachine4_trccon_count <= 2'd0;
+ litedramcore_bankmachine4_trascon_ready <= 1'd0;
+ litedramcore_bankmachine4_trascon_count <= 2'd0;
+ litedramcore_bankmachine5_cmd_buffer_lookahead_level <= 5'd0;
+ litedramcore_bankmachine5_cmd_buffer_lookahead_produce <= 4'd0;
+ litedramcore_bankmachine5_cmd_buffer_lookahead_consume <= 4'd0;
+ litedramcore_bankmachine5_cmd_buffer_source_valid <= 1'd0;
+ litedramcore_bankmachine5_cmd_buffer_source_payload_we <= 1'd0;
+ litedramcore_bankmachine5_cmd_buffer_source_payload_addr <= 22'd0;
+ litedramcore_bankmachine5_row <= 15'd0;
+ litedramcore_bankmachine5_row_opened <= 1'd0;
+ litedramcore_bankmachine5_twtpcon_ready <= 1'd0;
+ litedramcore_bankmachine5_twtpcon_count <= 3'd0;
+ litedramcore_bankmachine5_trccon_ready <= 1'd0;
+ litedramcore_bankmachine5_trccon_count <= 2'd0;
+ litedramcore_bankmachine5_trascon_ready <= 1'd0;
+ litedramcore_bankmachine5_trascon_count <= 2'd0;
+ litedramcore_bankmachine6_cmd_buffer_lookahead_level <= 5'd0;
+ litedramcore_bankmachine6_cmd_buffer_lookahead_produce <= 4'd0;
+ litedramcore_bankmachine6_cmd_buffer_lookahead_consume <= 4'd0;
+ litedramcore_bankmachine6_cmd_buffer_source_valid <= 1'd0;
+ litedramcore_bankmachine6_cmd_buffer_source_payload_we <= 1'd0;
+ litedramcore_bankmachine6_cmd_buffer_source_payload_addr <= 22'd0;
+ litedramcore_bankmachine6_row <= 15'd0;
+ litedramcore_bankmachine6_row_opened <= 1'd0;
+ litedramcore_bankmachine6_twtpcon_ready <= 1'd0;
+ litedramcore_bankmachine6_twtpcon_count <= 3'd0;
+ litedramcore_bankmachine6_trccon_ready <= 1'd0;
+ litedramcore_bankmachine6_trccon_count <= 2'd0;
+ litedramcore_bankmachine6_trascon_ready <= 1'd0;
+ litedramcore_bankmachine6_trascon_count <= 2'd0;
+ litedramcore_bankmachine7_cmd_buffer_lookahead_level <= 5'd0;
+ litedramcore_bankmachine7_cmd_buffer_lookahead_produce <= 4'd0;
+ litedramcore_bankmachine7_cmd_buffer_lookahead_consume <= 4'd0;
+ litedramcore_bankmachine7_cmd_buffer_source_valid <= 1'd0;
+ litedramcore_bankmachine7_cmd_buffer_source_payload_we <= 1'd0;
+ litedramcore_bankmachine7_cmd_buffer_source_payload_addr <= 22'd0;
+ litedramcore_bankmachine7_row <= 15'd0;
+ litedramcore_bankmachine7_row_opened <= 1'd0;
+ litedramcore_bankmachine7_twtpcon_ready <= 1'd0;
+ litedramcore_bankmachine7_twtpcon_count <= 3'd0;
+ litedramcore_bankmachine7_trccon_ready <= 1'd0;
+ litedramcore_bankmachine7_trccon_count <= 2'd0;
+ litedramcore_bankmachine7_trascon_ready <= 1'd0;
+ litedramcore_bankmachine7_trascon_count <= 2'd0;
+ litedramcore_choose_cmd_grant <= 3'd0;
+ litedramcore_choose_req_grant <= 3'd0;
+ litedramcore_trrdcon_ready <= 1'd0;
+ litedramcore_trrdcon_count <= 1'd0;
+ litedramcore_tfawcon_ready <= 1'd1;
+ litedramcore_tfawcon_window <= 3'd0;
+ litedramcore_tccdcon_ready <= 1'd0;
+ litedramcore_tccdcon_count <= 1'd0;
+ litedramcore_twtrcon_ready <= 1'd0;
+ litedramcore_twtrcon_count <= 3'd0;
+ litedramcore_time0 <= 5'd0;
+ litedramcore_time1 <= 4'd0;
+ init_done_storage <= 1'd0;
+ init_done_re <= 1'd0;
+ init_error_storage <= 1'd0;
+ init_error_re <= 1'd0;
+ litedramcore_refresher_state <= 2'd0;
+ litedramcore_bankmachine0_state <= 3'd0;
+ litedramcore_bankmachine1_state <= 3'd0;
+ litedramcore_bankmachine2_state <= 3'd0;
+ litedramcore_bankmachine3_state <= 3'd0;
+ litedramcore_bankmachine4_state <= 3'd0;
+ litedramcore_bankmachine5_state <= 3'd0;
+ litedramcore_bankmachine6_state <= 3'd0;
+ litedramcore_bankmachine7_state <= 3'd0;
+ litedramcore_multiplexer_state <= 4'd0;
+ litedramcore_new_master_wdata_ready0 <= 1'd0;
+ litedramcore_new_master_wdata_ready1 <= 1'd0;
+ litedramcore_new_master_wdata_ready2 <= 1'd0;
+ litedramcore_new_master_wdata_ready3 <= 1'd0;
+ litedramcore_new_master_rdata_valid0 <= 1'd0;
+ litedramcore_new_master_rdata_valid1 <= 1'd0;
+ litedramcore_new_master_rdata_valid2 <= 1'd0;
+ litedramcore_new_master_rdata_valid3 <= 1'd0;
+ litedramcore_new_master_rdata_valid4 <= 1'd0;
+ litedramcore_new_master_rdata_valid5 <= 1'd0;
+ litedramcore_new_master_rdata_valid6 <= 1'd0;
+ litedramcore_new_master_rdata_valid7 <= 1'd0;
+ litedramcore_new_master_rdata_valid8 <= 1'd0;
+ litedramcore_new_master_rdata_valid9 <= 1'd0;
+ litedramcore_new_master_rdata_valid10 <= 1'd0;
+ litedramcore_new_master_rdata_valid11 <= 1'd0;
+ litedramcore_new_master_rdata_valid12 <= 1'd0;
+ litedramcore_new_master_rdata_valid13 <= 1'd0;
+ litedramcore_we <= 1'd0;
+ state <= 2'd0;
+ end
+end
+
+
+//------------------------------------------------------------------------------
+// Specialized Logic
+//------------------------------------------------------------------------------
+
+ECLKBRIDGECS ECLKBRIDGECS(
+ .CLK0(sys2x_i_clk),
+ .SEL(1'd0),
+ .ECSOUT(crg_sys2x_clk_ecsout)
+);
+
+ECLKSYNCB ECLKSYNCB(
+ .ECLKI(crg_sys2x_clk_ecsout),
+ .STOP(crg_stop),
+ .ECLKO(sys2x_clk)
+);
+
+CLKDIVF #(
+ .DIV("2.0")
+) CLKDIVF (
+ .ALIGNWD(1'd0),
+ .CLKI(sys2x_clk),
+ .RST(crg_reset0),
+ .CDIVX(sys_clk)
+);
+
+DDRDLLA DDRDLLA(
+ .CLK(sys2x_clk),
+ .FREEZE(ddrphy_freeze),
+ .RST(init_rst),
+ .UDDCNTLN((~ddrphy_update)),
+ .DDRDEL(ddrphy_delay1),
+ .LOCK(ddrphy_lock0)
+);
+
+ODDRX2F ODDRX2F(
+ .D0(1'd0),
+ .D1(1'd1),
+ .D2(1'd0),
+ .D3(1'd1),
+ .ECLK(sys2x_clk),
+ .RST(sys_rst),
+ .SCLK(sys_clk),
+ .Q(ddrphy_pad_oddrx2f0)
+);
+
+DELAYG #(
+ .DEL_VALUE(7'd100)
+) DELAYG (
+ .A(ddrphy_pad_oddrx2f0),
+ .Z(ddram_clk_p[0])
+);
+
+ODDRX2F ODDRX2F_1(
+ .D0(1'd0),
+ .D1(1'd1),
+ .D2(1'd0),
+ .D3(1'd1),
+ .ECLK(sys2x_clk),
+ .RST(sys_rst),
+ .SCLK(sys_clk),
+ .Q(ddrphy_pad_oddrx2f1)
+);
+
+DELAYG #(
+ .DEL_VALUE(7'd100)
+) DELAYG_1 (
+ .A(ddrphy_pad_oddrx2f1),
+ .Z(ddram_clk_p[1])
+);
+
+ODDRX2F ODDRX2F_2(
+ .D0(ddrphy_dfi_p0_reset_n),
+ .D1(ddrphy_dfi_p0_reset_n),
+ .D2(ddrphy_dfi_p1_reset_n),
+ .D3(ddrphy_dfi_p1_reset_n),
+ .ECLK(sys2x_clk),
+ .RST(sys_rst),
+ .SCLK(sys_clk),
+ .Q(ddrphy_pad_oddrx2f2)
+);
+
+DELAYG #(
+ .DEL_VALUE(7'd100)
+) DELAYG_2 (
+ .A(ddrphy_pad_oddrx2f2),
+ .Z(ddram_reset_n)
+);
+
+ODDRX2F ODDRX2F_3(
+ .D0(ddrphy_dfi_p0_cs_n),
+ .D1(ddrphy_dfi_p0_cs_n),
+ .D2(ddrphy_dfi_p1_cs_n),
+ .D3(ddrphy_dfi_p1_cs_n),
+ .ECLK(sys2x_clk),
+ .RST(sys_rst),
+ .SCLK(sys_clk),
+ .Q(ddrphy_pad_oddrx2f3)
+);
+
+DELAYG #(
+ .DEL_VALUE(7'd100)
+) DELAYG_3 (
+ .A(ddrphy_pad_oddrx2f3),
+ .Z(ddram_cs_n)
+);
+
+ODDRX2F ODDRX2F_4(
+ .D0(ddrphy_dfi_p0_address[0]),
+ .D1(ddrphy_dfi_p0_address[0]),
+ .D2(ddrphy_dfi_p1_address[0]),
+ .D3(ddrphy_dfi_p1_address[0]),
+ .ECLK(sys2x_clk),
+ .RST(sys_rst),
+ .SCLK(sys_clk),
+ .Q(ddrphy_pad_oddrx2f4)
+);
+
+DELAYG #(
+ .DEL_VALUE(7'd100)
+) DELAYG_4 (
+ .A(ddrphy_pad_oddrx2f4),
+ .Z(ddram_a[0])
+);
+
+ODDRX2F ODDRX2F_5(
+ .D0(ddrphy_dfi_p0_address[1]),
+ .D1(ddrphy_dfi_p0_address[1]),
+ .D2(ddrphy_dfi_p1_address[1]),
+ .D3(ddrphy_dfi_p1_address[1]),
+ .ECLK(sys2x_clk),
+ .RST(sys_rst),
+ .SCLK(sys_clk),
+ .Q(ddrphy_pad_oddrx2f5)
+);
+
+DELAYG #(
+ .DEL_VALUE(7'd100)
+) DELAYG_5 (
+ .A(ddrphy_pad_oddrx2f5),
+ .Z(ddram_a[1])
+);
+
+ODDRX2F ODDRX2F_6(
+ .D0(ddrphy_dfi_p0_address[2]),
+ .D1(ddrphy_dfi_p0_address[2]),
+ .D2(ddrphy_dfi_p1_address[2]),
+ .D3(ddrphy_dfi_p1_address[2]),
+ .ECLK(sys2x_clk),
+ .RST(sys_rst),
+ .SCLK(sys_clk),
+ .Q(ddrphy_pad_oddrx2f6)
+);
+
+DELAYG #(
+ .DEL_VALUE(7'd100)
+) DELAYG_6 (
+ .A(ddrphy_pad_oddrx2f6),
+ .Z(ddram_a[2])
+);
+
+ODDRX2F ODDRX2F_7(
+ .D0(ddrphy_dfi_p0_address[3]),
+ .D1(ddrphy_dfi_p0_address[3]),
+ .D2(ddrphy_dfi_p1_address[3]),
+ .D3(ddrphy_dfi_p1_address[3]),
+ .ECLK(sys2x_clk),
+ .RST(sys_rst),
+ .SCLK(sys_clk),
+ .Q(ddrphy_pad_oddrx2f7)
+);
+
+DELAYG #(
+ .DEL_VALUE(7'd100)
+) DELAYG_7 (
+ .A(ddrphy_pad_oddrx2f7),
+ .Z(ddram_a[3])
+);
+
+ODDRX2F ODDRX2F_8(
+ .D0(ddrphy_dfi_p0_address[4]),
+ .D1(ddrphy_dfi_p0_address[4]),
+ .D2(ddrphy_dfi_p1_address[4]),
+ .D3(ddrphy_dfi_p1_address[4]),
+ .ECLK(sys2x_clk),
+ .RST(sys_rst),
+ .SCLK(sys_clk),
+ .Q(ddrphy_pad_oddrx2f8)
+);
+
+DELAYG #(
+ .DEL_VALUE(7'd100)
+) DELAYG_8 (
+ .A(ddrphy_pad_oddrx2f8),
+ .Z(ddram_a[4])
+);
+
+ODDRX2F ODDRX2F_9(
+ .D0(ddrphy_dfi_p0_address[5]),
+ .D1(ddrphy_dfi_p0_address[5]),
+ .D2(ddrphy_dfi_p1_address[5]),
+ .D3(ddrphy_dfi_p1_address[5]),
+ .ECLK(sys2x_clk),
+ .RST(sys_rst),
+ .SCLK(sys_clk),
+ .Q(ddrphy_pad_oddrx2f9)
+);
+
+DELAYG #(
+ .DEL_VALUE(7'd100)
+) DELAYG_9 (
+ .A(ddrphy_pad_oddrx2f9),
+ .Z(ddram_a[5])
+);
+
+ODDRX2F ODDRX2F_10(
+ .D0(ddrphy_dfi_p0_address[6]),
+ .D1(ddrphy_dfi_p0_address[6]),
+ .D2(ddrphy_dfi_p1_address[6]),
+ .D3(ddrphy_dfi_p1_address[6]),
+ .ECLK(sys2x_clk),
+ .RST(sys_rst),
+ .SCLK(sys_clk),
+ .Q(ddrphy_pad_oddrx2f10)
+);
+
+DELAYG #(
+ .DEL_VALUE(7'd100)
+) DELAYG_10 (
+ .A(ddrphy_pad_oddrx2f10),
+ .Z(ddram_a[6])
+);
+
+ODDRX2F ODDRX2F_11(
+ .D0(ddrphy_dfi_p0_address[7]),
+ .D1(ddrphy_dfi_p0_address[7]),
+ .D2(ddrphy_dfi_p1_address[7]),
+ .D3(ddrphy_dfi_p1_address[7]),
+ .ECLK(sys2x_clk),
+ .RST(sys_rst),
+ .SCLK(sys_clk),
+ .Q(ddrphy_pad_oddrx2f11)
+);
+
+DELAYG #(
+ .DEL_VALUE(7'd100)
+) DELAYG_11 (
+ .A(ddrphy_pad_oddrx2f11),
+ .Z(ddram_a[7])
+);
+
+ODDRX2F ODDRX2F_12(
+ .D0(ddrphy_dfi_p0_address[8]),
+ .D1(ddrphy_dfi_p0_address[8]),
+ .D2(ddrphy_dfi_p1_address[8]),
+ .D3(ddrphy_dfi_p1_address[8]),
+ .ECLK(sys2x_clk),
+ .RST(sys_rst),
+ .SCLK(sys_clk),
+ .Q(ddrphy_pad_oddrx2f12)
+);
+
+DELAYG #(
+ .DEL_VALUE(7'd100)
+) DELAYG_12 (
+ .A(ddrphy_pad_oddrx2f12),
+ .Z(ddram_a[8])
+);
+
+ODDRX2F ODDRX2F_13(
+ .D0(ddrphy_dfi_p0_address[9]),
+ .D1(ddrphy_dfi_p0_address[9]),
+ .D2(ddrphy_dfi_p1_address[9]),
+ .D3(ddrphy_dfi_p1_address[9]),
+ .ECLK(sys2x_clk),
+ .RST(sys_rst),
+ .SCLK(sys_clk),
+ .Q(ddrphy_pad_oddrx2f13)
+);
+
+DELAYG #(
+ .DEL_VALUE(7'd100)
+) DELAYG_13 (
+ .A(ddrphy_pad_oddrx2f13),
+ .Z(ddram_a[9])
+);
+
+ODDRX2F ODDRX2F_14(
+ .D0(ddrphy_dfi_p0_address[10]),
+ .D1(ddrphy_dfi_p0_address[10]),
+ .D2(ddrphy_dfi_p1_address[10]),
+ .D3(ddrphy_dfi_p1_address[10]),
+ .ECLK(sys2x_clk),
+ .RST(sys_rst),
+ .SCLK(sys_clk),
+ .Q(ddrphy_pad_oddrx2f14)
+);
+
+DELAYG #(
+ .DEL_VALUE(7'd100)
+) DELAYG_14 (
+ .A(ddrphy_pad_oddrx2f14),
+ .Z(ddram_a[10])
+);
+
+ODDRX2F ODDRX2F_15(
+ .D0(ddrphy_dfi_p0_address[11]),
+ .D1(ddrphy_dfi_p0_address[11]),
+ .D2(ddrphy_dfi_p1_address[11]),
+ .D3(ddrphy_dfi_p1_address[11]),
+ .ECLK(sys2x_clk),
+ .RST(sys_rst),
+ .SCLK(sys_clk),
+ .Q(ddrphy_pad_oddrx2f15)
+);
+
+DELAYG #(
+ .DEL_VALUE(7'd100)
+) DELAYG_15 (
+ .A(ddrphy_pad_oddrx2f15),
+ .Z(ddram_a[11])
+);
+
+ODDRX2F ODDRX2F_16(
+ .D0(ddrphy_dfi_p0_address[12]),
+ .D1(ddrphy_dfi_p0_address[12]),
+ .D2(ddrphy_dfi_p1_address[12]),
+ .D3(ddrphy_dfi_p1_address[12]),
+ .ECLK(sys2x_clk),
+ .RST(sys_rst),
+ .SCLK(sys_clk),
+ .Q(ddrphy_pad_oddrx2f16)
+);
+
+DELAYG #(
+ .DEL_VALUE(7'd100)
+) DELAYG_16 (
+ .A(ddrphy_pad_oddrx2f16),
+ .Z(ddram_a[12])
+);
+
+ODDRX2F ODDRX2F_17(
+ .D0(ddrphy_dfi_p0_address[13]),
+ .D1(ddrphy_dfi_p0_address[13]),
+ .D2(ddrphy_dfi_p1_address[13]),
+ .D3(ddrphy_dfi_p1_address[13]),
+ .ECLK(sys2x_clk),
+ .RST(sys_rst),
+ .SCLK(sys_clk),
+ .Q(ddrphy_pad_oddrx2f17)
+);
+
+DELAYG #(
+ .DEL_VALUE(7'd100)
+) DELAYG_17 (
+ .A(ddrphy_pad_oddrx2f17),
+ .Z(ddram_a[13])
+);
+
+ODDRX2F ODDRX2F_18(
+ .D0(ddrphy_dfi_p0_address[14]),
+ .D1(ddrphy_dfi_p0_address[14]),
+ .D2(ddrphy_dfi_p1_address[14]),
+ .D3(ddrphy_dfi_p1_address[14]),
+ .ECLK(sys2x_clk),
+ .RST(sys_rst),
+ .SCLK(sys_clk),
+ .Q(ddrphy_pad_oddrx2f18)
+);
+
+DELAYG #(
+ .DEL_VALUE(7'd100)
+) DELAYG_18 (
+ .A(ddrphy_pad_oddrx2f18),
+ .Z(ddram_a[14])
+);
+
+ODDRX2F ODDRX2F_19(
+ .D0(ddrphy_dfi_p0_bank[0]),
+ .D1(ddrphy_dfi_p0_bank[0]),
+ .D2(ddrphy_dfi_p1_bank[0]),
+ .D3(ddrphy_dfi_p1_bank[0]),
+ .ECLK(sys2x_clk),
+ .RST(sys_rst),
+ .SCLK(sys_clk),
+ .Q(ddrphy_pad_oddrx2f19)
+);
+
+DELAYG #(
+ .DEL_VALUE(7'd100)
+) DELAYG_19 (
+ .A(ddrphy_pad_oddrx2f19),
+ .Z(ddram_ba[0])
+);
+
+ODDRX2F ODDRX2F_20(
+ .D0(ddrphy_dfi_p0_bank[1]),
+ .D1(ddrphy_dfi_p0_bank[1]),
+ .D2(ddrphy_dfi_p1_bank[1]),
+ .D3(ddrphy_dfi_p1_bank[1]),
+ .ECLK(sys2x_clk),
+ .RST(sys_rst),
+ .SCLK(sys_clk),
+ .Q(ddrphy_pad_oddrx2f20)
+);
+
+DELAYG #(
+ .DEL_VALUE(7'd100)
+) DELAYG_20 (
+ .A(ddrphy_pad_oddrx2f20),
+ .Z(ddram_ba[1])
+);
+
+ODDRX2F ODDRX2F_21(
+ .D0(ddrphy_dfi_p0_bank[2]),
+ .D1(ddrphy_dfi_p0_bank[2]),
+ .D2(ddrphy_dfi_p1_bank[2]),
+ .D3(ddrphy_dfi_p1_bank[2]),
+ .ECLK(sys2x_clk),
+ .RST(sys_rst),
+ .SCLK(sys_clk),
+ .Q(ddrphy_pad_oddrx2f21)
+);
+
+DELAYG #(
+ .DEL_VALUE(7'd100)
+) DELAYG_21 (
+ .A(ddrphy_pad_oddrx2f21),
+ .Z(ddram_ba[2])
+);
+
+ODDRX2F ODDRX2F_22(
+ .D0(ddrphy_dfi_p0_ras_n),
+ .D1(ddrphy_dfi_p0_ras_n),
+ .D2(ddrphy_dfi_p1_ras_n),
+ .D3(ddrphy_dfi_p1_ras_n),
+ .ECLK(sys2x_clk),
+ .RST(sys_rst),
+ .SCLK(sys_clk),
+ .Q(ddrphy_pad_oddrx2f22)
+);
+
+DELAYG #(
+ .DEL_VALUE(7'd100)
+) DELAYG_22 (
+ .A(ddrphy_pad_oddrx2f22),
+ .Z(ddram_ras_n)
+);
+
+ODDRX2F ODDRX2F_23(
+ .D0(ddrphy_dfi_p0_cas_n),
+ .D1(ddrphy_dfi_p0_cas_n),
+ .D2(ddrphy_dfi_p1_cas_n),
+ .D3(ddrphy_dfi_p1_cas_n),
+ .ECLK(sys2x_clk),
+ .RST(sys_rst),
+ .SCLK(sys_clk),
+ .Q(ddrphy_pad_oddrx2f23)
+);
+
+DELAYG #(
+ .DEL_VALUE(7'd100)
+) DELAYG_23 (
+ .A(ddrphy_pad_oddrx2f23),
+ .Z(ddram_cas_n)
+);
+
+ODDRX2F ODDRX2F_24(
+ .D0(ddrphy_dfi_p0_we_n),
+ .D1(ddrphy_dfi_p0_we_n),
+ .D2(ddrphy_dfi_p1_we_n),
+ .D3(ddrphy_dfi_p1_we_n),
+ .ECLK(sys2x_clk),
+ .RST(sys_rst),
+ .SCLK(sys_clk),
+ .Q(ddrphy_pad_oddrx2f24)
+);
+
+DELAYG #(
+ .DEL_VALUE(7'd100)
+) DELAYG_24 (
+ .A(ddrphy_pad_oddrx2f24),
+ .Z(ddram_we_n)
+);
+
+ODDRX2F ODDRX2F_25(
+ .D0(ddrphy_dfi_p0_cke),
+ .D1(ddrphy_dfi_p0_cke),
+ .D2(ddrphy_dfi_p1_cke),
+ .D3(ddrphy_dfi_p1_cke),
+ .ECLK(sys2x_clk),
+ .RST(sys_rst),
+ .SCLK(sys_clk),
+ .Q(ddrphy_pad_oddrx2f25)
+);
+
+DELAYG #(
+ .DEL_VALUE(7'd100)
+) DELAYG_25 (
+ .A(ddrphy_pad_oddrx2f25),
+ .Z(ddram_cke)
+);
+
+ODDRX2F ODDRX2F_26(
+ .D0(ddrphy_dfi_p0_odt),
+ .D1(ddrphy_dfi_p0_odt),
+ .D2(ddrphy_dfi_p1_odt),
+ .D3(ddrphy_dfi_p1_odt),
+ .ECLK(sys2x_clk),
+ .RST(sys_rst),
+ .SCLK(sys_clk),
+ .Q(ddrphy_pad_oddrx2f26)
+);
+
+DELAYG #(
+ .DEL_VALUE(7'd100)
+) DELAYG_26 (
+ .A(ddrphy_pad_oddrx2f26),
+ .Z(ddram_odt)
+);
+
+DQSBUFM #(
+ .DQS_LI_DEL_ADJ("MINUS"),
+ .DQS_LI_DEL_VAL(1'd1),
+ .DQS_LO_DEL_ADJ("MINUS"),
+ .DQS_LO_DEL_VAL(3'd4)
+) DQSBUFM (
+ .DDRDEL(ddrphy_delay0),
+ .DQSI(ddrphy_dqs_i0),
+ .ECLK(sys2x_clk),
+ .PAUSE((ddrphy_pause0 | ddrphy_dly_sel_storage[0])),
+ .RDDIRECTION(1'd1),
+ .RDLOADN(1'd0),
+ .RDMOVE(1'd0),
+ .READ0(ddrphy_dqs_re),
+ .READ1(ddrphy_dqs_re),
+ .READCLKSEL0(ddrphy_rdly0[0]),
+ .READCLKSEL1(ddrphy_rdly0[1]),
+ .READCLKSEL2(ddrphy_rdly0[2]),
+ .RST(sys_rst),
+ .SCLK(sys_clk),
+ .WRDIRECTION(1'd1),
+ .WRLOADN(1'd0),
+ .WRMOVE(1'd0),
+ .BURSTDET(ddrphy_burstdet0),
+ .DATAVALID(ddrphy_datavalid[0]),
+ .DQSR90(ddrphy_dqsr900),
+ .DQSW(ddrphy_dqsw0),
+ .DQSW270(ddrphy_dqsw2700),
+ .RDPNTR0(ddrphy_rdpntr0[0]),
+ .RDPNTR1(ddrphy_rdpntr0[1]),
+ .RDPNTR2(ddrphy_rdpntr0[2]),
+ .WRPNTR0(ddrphy_wrpntr0[0]),
+ .WRPNTR1(ddrphy_wrpntr0[1]),
+ .WRPNTR2(ddrphy_wrpntr0[2])
+);
+
+ODDRX2DQSB ODDRX2DQSB(
+ .D0(1'd0),
+ .D1(1'd1),
+ .D2(1'd0),
+ .D3(1'd1),
+ .DQSW(ddrphy_dqsw0),
+ .ECLK(sys2x_clk),
+ .RST(sys_rst),
+ .SCLK(sys_clk),
+ .Q(ddrphy_dqs0)
+);
+
+TSHX2DQSA TSHX2DQSA(
+ .DQSW(ddrphy_dqsw0),
+ .ECLK(sys2x_clk),
+ .RST(sys_rst),
+ .SCLK(sys_clk),
+ .T0((~(ddrphy_dqs_oe | ddrphy_dqs_postamble))),
+ .T1((~(ddrphy_dqs_oe | ddrphy_dqs_preamble))),
+ .Q(ddrphy_dqs_oe_n0)
+);
+
+ODDRX2DQA ODDRX2DQA(
+ .D0(ddrphy_dm_o_data_muxed0[0]),
+ .D1(ddrphy_dm_o_data_muxed0[1]),
+ .D2(ddrphy_dm_o_data_muxed0[2]),
+ .D3(ddrphy_dm_o_data_muxed0[3]),
+ .DQSW270(ddrphy_dqsw2700),
+ .ECLK(sys2x_clk),
+ .RST(sys_rst),
+ .SCLK(sys_clk),
+ .Q(ddram_dm[0])
+);
+
+ODDRX2DQA ODDRX2DQA_1(
+ .D0(ddrphy_dq_o_data_muxed0[0]),
+ .D1(ddrphy_dq_o_data_muxed0[1]),
+ .D2(ddrphy_dq_o_data_muxed0[2]),
+ .D3(ddrphy_dq_o_data_muxed0[3]),
+ .DQSW270(ddrphy_dqsw2700),
+ .ECLK(sys2x_clk),
+ .RST(sys_rst),
+ .SCLK(sys_clk),
+ .Q(ddrphy_dq_o0)
+);
+
+DELAYG #(
+ .DEL_MODE("DQS_ALIGNED_X2")
+) DELAYG_27 (
+ .A(ddrphy_dq_i0),
+ .Z(ddrphy_dq_i_delayed0)
+);
+
+IDDRX2DQA IDDRX2DQA(
+ .D(ddrphy_dq_i_delayed0),
+ .DQSR90(ddrphy_dqsr900),
+ .ECLK(sys2x_clk),
+ .RDPNTR0(ddrphy_rdpntr0[0]),
+ .RDPNTR1(ddrphy_rdpntr0[1]),
+ .RDPNTR2(ddrphy_rdpntr0[2]),
+ .RST(sys_rst),
+ .SCLK(sys_clk),
+ .WRPNTR0(ddrphy_wrpntr0[0]),
+ .WRPNTR1(ddrphy_wrpntr0[1]),
+ .WRPNTR2(ddrphy_wrpntr0[2]),
+ .Q0(ddrphy_bitslip0_i[0]),
+ .Q1(ddrphy_bitslip0_i[1]),
+ .Q2(ddrphy_bitslip0_i[2]),
+ .Q3(ddrphy_bitslip0_i[3])
+);
+
+TSHX2DQA TSHX2DQA(
+ .DQSW270(ddrphy_dqsw2700),
+ .ECLK(sys2x_clk),
+ .RST(sys_rst),
+ .SCLK(sys_clk),
+ .T0((~ddrphy_dq_oe)),
+ .T1((~ddrphy_dq_oe)),
+ .Q(ddrphy_dq_oe_n0)
+);
+
+ODDRX2DQA ODDRX2DQA_2(
+ .D0(ddrphy_dq_o_data_muxed1[0]),
+ .D1(ddrphy_dq_o_data_muxed1[1]),
+ .D2(ddrphy_dq_o_data_muxed1[2]),
+ .D3(ddrphy_dq_o_data_muxed1[3]),
+ .DQSW270(ddrphy_dqsw2700),
+ .ECLK(sys2x_clk),
+ .RST(sys_rst),
+ .SCLK(sys_clk),
+ .Q(ddrphy_dq_o1)
+);
+
+DELAYG #(
+ .DEL_MODE("DQS_ALIGNED_X2")
+) DELAYG_28 (
+ .A(ddrphy_dq_i1),
+ .Z(ddrphy_dq_i_delayed1)
+);
+
+IDDRX2DQA IDDRX2DQA_1(
+ .D(ddrphy_dq_i_delayed1),
+ .DQSR90(ddrphy_dqsr900),
+ .ECLK(sys2x_clk),
+ .RDPNTR0(ddrphy_rdpntr0[0]),
+ .RDPNTR1(ddrphy_rdpntr0[1]),
+ .RDPNTR2(ddrphy_rdpntr0[2]),
+ .RST(sys_rst),
+ .SCLK(sys_clk),
+ .WRPNTR0(ddrphy_wrpntr0[0]),
+ .WRPNTR1(ddrphy_wrpntr0[1]),
+ .WRPNTR2(ddrphy_wrpntr0[2]),
+ .Q0(ddrphy_bitslip1_i[0]),
+ .Q1(ddrphy_bitslip1_i[1]),
+ .Q2(ddrphy_bitslip1_i[2]),
+ .Q3(ddrphy_bitslip1_i[3])
+);
+
+TSHX2DQA TSHX2DQA_1(
+ .DQSW270(ddrphy_dqsw2700),
+ .ECLK(sys2x_clk),
+ .RST(sys_rst),
+ .SCLK(sys_clk),
+ .T0((~ddrphy_dq_oe)),
+ .T1((~ddrphy_dq_oe)),
+ .Q(ddrphy_dq_oe_n1)
+);
+
+ODDRX2DQA ODDRX2DQA_3(
+ .D0(ddrphy_dq_o_data_muxed2[0]),
+ .D1(ddrphy_dq_o_data_muxed2[1]),
+ .D2(ddrphy_dq_o_data_muxed2[2]),
+ .D3(ddrphy_dq_o_data_muxed2[3]),
+ .DQSW270(ddrphy_dqsw2700),
+ .ECLK(sys2x_clk),
+ .RST(sys_rst),
+ .SCLK(sys_clk),
+ .Q(ddrphy_dq_o2)
+);
+
+DELAYG #(
+ .DEL_MODE("DQS_ALIGNED_X2")
+) DELAYG_29 (
+ .A(ddrphy_dq_i2),
+ .Z(ddrphy_dq_i_delayed2)
+);
+
+IDDRX2DQA IDDRX2DQA_2(
+ .D(ddrphy_dq_i_delayed2),
+ .DQSR90(ddrphy_dqsr900),
+ .ECLK(sys2x_clk),
+ .RDPNTR0(ddrphy_rdpntr0[0]),
+ .RDPNTR1(ddrphy_rdpntr0[1]),
+ .RDPNTR2(ddrphy_rdpntr0[2]),
+ .RST(sys_rst),
+ .SCLK(sys_clk),
+ .WRPNTR0(ddrphy_wrpntr0[0]),
+ .WRPNTR1(ddrphy_wrpntr0[1]),
+ .WRPNTR2(ddrphy_wrpntr0[2]),
+ .Q0(ddrphy_bitslip2_i[0]),
+ .Q1(ddrphy_bitslip2_i[1]),
+ .Q2(ddrphy_bitslip2_i[2]),
+ .Q3(ddrphy_bitslip2_i[3])
+);
+
+TSHX2DQA TSHX2DQA_2(
+ .DQSW270(ddrphy_dqsw2700),
+ .ECLK(sys2x_clk),
+ .RST(sys_rst),
+ .SCLK(sys_clk),
+ .T0((~ddrphy_dq_oe)),
+ .T1((~ddrphy_dq_oe)),
+ .Q(ddrphy_dq_oe_n2)
+);
+
+ODDRX2DQA ODDRX2DQA_4(
+ .D0(ddrphy_dq_o_data_muxed3[0]),
+ .D1(ddrphy_dq_o_data_muxed3[1]),
+ .D2(ddrphy_dq_o_data_muxed3[2]),
+ .D3(ddrphy_dq_o_data_muxed3[3]),
+ .DQSW270(ddrphy_dqsw2700),
+ .ECLK(sys2x_clk),
+ .RST(sys_rst),
+ .SCLK(sys_clk),
+ .Q(ddrphy_dq_o3)
+);
+
+DELAYG #(
+ .DEL_MODE("DQS_ALIGNED_X2")
+) DELAYG_30 (
+ .A(ddrphy_dq_i3),
+ .Z(ddrphy_dq_i_delayed3)
+);
+
+IDDRX2DQA IDDRX2DQA_3(
+ .D(ddrphy_dq_i_delayed3),
+ .DQSR90(ddrphy_dqsr900),
+ .ECLK(sys2x_clk),
+ .RDPNTR0(ddrphy_rdpntr0[0]),
+ .RDPNTR1(ddrphy_rdpntr0[1]),
+ .RDPNTR2(ddrphy_rdpntr0[2]),
+ .RST(sys_rst),
+ .SCLK(sys_clk),
+ .WRPNTR0(ddrphy_wrpntr0[0]),
+ .WRPNTR1(ddrphy_wrpntr0[1]),
+ .WRPNTR2(ddrphy_wrpntr0[2]),
+ .Q0(ddrphy_bitslip3_i[0]),
+ .Q1(ddrphy_bitslip3_i[1]),
+ .Q2(ddrphy_bitslip3_i[2]),
+ .Q3(ddrphy_bitslip3_i[3])
+);
+
+TSHX2DQA TSHX2DQA_3(
+ .DQSW270(ddrphy_dqsw2700),
+ .ECLK(sys2x_clk),
+ .RST(sys_rst),
+ .SCLK(sys_clk),
+ .T0((~ddrphy_dq_oe)),
+ .T1((~ddrphy_dq_oe)),
+ .Q(ddrphy_dq_oe_n3)
+);
+
+ODDRX2DQA ODDRX2DQA_5(
+ .D0(ddrphy_dq_o_data_muxed4[0]),
+ .D1(ddrphy_dq_o_data_muxed4[1]),
+ .D2(ddrphy_dq_o_data_muxed4[2]),
+ .D3(ddrphy_dq_o_data_muxed4[3]),
+ .DQSW270(ddrphy_dqsw2700),
+ .ECLK(sys2x_clk),
+ .RST(sys_rst),
+ .SCLK(sys_clk),
+ .Q(ddrphy_dq_o4)
+);
+
+DELAYG #(
+ .DEL_MODE("DQS_ALIGNED_X2")
+) DELAYG_31 (
+ .A(ddrphy_dq_i4),
+ .Z(ddrphy_dq_i_delayed4)
+);
+
+IDDRX2DQA IDDRX2DQA_4(
+ .D(ddrphy_dq_i_delayed4),
+ .DQSR90(ddrphy_dqsr900),
+ .ECLK(sys2x_clk),
+ .RDPNTR0(ddrphy_rdpntr0[0]),
+ .RDPNTR1(ddrphy_rdpntr0[1]),
+ .RDPNTR2(ddrphy_rdpntr0[2]),
+ .RST(sys_rst),
+ .SCLK(sys_clk),
+ .WRPNTR0(ddrphy_wrpntr0[0]),
+ .WRPNTR1(ddrphy_wrpntr0[1]),
+ .WRPNTR2(ddrphy_wrpntr0[2]),
+ .Q0(ddrphy_bitslip4_i[0]),
+ .Q1(ddrphy_bitslip4_i[1]),
+ .Q2(ddrphy_bitslip4_i[2]),
+ .Q3(ddrphy_bitslip4_i[3])
+);
+
+TSHX2DQA TSHX2DQA_4(
+ .DQSW270(ddrphy_dqsw2700),
+ .ECLK(sys2x_clk),
+ .RST(sys_rst),
+ .SCLK(sys_clk),
+ .T0((~ddrphy_dq_oe)),
+ .T1((~ddrphy_dq_oe)),
+ .Q(ddrphy_dq_oe_n4)
+);
+
+ODDRX2DQA ODDRX2DQA_6(
+ .D0(ddrphy_dq_o_data_muxed5[0]),
+ .D1(ddrphy_dq_o_data_muxed5[1]),
+ .D2(ddrphy_dq_o_data_muxed5[2]),
+ .D3(ddrphy_dq_o_data_muxed5[3]),
+ .DQSW270(ddrphy_dqsw2700),
+ .ECLK(sys2x_clk),
+ .RST(sys_rst),
+ .SCLK(sys_clk),
+ .Q(ddrphy_dq_o5)
+);
+
+DELAYG #(
+ .DEL_MODE("DQS_ALIGNED_X2")
+) DELAYG_32 (
+ .A(ddrphy_dq_i5),
+ .Z(ddrphy_dq_i_delayed5)
+);
+
+IDDRX2DQA IDDRX2DQA_5(
+ .D(ddrphy_dq_i_delayed5),
+ .DQSR90(ddrphy_dqsr900),
+ .ECLK(sys2x_clk),
+ .RDPNTR0(ddrphy_rdpntr0[0]),
+ .RDPNTR1(ddrphy_rdpntr0[1]),
+ .RDPNTR2(ddrphy_rdpntr0[2]),
+ .RST(sys_rst),
+ .SCLK(sys_clk),
+ .WRPNTR0(ddrphy_wrpntr0[0]),
+ .WRPNTR1(ddrphy_wrpntr0[1]),
+ .WRPNTR2(ddrphy_wrpntr0[2]),
+ .Q0(ddrphy_bitslip5_i[0]),
+ .Q1(ddrphy_bitslip5_i[1]),
+ .Q2(ddrphy_bitslip5_i[2]),
+ .Q3(ddrphy_bitslip5_i[3])
+);
+
+TSHX2DQA TSHX2DQA_5(
+ .DQSW270(ddrphy_dqsw2700),
+ .ECLK(sys2x_clk),
+ .RST(sys_rst),
+ .SCLK(sys_clk),
+ .T0((~ddrphy_dq_oe)),
+ .T1((~ddrphy_dq_oe)),
+ .Q(ddrphy_dq_oe_n5)
+);
+
+ODDRX2DQA ODDRX2DQA_7(
+ .D0(ddrphy_dq_o_data_muxed6[0]),
+ .D1(ddrphy_dq_o_data_muxed6[1]),
+ .D2(ddrphy_dq_o_data_muxed6[2]),
+ .D3(ddrphy_dq_o_data_muxed6[3]),
+ .DQSW270(ddrphy_dqsw2700),
+ .ECLK(sys2x_clk),
+ .RST(sys_rst),
+ .SCLK(sys_clk),
+ .Q(ddrphy_dq_o6)
+);
+
+DELAYG #(
+ .DEL_MODE("DQS_ALIGNED_X2")
+) DELAYG_33 (
+ .A(ddrphy_dq_i6),
+ .Z(ddrphy_dq_i_delayed6)
+);
+
+IDDRX2DQA IDDRX2DQA_6(
+ .D(ddrphy_dq_i_delayed6),
+ .DQSR90(ddrphy_dqsr900),
+ .ECLK(sys2x_clk),
+ .RDPNTR0(ddrphy_rdpntr0[0]),
+ .RDPNTR1(ddrphy_rdpntr0[1]),
+ .RDPNTR2(ddrphy_rdpntr0[2]),
+ .RST(sys_rst),
+ .SCLK(sys_clk),
+ .WRPNTR0(ddrphy_wrpntr0[0]),
+ .WRPNTR1(ddrphy_wrpntr0[1]),
+ .WRPNTR2(ddrphy_wrpntr0[2]),
+ .Q0(ddrphy_bitslip6_i[0]),
+ .Q1(ddrphy_bitslip6_i[1]),
+ .Q2(ddrphy_bitslip6_i[2]),
+ .Q3(ddrphy_bitslip6_i[3])
+);
+
+TSHX2DQA TSHX2DQA_6(
+ .DQSW270(ddrphy_dqsw2700),
+ .ECLK(sys2x_clk),
+ .RST(sys_rst),
+ .SCLK(sys_clk),
+ .T0((~ddrphy_dq_oe)),
+ .T1((~ddrphy_dq_oe)),
+ .Q(ddrphy_dq_oe_n6)
+);
+
+ODDRX2DQA ODDRX2DQA_8(
+ .D0(ddrphy_dq_o_data_muxed7[0]),
+ .D1(ddrphy_dq_o_data_muxed7[1]),
+ .D2(ddrphy_dq_o_data_muxed7[2]),
+ .D3(ddrphy_dq_o_data_muxed7[3]),
+ .DQSW270(ddrphy_dqsw2700),
+ .ECLK(sys2x_clk),
+ .RST(sys_rst),
+ .SCLK(sys_clk),
+ .Q(ddrphy_dq_o7)
+);
+
+DELAYG #(
+ .DEL_MODE("DQS_ALIGNED_X2")
+) DELAYG_34 (
+ .A(ddrphy_dq_i7),
+ .Z(ddrphy_dq_i_delayed7)
+);
+
+IDDRX2DQA IDDRX2DQA_7(
+ .D(ddrphy_dq_i_delayed7),
+ .DQSR90(ddrphy_dqsr900),
+ .ECLK(sys2x_clk),
+ .RDPNTR0(ddrphy_rdpntr0[0]),
+ .RDPNTR1(ddrphy_rdpntr0[1]),
+ .RDPNTR2(ddrphy_rdpntr0[2]),
+ .RST(sys_rst),
+ .SCLK(sys_clk),
+ .WRPNTR0(ddrphy_wrpntr0[0]),
+ .WRPNTR1(ddrphy_wrpntr0[1]),
+ .WRPNTR2(ddrphy_wrpntr0[2]),
+ .Q0(ddrphy_bitslip7_i[0]),
+ .Q1(ddrphy_bitslip7_i[1]),
+ .Q2(ddrphy_bitslip7_i[2]),
+ .Q3(ddrphy_bitslip7_i[3])
+);
+
+TSHX2DQA TSHX2DQA_7(
+ .DQSW270(ddrphy_dqsw2700),
+ .ECLK(sys2x_clk),
+ .RST(sys_rst),
+ .SCLK(sys_clk),
+ .T0((~ddrphy_dq_oe)),
+ .T1((~ddrphy_dq_oe)),
+ .Q(ddrphy_dq_oe_n7)
+);
+
+DQSBUFM #(
+ .DQS_LI_DEL_ADJ("MINUS"),
+ .DQS_LI_DEL_VAL(1'd1),
+ .DQS_LO_DEL_ADJ("MINUS"),
+ .DQS_LO_DEL_VAL(3'd4)
+) DQSBUFM_1 (
+ .DDRDEL(ddrphy_delay0),
+ .DQSI(ddrphy_dqs_i1),
+ .ECLK(sys2x_clk),
+ .PAUSE((ddrphy_pause0 | ddrphy_dly_sel_storage[1])),
+ .RDDIRECTION(1'd1),
+ .RDLOADN(1'd0),
+ .RDMOVE(1'd0),
+ .READ0(ddrphy_dqs_re),
+ .READ1(ddrphy_dqs_re),
+ .READCLKSEL0(ddrphy_rdly1[0]),
+ .READCLKSEL1(ddrphy_rdly1[1]),
+ .READCLKSEL2(ddrphy_rdly1[2]),
+ .RST(sys_rst),
+ .SCLK(sys_clk),
+ .WRDIRECTION(1'd1),
+ .WRLOADN(1'd0),
+ .WRMOVE(1'd0),
+ .BURSTDET(ddrphy_burstdet1),
+ .DATAVALID(ddrphy_datavalid[1]),
+ .DQSR90(ddrphy_dqsr901),
+ .DQSW(ddrphy_dqsw1),
+ .DQSW270(ddrphy_dqsw2701),
+ .RDPNTR0(ddrphy_rdpntr1[0]),
+ .RDPNTR1(ddrphy_rdpntr1[1]),
+ .RDPNTR2(ddrphy_rdpntr1[2]),
+ .WRPNTR0(ddrphy_wrpntr1[0]),
+ .WRPNTR1(ddrphy_wrpntr1[1]),
+ .WRPNTR2(ddrphy_wrpntr1[2])
+);
+
+ODDRX2DQSB ODDRX2DQSB_1(
+ .D0(1'd0),
+ .D1(1'd1),
+ .D2(1'd0),
+ .D3(1'd1),
+ .DQSW(ddrphy_dqsw1),
+ .ECLK(sys2x_clk),
+ .RST(sys_rst),
+ .SCLK(sys_clk),
+ .Q(ddrphy_dqs1)
+);
+
+TSHX2DQSA TSHX2DQSA_1(
+ .DQSW(ddrphy_dqsw1),
+ .ECLK(sys2x_clk),
+ .RST(sys_rst),
+ .SCLK(sys_clk),
+ .T0((~(ddrphy_dqs_oe | ddrphy_dqs_postamble))),
+ .T1((~(ddrphy_dqs_oe | ddrphy_dqs_preamble))),
+ .Q(ddrphy_dqs_oe_n1)
+);
+
+ODDRX2DQA ODDRX2DQA_9(
+ .D0(ddrphy_dm_o_data_muxed1[0]),
+ .D1(ddrphy_dm_o_data_muxed1[1]),
+ .D2(ddrphy_dm_o_data_muxed1[2]),
+ .D3(ddrphy_dm_o_data_muxed1[3]),
+ .DQSW270(ddrphy_dqsw2701),
+ .ECLK(sys2x_clk),
+ .RST(sys_rst),
+ .SCLK(sys_clk),
+ .Q(ddram_dm[1])
+);
+
+ODDRX2DQA ODDRX2DQA_10(
+ .D0(ddrphy_dq_o_data_muxed8[0]),
+ .D1(ddrphy_dq_o_data_muxed8[1]),
+ .D2(ddrphy_dq_o_data_muxed8[2]),
+ .D3(ddrphy_dq_o_data_muxed8[3]),
+ .DQSW270(ddrphy_dqsw2701),
+ .ECLK(sys2x_clk),
+ .RST(sys_rst),
+ .SCLK(sys_clk),
+ .Q(ddrphy_dq_o8)
+);
+
+DELAYG #(
+ .DEL_MODE("DQS_ALIGNED_X2")
+) DELAYG_35 (
+ .A(ddrphy_dq_i8),
+ .Z(ddrphy_dq_i_delayed8)
+);
+
+IDDRX2DQA IDDRX2DQA_8(
+ .D(ddrphy_dq_i_delayed8),
+ .DQSR90(ddrphy_dqsr901),
+ .ECLK(sys2x_clk),
+ .RDPNTR0(ddrphy_rdpntr1[0]),
+ .RDPNTR1(ddrphy_rdpntr1[1]),
+ .RDPNTR2(ddrphy_rdpntr1[2]),
+ .RST(sys_rst),
+ .SCLK(sys_clk),
+ .WRPNTR0(ddrphy_wrpntr1[0]),
+ .WRPNTR1(ddrphy_wrpntr1[1]),
+ .WRPNTR2(ddrphy_wrpntr1[2]),
+ .Q0(ddrphy_bitslip8_i[0]),
+ .Q1(ddrphy_bitslip8_i[1]),
+ .Q2(ddrphy_bitslip8_i[2]),
+ .Q3(ddrphy_bitslip8_i[3])
+);
+
+TSHX2DQA TSHX2DQA_8(
+ .DQSW270(ddrphy_dqsw2701),
+ .ECLK(sys2x_clk),
+ .RST(sys_rst),
+ .SCLK(sys_clk),
+ .T0((~ddrphy_dq_oe)),
+ .T1((~ddrphy_dq_oe)),
+ .Q(ddrphy_dq_oe_n8)
+);
+
+ODDRX2DQA ODDRX2DQA_11(
+ .D0(ddrphy_dq_o_data_muxed9[0]),
+ .D1(ddrphy_dq_o_data_muxed9[1]),
+ .D2(ddrphy_dq_o_data_muxed9[2]),
+ .D3(ddrphy_dq_o_data_muxed9[3]),
+ .DQSW270(ddrphy_dqsw2701),
+ .ECLK(sys2x_clk),
+ .RST(sys_rst),
+ .SCLK(sys_clk),
+ .Q(ddrphy_dq_o9)
+);
+
+DELAYG #(
+ .DEL_MODE("DQS_ALIGNED_X2")
+) DELAYG_36 (
+ .A(ddrphy_dq_i9),
+ .Z(ddrphy_dq_i_delayed9)
+);
+
+IDDRX2DQA IDDRX2DQA_9(
+ .D(ddrphy_dq_i_delayed9),
+ .DQSR90(ddrphy_dqsr901),
+ .ECLK(sys2x_clk),
+ .RDPNTR0(ddrphy_rdpntr1[0]),
+ .RDPNTR1(ddrphy_rdpntr1[1]),
+ .RDPNTR2(ddrphy_rdpntr1[2]),
+ .RST(sys_rst),
+ .SCLK(sys_clk),
+ .WRPNTR0(ddrphy_wrpntr1[0]),
+ .WRPNTR1(ddrphy_wrpntr1[1]),
+ .WRPNTR2(ddrphy_wrpntr1[2]),
+ .Q0(ddrphy_bitslip9_i[0]),
+ .Q1(ddrphy_bitslip9_i[1]),
+ .Q2(ddrphy_bitslip9_i[2]),
+ .Q3(ddrphy_bitslip9_i[3])
+);
+
+TSHX2DQA TSHX2DQA_9(
+ .DQSW270(ddrphy_dqsw2701),
+ .ECLK(sys2x_clk),
+ .RST(sys_rst),
+ .SCLK(sys_clk),
+ .T0((~ddrphy_dq_oe)),
+ .T1((~ddrphy_dq_oe)),
+ .Q(ddrphy_dq_oe_n9)
+);
+
+ODDRX2DQA ODDRX2DQA_12(
+ .D0(ddrphy_dq_o_data_muxed10[0]),
+ .D1(ddrphy_dq_o_data_muxed10[1]),
+ .D2(ddrphy_dq_o_data_muxed10[2]),
+ .D3(ddrphy_dq_o_data_muxed10[3]),
+ .DQSW270(ddrphy_dqsw2701),
+ .ECLK(sys2x_clk),
+ .RST(sys_rst),
+ .SCLK(sys_clk),
+ .Q(ddrphy_dq_o10)
+);
+
+DELAYG #(
+ .DEL_MODE("DQS_ALIGNED_X2")
+) DELAYG_37 (
+ .A(ddrphy_dq_i10),
+ .Z(ddrphy_dq_i_delayed10)
+);
+
+IDDRX2DQA IDDRX2DQA_10(
+ .D(ddrphy_dq_i_delayed10),
+ .DQSR90(ddrphy_dqsr901),
+ .ECLK(sys2x_clk),
+ .RDPNTR0(ddrphy_rdpntr1[0]),
+ .RDPNTR1(ddrphy_rdpntr1[1]),
+ .RDPNTR2(ddrphy_rdpntr1[2]),
+ .RST(sys_rst),
+ .SCLK(sys_clk),
+ .WRPNTR0(ddrphy_wrpntr1[0]),
+ .WRPNTR1(ddrphy_wrpntr1[1]),
+ .WRPNTR2(ddrphy_wrpntr1[2]),
+ .Q0(ddrphy_bitslip10_i[0]),
+ .Q1(ddrphy_bitslip10_i[1]),
+ .Q2(ddrphy_bitslip10_i[2]),
+ .Q3(ddrphy_bitslip10_i[3])
+);
+
+TSHX2DQA TSHX2DQA_10(
+ .DQSW270(ddrphy_dqsw2701),
+ .ECLK(sys2x_clk),
+ .RST(sys_rst),
+ .SCLK(sys_clk),
+ .T0((~ddrphy_dq_oe)),
+ .T1((~ddrphy_dq_oe)),
+ .Q(ddrphy_dq_oe_n10)
+);
+
+ODDRX2DQA ODDRX2DQA_13(
+ .D0(ddrphy_dq_o_data_muxed11[0]),
+ .D1(ddrphy_dq_o_data_muxed11[1]),
+ .D2(ddrphy_dq_o_data_muxed11[2]),
+ .D3(ddrphy_dq_o_data_muxed11[3]),
+ .DQSW270(ddrphy_dqsw2701),
+ .ECLK(sys2x_clk),
+ .RST(sys_rst),
+ .SCLK(sys_clk),
+ .Q(ddrphy_dq_o11)
+);
+
+DELAYG #(
+ .DEL_MODE("DQS_ALIGNED_X2")
+) DELAYG_38 (
+ .A(ddrphy_dq_i11),
+ .Z(ddrphy_dq_i_delayed11)
+);
+
+IDDRX2DQA IDDRX2DQA_11(
+ .D(ddrphy_dq_i_delayed11),
+ .DQSR90(ddrphy_dqsr901),
+ .ECLK(sys2x_clk),
+ .RDPNTR0(ddrphy_rdpntr1[0]),
+ .RDPNTR1(ddrphy_rdpntr1[1]),
+ .RDPNTR2(ddrphy_rdpntr1[2]),
+ .RST(sys_rst),
+ .SCLK(sys_clk),
+ .WRPNTR0(ddrphy_wrpntr1[0]),
+ .WRPNTR1(ddrphy_wrpntr1[1]),
+ .WRPNTR2(ddrphy_wrpntr1[2]),
+ .Q0(ddrphy_bitslip11_i[0]),
+ .Q1(ddrphy_bitslip11_i[1]),
+ .Q2(ddrphy_bitslip11_i[2]),
+ .Q3(ddrphy_bitslip11_i[3])
+);
+
+TSHX2DQA TSHX2DQA_11(
+ .DQSW270(ddrphy_dqsw2701),
+ .ECLK(sys2x_clk),
+ .RST(sys_rst),
+ .SCLK(sys_clk),
+ .T0((~ddrphy_dq_oe)),
+ .T1((~ddrphy_dq_oe)),
+ .Q(ddrphy_dq_oe_n11)
+);
+
+ODDRX2DQA ODDRX2DQA_14(
+ .D0(ddrphy_dq_o_data_muxed12[0]),
+ .D1(ddrphy_dq_o_data_muxed12[1]),
+ .D2(ddrphy_dq_o_data_muxed12[2]),
+ .D3(ddrphy_dq_o_data_muxed12[3]),
+ .DQSW270(ddrphy_dqsw2701),
+ .ECLK(sys2x_clk),
+ .RST(sys_rst),
+ .SCLK(sys_clk),
+ .Q(ddrphy_dq_o12)
+);
+
+DELAYG #(
+ .DEL_MODE("DQS_ALIGNED_X2")
+) DELAYG_39 (
+ .A(ddrphy_dq_i12),
+ .Z(ddrphy_dq_i_delayed12)
+);
+
+IDDRX2DQA IDDRX2DQA_12(
+ .D(ddrphy_dq_i_delayed12),
+ .DQSR90(ddrphy_dqsr901),
+ .ECLK(sys2x_clk),
+ .RDPNTR0(ddrphy_rdpntr1[0]),
+ .RDPNTR1(ddrphy_rdpntr1[1]),
+ .RDPNTR2(ddrphy_rdpntr1[2]),
+ .RST(sys_rst),
+ .SCLK(sys_clk),
+ .WRPNTR0(ddrphy_wrpntr1[0]),
+ .WRPNTR1(ddrphy_wrpntr1[1]),
+ .WRPNTR2(ddrphy_wrpntr1[2]),
+ .Q0(ddrphy_bitslip12_i[0]),
+ .Q1(ddrphy_bitslip12_i[1]),
+ .Q2(ddrphy_bitslip12_i[2]),
+ .Q3(ddrphy_bitslip12_i[3])
+);
+
+TSHX2DQA TSHX2DQA_12(
+ .DQSW270(ddrphy_dqsw2701),
+ .ECLK(sys2x_clk),
+ .RST(sys_rst),
+ .SCLK(sys_clk),
+ .T0((~ddrphy_dq_oe)),
+ .T1((~ddrphy_dq_oe)),
+ .Q(ddrphy_dq_oe_n12)
+);
+
+ODDRX2DQA ODDRX2DQA_15(
+ .D0(ddrphy_dq_o_data_muxed13[0]),
+ .D1(ddrphy_dq_o_data_muxed13[1]),
+ .D2(ddrphy_dq_o_data_muxed13[2]),
+ .D3(ddrphy_dq_o_data_muxed13[3]),
+ .DQSW270(ddrphy_dqsw2701),
+ .ECLK(sys2x_clk),
+ .RST(sys_rst),
+ .SCLK(sys_clk),
+ .Q(ddrphy_dq_o13)
+);
+
+DELAYG #(
+ .DEL_MODE("DQS_ALIGNED_X2")
+) DELAYG_40 (
+ .A(ddrphy_dq_i13),
+ .Z(ddrphy_dq_i_delayed13)
+);
+
+IDDRX2DQA IDDRX2DQA_13(
+ .D(ddrphy_dq_i_delayed13),
+ .DQSR90(ddrphy_dqsr901),
+ .ECLK(sys2x_clk),
+ .RDPNTR0(ddrphy_rdpntr1[0]),
+ .RDPNTR1(ddrphy_rdpntr1[1]),
+ .RDPNTR2(ddrphy_rdpntr1[2]),
+ .RST(sys_rst),
+ .SCLK(sys_clk),
+ .WRPNTR0(ddrphy_wrpntr1[0]),
+ .WRPNTR1(ddrphy_wrpntr1[1]),
+ .WRPNTR2(ddrphy_wrpntr1[2]),
+ .Q0(ddrphy_bitslip13_i[0]),
+ .Q1(ddrphy_bitslip13_i[1]),
+ .Q2(ddrphy_bitslip13_i[2]),
+ .Q3(ddrphy_bitslip13_i[3])
+);
+
+TSHX2DQA TSHX2DQA_13(
+ .DQSW270(ddrphy_dqsw2701),
+ .ECLK(sys2x_clk),
+ .RST(sys_rst),
+ .SCLK(sys_clk),
+ .T0((~ddrphy_dq_oe)),
+ .T1((~ddrphy_dq_oe)),
+ .Q(ddrphy_dq_oe_n13)
+);
+
+ODDRX2DQA ODDRX2DQA_16(
+ .D0(ddrphy_dq_o_data_muxed14[0]),
+ .D1(ddrphy_dq_o_data_muxed14[1]),
+ .D2(ddrphy_dq_o_data_muxed14[2]),
+ .D3(ddrphy_dq_o_data_muxed14[3]),
+ .DQSW270(ddrphy_dqsw2701),
+ .ECLK(sys2x_clk),
+ .RST(sys_rst),
+ .SCLK(sys_clk),
+ .Q(ddrphy_dq_o14)
+);
+
+DELAYG #(
+ .DEL_MODE("DQS_ALIGNED_X2")
+) DELAYG_41 (
+ .A(ddrphy_dq_i14),
+ .Z(ddrphy_dq_i_delayed14)
+);
+
+IDDRX2DQA IDDRX2DQA_14(
+ .D(ddrphy_dq_i_delayed14),
+ .DQSR90(ddrphy_dqsr901),
+ .ECLK(sys2x_clk),
+ .RDPNTR0(ddrphy_rdpntr1[0]),
+ .RDPNTR1(ddrphy_rdpntr1[1]),
+ .RDPNTR2(ddrphy_rdpntr1[2]),
+ .RST(sys_rst),
+ .SCLK(sys_clk),
+ .WRPNTR0(ddrphy_wrpntr1[0]),
+ .WRPNTR1(ddrphy_wrpntr1[1]),
+ .WRPNTR2(ddrphy_wrpntr1[2]),
+ .Q0(ddrphy_bitslip14_i[0]),
+ .Q1(ddrphy_bitslip14_i[1]),
+ .Q2(ddrphy_bitslip14_i[2]),
+ .Q3(ddrphy_bitslip14_i[3])
+);
+
+TSHX2DQA TSHX2DQA_14(
+ .DQSW270(ddrphy_dqsw2701),
+ .ECLK(sys2x_clk),
+ .RST(sys_rst),
+ .SCLK(sys_clk),
+ .T0((~ddrphy_dq_oe)),
+ .T1((~ddrphy_dq_oe)),
+ .Q(ddrphy_dq_oe_n14)
+);
+
+ODDRX2DQA ODDRX2DQA_17(
+ .D0(ddrphy_dq_o_data_muxed15[0]),
+ .D1(ddrphy_dq_o_data_muxed15[1]),
+ .D2(ddrphy_dq_o_data_muxed15[2]),
+ .D3(ddrphy_dq_o_data_muxed15[3]),
+ .DQSW270(ddrphy_dqsw2701),
+ .ECLK(sys2x_clk),
+ .RST(sys_rst),
+ .SCLK(sys_clk),
+ .Q(ddrphy_dq_o15)
+);
+
+DELAYG #(
+ .DEL_MODE("DQS_ALIGNED_X2")
+) DELAYG_42 (
+ .A(ddrphy_dq_i15),
+ .Z(ddrphy_dq_i_delayed15)
+);
+
+IDDRX2DQA IDDRX2DQA_15(
+ .D(ddrphy_dq_i_delayed15),
+ .DQSR90(ddrphy_dqsr901),
+ .ECLK(sys2x_clk),
+ .RDPNTR0(ddrphy_rdpntr1[0]),
+ .RDPNTR1(ddrphy_rdpntr1[1]),
+ .RDPNTR2(ddrphy_rdpntr1[2]),
+ .RST(sys_rst),
+ .SCLK(sys_clk),
+ .WRPNTR0(ddrphy_wrpntr1[0]),
+ .WRPNTR1(ddrphy_wrpntr1[1]),
+ .WRPNTR2(ddrphy_wrpntr1[2]),
+ .Q0(ddrphy_bitslip15_i[0]),
+ .Q1(ddrphy_bitslip15_i[1]),
+ .Q2(ddrphy_bitslip15_i[2]),
+ .Q3(ddrphy_bitslip15_i[3])
+);
+
+TSHX2DQA TSHX2DQA_15(
+ .DQSW270(ddrphy_dqsw2701),
+ .ECLK(sys2x_clk),
+ .RST(sys_rst),
+ .SCLK(sys_clk),
+ .T0((~ddrphy_dq_oe)),
+ .T1((~ddrphy_dq_oe)),
+ .Q(ddrphy_dq_oe_n15)
+);
+
+DQSBUFM #(
+ .DQS_LI_DEL_ADJ("MINUS"),
+ .DQS_LI_DEL_VAL(1'd1),
+ .DQS_LO_DEL_ADJ("MINUS"),
+ .DQS_LO_DEL_VAL(3'd4)
+) DQSBUFM_2 (
+ .DDRDEL(ddrphy_delay0),
+ .DQSI(ddrphy_dqs_i2),
+ .ECLK(sys2x_clk),
+ .PAUSE((ddrphy_pause0 | ddrphy_dly_sel_storage[2])),
+ .RDDIRECTION(1'd1),
+ .RDLOADN(1'd0),
+ .RDMOVE(1'd0),
+ .READ0(ddrphy_dqs_re),
+ .READ1(ddrphy_dqs_re),
+ .READCLKSEL0(ddrphy_rdly2[0]),
+ .READCLKSEL1(ddrphy_rdly2[1]),
+ .READCLKSEL2(ddrphy_rdly2[2]),
+ .RST(sys_rst),
+ .SCLK(sys_clk),
+ .WRDIRECTION(1'd1),
+ .WRLOADN(1'd0),
+ .WRMOVE(1'd0),
+ .BURSTDET(ddrphy_burstdet2),
+ .DATAVALID(ddrphy_datavalid[2]),
+ .DQSR90(ddrphy_dqsr902),
+ .DQSW(ddrphy_dqsw2),
+ .DQSW270(ddrphy_dqsw2702),
+ .RDPNTR0(ddrphy_rdpntr2[0]),
+ .RDPNTR1(ddrphy_rdpntr2[1]),
+ .RDPNTR2(ddrphy_rdpntr2[2]),
+ .WRPNTR0(ddrphy_wrpntr2[0]),
+ .WRPNTR1(ddrphy_wrpntr2[1]),
+ .WRPNTR2(ddrphy_wrpntr2[2])
+);
+
+ODDRX2DQSB ODDRX2DQSB_2(
+ .D0(1'd0),
+ .D1(1'd1),
+ .D2(1'd0),
+ .D3(1'd1),
+ .DQSW(ddrphy_dqsw2),
+ .ECLK(sys2x_clk),
+ .RST(sys_rst),
+ .SCLK(sys_clk),
+ .Q(ddrphy_dqs2)
+);
+
+TSHX2DQSA TSHX2DQSA_2(
+ .DQSW(ddrphy_dqsw2),
+ .ECLK(sys2x_clk),
+ .RST(sys_rst),
+ .SCLK(sys_clk),
+ .T0((~(ddrphy_dqs_oe | ddrphy_dqs_postamble))),
+ .T1((~(ddrphy_dqs_oe | ddrphy_dqs_preamble))),
+ .Q(ddrphy_dqs_oe_n2)
+);
+
+ODDRX2DQA ODDRX2DQA_18(
+ .D0(ddrphy_dm_o_data_muxed2[0]),
+ .D1(ddrphy_dm_o_data_muxed2[1]),
+ .D2(ddrphy_dm_o_data_muxed2[2]),
+ .D3(ddrphy_dm_o_data_muxed2[3]),
+ .DQSW270(ddrphy_dqsw2702),
+ .ECLK(sys2x_clk),
+ .RST(sys_rst),
+ .SCLK(sys_clk),
+ .Q(ddram_dm[2])
+);
+
+ODDRX2DQA ODDRX2DQA_19(
+ .D0(ddrphy_dq_o_data_muxed16[0]),
+ .D1(ddrphy_dq_o_data_muxed16[1]),
+ .D2(ddrphy_dq_o_data_muxed16[2]),
+ .D3(ddrphy_dq_o_data_muxed16[3]),
+ .DQSW270(ddrphy_dqsw2702),
+ .ECLK(sys2x_clk),
+ .RST(sys_rst),
+ .SCLK(sys_clk),
+ .Q(ddrphy_dq_o16)
+);
+
+DELAYG #(
+ .DEL_MODE("DQS_ALIGNED_X2")
+) DELAYG_43 (
+ .A(ddrphy_dq_i16),
+ .Z(ddrphy_dq_i_delayed16)
+);
+
+IDDRX2DQA IDDRX2DQA_16(
+ .D(ddrphy_dq_i_delayed16),
+ .DQSR90(ddrphy_dqsr902),
+ .ECLK(sys2x_clk),
+ .RDPNTR0(ddrphy_rdpntr2[0]),
+ .RDPNTR1(ddrphy_rdpntr2[1]),
+ .RDPNTR2(ddrphy_rdpntr2[2]),
+ .RST(sys_rst),
+ .SCLK(sys_clk),
+ .WRPNTR0(ddrphy_wrpntr2[0]),
+ .WRPNTR1(ddrphy_wrpntr2[1]),
+ .WRPNTR2(ddrphy_wrpntr2[2]),
+ .Q0(ddrphy_bitslip16_i[0]),
+ .Q1(ddrphy_bitslip16_i[1]),
+ .Q2(ddrphy_bitslip16_i[2]),
+ .Q3(ddrphy_bitslip16_i[3])
+);
+
+TSHX2DQA TSHX2DQA_16(
+ .DQSW270(ddrphy_dqsw2702),
+ .ECLK(sys2x_clk),
+ .RST(sys_rst),
+ .SCLK(sys_clk),
+ .T0((~ddrphy_dq_oe)),
+ .T1((~ddrphy_dq_oe)),
+ .Q(ddrphy_dq_oe_n16)
+);
+
+ODDRX2DQA ODDRX2DQA_20(
+ .D0(ddrphy_dq_o_data_muxed17[0]),
+ .D1(ddrphy_dq_o_data_muxed17[1]),
+ .D2(ddrphy_dq_o_data_muxed17[2]),
+ .D3(ddrphy_dq_o_data_muxed17[3]),
+ .DQSW270(ddrphy_dqsw2702),
+ .ECLK(sys2x_clk),
+ .RST(sys_rst),
+ .SCLK(sys_clk),
+ .Q(ddrphy_dq_o17)
+);
+
+DELAYG #(
+ .DEL_MODE("DQS_ALIGNED_X2")
+) DELAYG_44 (
+ .A(ddrphy_dq_i17),
+ .Z(ddrphy_dq_i_delayed17)
+);
+
+IDDRX2DQA IDDRX2DQA_17(
+ .D(ddrphy_dq_i_delayed17),
+ .DQSR90(ddrphy_dqsr902),
+ .ECLK(sys2x_clk),
+ .RDPNTR0(ddrphy_rdpntr2[0]),
+ .RDPNTR1(ddrphy_rdpntr2[1]),
+ .RDPNTR2(ddrphy_rdpntr2[2]),
+ .RST(sys_rst),
+ .SCLK(sys_clk),
+ .WRPNTR0(ddrphy_wrpntr2[0]),
+ .WRPNTR1(ddrphy_wrpntr2[1]),
+ .WRPNTR2(ddrphy_wrpntr2[2]),
+ .Q0(ddrphy_bitslip17_i[0]),
+ .Q1(ddrphy_bitslip17_i[1]),
+ .Q2(ddrphy_bitslip17_i[2]),
+ .Q3(ddrphy_bitslip17_i[3])
+);
+
+TSHX2DQA TSHX2DQA_17(
+ .DQSW270(ddrphy_dqsw2702),
+ .ECLK(sys2x_clk),
+ .RST(sys_rst),
+ .SCLK(sys_clk),
+ .T0((~ddrphy_dq_oe)),
+ .T1((~ddrphy_dq_oe)),
+ .Q(ddrphy_dq_oe_n17)
+);
+
+ODDRX2DQA ODDRX2DQA_21(
+ .D0(ddrphy_dq_o_data_muxed18[0]),
+ .D1(ddrphy_dq_o_data_muxed18[1]),
+ .D2(ddrphy_dq_o_data_muxed18[2]),
+ .D3(ddrphy_dq_o_data_muxed18[3]),
+ .DQSW270(ddrphy_dqsw2702),
+ .ECLK(sys2x_clk),
+ .RST(sys_rst),
+ .SCLK(sys_clk),
+ .Q(ddrphy_dq_o18)
+);
+
+DELAYG #(
+ .DEL_MODE("DQS_ALIGNED_X2")
+) DELAYG_45 (
+ .A(ddrphy_dq_i18),
+ .Z(ddrphy_dq_i_delayed18)
+);
+
+IDDRX2DQA IDDRX2DQA_18(
+ .D(ddrphy_dq_i_delayed18),
+ .DQSR90(ddrphy_dqsr902),
+ .ECLK(sys2x_clk),
+ .RDPNTR0(ddrphy_rdpntr2[0]),
+ .RDPNTR1(ddrphy_rdpntr2[1]),
+ .RDPNTR2(ddrphy_rdpntr2[2]),
+ .RST(sys_rst),
+ .SCLK(sys_clk),
+ .WRPNTR0(ddrphy_wrpntr2[0]),
+ .WRPNTR1(ddrphy_wrpntr2[1]),
+ .WRPNTR2(ddrphy_wrpntr2[2]),
+ .Q0(ddrphy_bitslip18_i[0]),
+ .Q1(ddrphy_bitslip18_i[1]),
+ .Q2(ddrphy_bitslip18_i[2]),
+ .Q3(ddrphy_bitslip18_i[3])
+);
+
+TSHX2DQA TSHX2DQA_18(
+ .DQSW270(ddrphy_dqsw2702),
+ .ECLK(sys2x_clk),
+ .RST(sys_rst),
+ .SCLK(sys_clk),
+ .T0((~ddrphy_dq_oe)),
+ .T1((~ddrphy_dq_oe)),
+ .Q(ddrphy_dq_oe_n18)
+);
+
+ODDRX2DQA ODDRX2DQA_22(
+ .D0(ddrphy_dq_o_data_muxed19[0]),
+ .D1(ddrphy_dq_o_data_muxed19[1]),
+ .D2(ddrphy_dq_o_data_muxed19[2]),
+ .D3(ddrphy_dq_o_data_muxed19[3]),
+ .DQSW270(ddrphy_dqsw2702),
+ .ECLK(sys2x_clk),
+ .RST(sys_rst),
+ .SCLK(sys_clk),
+ .Q(ddrphy_dq_o19)
+);
+
+DELAYG #(
+ .DEL_MODE("DQS_ALIGNED_X2")
+) DELAYG_46 (
+ .A(ddrphy_dq_i19),
+ .Z(ddrphy_dq_i_delayed19)
+);
+
+IDDRX2DQA IDDRX2DQA_19(
+ .D(ddrphy_dq_i_delayed19),
+ .DQSR90(ddrphy_dqsr902),
+ .ECLK(sys2x_clk),
+ .RDPNTR0(ddrphy_rdpntr2[0]),
+ .RDPNTR1(ddrphy_rdpntr2[1]),
+ .RDPNTR2(ddrphy_rdpntr2[2]),
+ .RST(sys_rst),
+ .SCLK(sys_clk),
+ .WRPNTR0(ddrphy_wrpntr2[0]),
+ .WRPNTR1(ddrphy_wrpntr2[1]),
+ .WRPNTR2(ddrphy_wrpntr2[2]),
+ .Q0(ddrphy_bitslip19_i[0]),
+ .Q1(ddrphy_bitslip19_i[1]),
+ .Q2(ddrphy_bitslip19_i[2]),
+ .Q3(ddrphy_bitslip19_i[3])
+);
+
+TSHX2DQA TSHX2DQA_19(
+ .DQSW270(ddrphy_dqsw2702),
+ .ECLK(sys2x_clk),
+ .RST(sys_rst),
+ .SCLK(sys_clk),
+ .T0((~ddrphy_dq_oe)),
+ .T1((~ddrphy_dq_oe)),
+ .Q(ddrphy_dq_oe_n19)
+);
+
+ODDRX2DQA ODDRX2DQA_23(
+ .D0(ddrphy_dq_o_data_muxed20[0]),
+ .D1(ddrphy_dq_o_data_muxed20[1]),
+ .D2(ddrphy_dq_o_data_muxed20[2]),
+ .D3(ddrphy_dq_o_data_muxed20[3]),
+ .DQSW270(ddrphy_dqsw2702),
+ .ECLK(sys2x_clk),
+ .RST(sys_rst),
+ .SCLK(sys_clk),
+ .Q(ddrphy_dq_o20)
+);
+
+DELAYG #(
+ .DEL_MODE("DQS_ALIGNED_X2")
+) DELAYG_47 (
+ .A(ddrphy_dq_i20),
+ .Z(ddrphy_dq_i_delayed20)
+);
+
+IDDRX2DQA IDDRX2DQA_20(
+ .D(ddrphy_dq_i_delayed20),
+ .DQSR90(ddrphy_dqsr902),
+ .ECLK(sys2x_clk),
+ .RDPNTR0(ddrphy_rdpntr2[0]),
+ .RDPNTR1(ddrphy_rdpntr2[1]),
+ .RDPNTR2(ddrphy_rdpntr2[2]),
+ .RST(sys_rst),
+ .SCLK(sys_clk),
+ .WRPNTR0(ddrphy_wrpntr2[0]),
+ .WRPNTR1(ddrphy_wrpntr2[1]),
+ .WRPNTR2(ddrphy_wrpntr2[2]),
+ .Q0(ddrphy_bitslip20_i[0]),
+ .Q1(ddrphy_bitslip20_i[1]),
+ .Q2(ddrphy_bitslip20_i[2]),
+ .Q3(ddrphy_bitslip20_i[3])
+);
+
+TSHX2DQA TSHX2DQA_20(
+ .DQSW270(ddrphy_dqsw2702),
+ .ECLK(sys2x_clk),
+ .RST(sys_rst),
+ .SCLK(sys_clk),
+ .T0((~ddrphy_dq_oe)),
+ .T1((~ddrphy_dq_oe)),
+ .Q(ddrphy_dq_oe_n20)
+);
+
+ODDRX2DQA ODDRX2DQA_24(
+ .D0(ddrphy_dq_o_data_muxed21[0]),
+ .D1(ddrphy_dq_o_data_muxed21[1]),
+ .D2(ddrphy_dq_o_data_muxed21[2]),
+ .D3(ddrphy_dq_o_data_muxed21[3]),
+ .DQSW270(ddrphy_dqsw2702),
+ .ECLK(sys2x_clk),
+ .RST(sys_rst),
+ .SCLK(sys_clk),
+ .Q(ddrphy_dq_o21)
+);
+
+DELAYG #(
+ .DEL_MODE("DQS_ALIGNED_X2")
+) DELAYG_48 (
+ .A(ddrphy_dq_i21),
+ .Z(ddrphy_dq_i_delayed21)
+);
+
+IDDRX2DQA IDDRX2DQA_21(
+ .D(ddrphy_dq_i_delayed21),
+ .DQSR90(ddrphy_dqsr902),
+ .ECLK(sys2x_clk),
+ .RDPNTR0(ddrphy_rdpntr2[0]),
+ .RDPNTR1(ddrphy_rdpntr2[1]),
+ .RDPNTR2(ddrphy_rdpntr2[2]),
+ .RST(sys_rst),
+ .SCLK(sys_clk),
+ .WRPNTR0(ddrphy_wrpntr2[0]),
+ .WRPNTR1(ddrphy_wrpntr2[1]),
+ .WRPNTR2(ddrphy_wrpntr2[2]),
+ .Q0(ddrphy_bitslip21_i[0]),
+ .Q1(ddrphy_bitslip21_i[1]),
+ .Q2(ddrphy_bitslip21_i[2]),
+ .Q3(ddrphy_bitslip21_i[3])
+);
+
+TSHX2DQA TSHX2DQA_21(
+ .DQSW270(ddrphy_dqsw2702),
+ .ECLK(sys2x_clk),
+ .RST(sys_rst),
+ .SCLK(sys_clk),
+ .T0((~ddrphy_dq_oe)),
+ .T1((~ddrphy_dq_oe)),
+ .Q(ddrphy_dq_oe_n21)
+);
+
+ODDRX2DQA ODDRX2DQA_25(
+ .D0(ddrphy_dq_o_data_muxed22[0]),
+ .D1(ddrphy_dq_o_data_muxed22[1]),
+ .D2(ddrphy_dq_o_data_muxed22[2]),
+ .D3(ddrphy_dq_o_data_muxed22[3]),
+ .DQSW270(ddrphy_dqsw2702),
+ .ECLK(sys2x_clk),
+ .RST(sys_rst),
+ .SCLK(sys_clk),
+ .Q(ddrphy_dq_o22)
+);
+
+DELAYG #(
+ .DEL_MODE("DQS_ALIGNED_X2")
+) DELAYG_49 (
+ .A(ddrphy_dq_i22),
+ .Z(ddrphy_dq_i_delayed22)
+);
+
+IDDRX2DQA IDDRX2DQA_22(
+ .D(ddrphy_dq_i_delayed22),
+ .DQSR90(ddrphy_dqsr902),
+ .ECLK(sys2x_clk),
+ .RDPNTR0(ddrphy_rdpntr2[0]),
+ .RDPNTR1(ddrphy_rdpntr2[1]),
+ .RDPNTR2(ddrphy_rdpntr2[2]),
+ .RST(sys_rst),
+ .SCLK(sys_clk),
+ .WRPNTR0(ddrphy_wrpntr2[0]),
+ .WRPNTR1(ddrphy_wrpntr2[1]),
+ .WRPNTR2(ddrphy_wrpntr2[2]),
+ .Q0(ddrphy_bitslip22_i[0]),
+ .Q1(ddrphy_bitslip22_i[1]),
+ .Q2(ddrphy_bitslip22_i[2]),
+ .Q3(ddrphy_bitslip22_i[3])
+);
+
+TSHX2DQA TSHX2DQA_22(
+ .DQSW270(ddrphy_dqsw2702),
+ .ECLK(sys2x_clk),
+ .RST(sys_rst),
+ .SCLK(sys_clk),
+ .T0((~ddrphy_dq_oe)),
+ .T1((~ddrphy_dq_oe)),
+ .Q(ddrphy_dq_oe_n22)
+);
+
+ODDRX2DQA ODDRX2DQA_26(
+ .D0(ddrphy_dq_o_data_muxed23[0]),
+ .D1(ddrphy_dq_o_data_muxed23[1]),
+ .D2(ddrphy_dq_o_data_muxed23[2]),
+ .D3(ddrphy_dq_o_data_muxed23[3]),
+ .DQSW270(ddrphy_dqsw2702),
+ .ECLK(sys2x_clk),
+ .RST(sys_rst),
+ .SCLK(sys_clk),
+ .Q(ddrphy_dq_o23)
+);
+
+DELAYG #(
+ .DEL_MODE("DQS_ALIGNED_X2")
+) DELAYG_50 (
+ .A(ddrphy_dq_i23),
+ .Z(ddrphy_dq_i_delayed23)
+);
+
+IDDRX2DQA IDDRX2DQA_23(
+ .D(ddrphy_dq_i_delayed23),
+ .DQSR90(ddrphy_dqsr902),
+ .ECLK(sys2x_clk),
+ .RDPNTR0(ddrphy_rdpntr2[0]),
+ .RDPNTR1(ddrphy_rdpntr2[1]),
+ .RDPNTR2(ddrphy_rdpntr2[2]),
+ .RST(sys_rst),
+ .SCLK(sys_clk),
+ .WRPNTR0(ddrphy_wrpntr2[0]),
+ .WRPNTR1(ddrphy_wrpntr2[1]),
+ .WRPNTR2(ddrphy_wrpntr2[2]),
+ .Q0(ddrphy_bitslip23_i[0]),
+ .Q1(ddrphy_bitslip23_i[1]),
+ .Q2(ddrphy_bitslip23_i[2]),
+ .Q3(ddrphy_bitslip23_i[3])
+);
+
+TSHX2DQA TSHX2DQA_23(
+ .DQSW270(ddrphy_dqsw2702),
+ .ECLK(sys2x_clk),
+ .RST(sys_rst),
+ .SCLK(sys_clk),
+ .T0((~ddrphy_dq_oe)),
+ .T1((~ddrphy_dq_oe)),
+ .Q(ddrphy_dq_oe_n23)
+);
+
+DQSBUFM #(
+ .DQS_LI_DEL_ADJ("MINUS"),
+ .DQS_LI_DEL_VAL(1'd1),
+ .DQS_LO_DEL_ADJ("MINUS"),
+ .DQS_LO_DEL_VAL(3'd4)
+) DQSBUFM_3 (
+ .DDRDEL(ddrphy_delay0),
+ .DQSI(ddrphy_dqs_i3),
+ .ECLK(sys2x_clk),
+ .PAUSE((ddrphy_pause0 | ddrphy_dly_sel_storage[3])),
+ .RDDIRECTION(1'd1),
+ .RDLOADN(1'd0),
+ .RDMOVE(1'd0),
+ .READ0(ddrphy_dqs_re),
+ .READ1(ddrphy_dqs_re),
+ .READCLKSEL0(ddrphy_rdly3[0]),
+ .READCLKSEL1(ddrphy_rdly3[1]),
+ .READCLKSEL2(ddrphy_rdly3[2]),
+ .RST(sys_rst),
+ .SCLK(sys_clk),
+ .WRDIRECTION(1'd1),
+ .WRLOADN(1'd0),
+ .WRMOVE(1'd0),
+ .BURSTDET(ddrphy_burstdet3),
+ .DATAVALID(ddrphy_datavalid[3]),
+ .DQSR90(ddrphy_dqsr903),
+ .DQSW(ddrphy_dqsw3),
+ .DQSW270(ddrphy_dqsw2703),
+ .RDPNTR0(ddrphy_rdpntr3[0]),
+ .RDPNTR1(ddrphy_rdpntr3[1]),
+ .RDPNTR2(ddrphy_rdpntr3[2]),
+ .WRPNTR0(ddrphy_wrpntr3[0]),
+ .WRPNTR1(ddrphy_wrpntr3[1]),
+ .WRPNTR2(ddrphy_wrpntr3[2])
+);
+
+ODDRX2DQSB ODDRX2DQSB_3(
+ .D0(1'd0),
+ .D1(1'd1),
+ .D2(1'd0),
+ .D3(1'd1),
+ .DQSW(ddrphy_dqsw3),
+ .ECLK(sys2x_clk),
+ .RST(sys_rst),
+ .SCLK(sys_clk),
+ .Q(ddrphy_dqs3)
+);
+
+TSHX2DQSA TSHX2DQSA_3(
+ .DQSW(ddrphy_dqsw3),
+ .ECLK(sys2x_clk),
+ .RST(sys_rst),
+ .SCLK(sys_clk),
+ .T0((~(ddrphy_dqs_oe | ddrphy_dqs_postamble))),
+ .T1((~(ddrphy_dqs_oe | ddrphy_dqs_preamble))),
+ .Q(ddrphy_dqs_oe_n3)
+);
+
+ODDRX2DQA ODDRX2DQA_27(
+ .D0(ddrphy_dm_o_data_muxed3[0]),
+ .D1(ddrphy_dm_o_data_muxed3[1]),
+ .D2(ddrphy_dm_o_data_muxed3[2]),
+ .D3(ddrphy_dm_o_data_muxed3[3]),
+ .DQSW270(ddrphy_dqsw2703),
+ .ECLK(sys2x_clk),
+ .RST(sys_rst),
+ .SCLK(sys_clk),
+ .Q(ddram_dm[3])
+);
+
+ODDRX2DQA ODDRX2DQA_28(
+ .D0(ddrphy_dq_o_data_muxed24[0]),
+ .D1(ddrphy_dq_o_data_muxed24[1]),
+ .D2(ddrphy_dq_o_data_muxed24[2]),
+ .D3(ddrphy_dq_o_data_muxed24[3]),
+ .DQSW270(ddrphy_dqsw2703),
+ .ECLK(sys2x_clk),
+ .RST(sys_rst),
+ .SCLK(sys_clk),
+ .Q(ddrphy_dq_o24)
+);
+
+DELAYG #(
+ .DEL_MODE("DQS_ALIGNED_X2")
+) DELAYG_51 (
+ .A(ddrphy_dq_i24),
+ .Z(ddrphy_dq_i_delayed24)
+);
+
+IDDRX2DQA IDDRX2DQA_24(
+ .D(ddrphy_dq_i_delayed24),
+ .DQSR90(ddrphy_dqsr903),
+ .ECLK(sys2x_clk),
+ .RDPNTR0(ddrphy_rdpntr3[0]),
+ .RDPNTR1(ddrphy_rdpntr3[1]),
+ .RDPNTR2(ddrphy_rdpntr3[2]),
+ .RST(sys_rst),
+ .SCLK(sys_clk),
+ .WRPNTR0(ddrphy_wrpntr3[0]),
+ .WRPNTR1(ddrphy_wrpntr3[1]),
+ .WRPNTR2(ddrphy_wrpntr3[2]),
+ .Q0(ddrphy_bitslip24_i[0]),
+ .Q1(ddrphy_bitslip24_i[1]),
+ .Q2(ddrphy_bitslip24_i[2]),
+ .Q3(ddrphy_bitslip24_i[3])
+);
+
+TSHX2DQA TSHX2DQA_24(
+ .DQSW270(ddrphy_dqsw2703),
+ .ECLK(sys2x_clk),
+ .RST(sys_rst),
+ .SCLK(sys_clk),
+ .T0((~ddrphy_dq_oe)),
+ .T1((~ddrphy_dq_oe)),
+ .Q(ddrphy_dq_oe_n24)
+);
+
+ODDRX2DQA ODDRX2DQA_29(
+ .D0(ddrphy_dq_o_data_muxed25[0]),
+ .D1(ddrphy_dq_o_data_muxed25[1]),
+ .D2(ddrphy_dq_o_data_muxed25[2]),
+ .D3(ddrphy_dq_o_data_muxed25[3]),
+ .DQSW270(ddrphy_dqsw2703),
+ .ECLK(sys2x_clk),
+ .RST(sys_rst),
+ .SCLK(sys_clk),
+ .Q(ddrphy_dq_o25)
+);
+
+DELAYG #(
+ .DEL_MODE("DQS_ALIGNED_X2")
+) DELAYG_52 (
+ .A(ddrphy_dq_i25),
+ .Z(ddrphy_dq_i_delayed25)
+);
+
+IDDRX2DQA IDDRX2DQA_25(
+ .D(ddrphy_dq_i_delayed25),
+ .DQSR90(ddrphy_dqsr903),
+ .ECLK(sys2x_clk),
+ .RDPNTR0(ddrphy_rdpntr3[0]),
+ .RDPNTR1(ddrphy_rdpntr3[1]),
+ .RDPNTR2(ddrphy_rdpntr3[2]),
+ .RST(sys_rst),
+ .SCLK(sys_clk),
+ .WRPNTR0(ddrphy_wrpntr3[0]),
+ .WRPNTR1(ddrphy_wrpntr3[1]),
+ .WRPNTR2(ddrphy_wrpntr3[2]),
+ .Q0(ddrphy_bitslip25_i[0]),
+ .Q1(ddrphy_bitslip25_i[1]),
+ .Q2(ddrphy_bitslip25_i[2]),
+ .Q3(ddrphy_bitslip25_i[3])
+);
+
+TSHX2DQA TSHX2DQA_25(
+ .DQSW270(ddrphy_dqsw2703),
+ .ECLK(sys2x_clk),
+ .RST(sys_rst),
+ .SCLK(sys_clk),
+ .T0((~ddrphy_dq_oe)),
+ .T1((~ddrphy_dq_oe)),
+ .Q(ddrphy_dq_oe_n25)
+);
+
+ODDRX2DQA ODDRX2DQA_30(
+ .D0(ddrphy_dq_o_data_muxed26[0]),
+ .D1(ddrphy_dq_o_data_muxed26[1]),
+ .D2(ddrphy_dq_o_data_muxed26[2]),
+ .D3(ddrphy_dq_o_data_muxed26[3]),
+ .DQSW270(ddrphy_dqsw2703),
+ .ECLK(sys2x_clk),
+ .RST(sys_rst),
+ .SCLK(sys_clk),
+ .Q(ddrphy_dq_o26)
+);
+
+DELAYG #(
+ .DEL_MODE("DQS_ALIGNED_X2")
+) DELAYG_53 (
+ .A(ddrphy_dq_i26),
+ .Z(ddrphy_dq_i_delayed26)
+);
+
+IDDRX2DQA IDDRX2DQA_26(
+ .D(ddrphy_dq_i_delayed26),
+ .DQSR90(ddrphy_dqsr903),
+ .ECLK(sys2x_clk),
+ .RDPNTR0(ddrphy_rdpntr3[0]),
+ .RDPNTR1(ddrphy_rdpntr3[1]),
+ .RDPNTR2(ddrphy_rdpntr3[2]),
+ .RST(sys_rst),
+ .SCLK(sys_clk),
+ .WRPNTR0(ddrphy_wrpntr3[0]),
+ .WRPNTR1(ddrphy_wrpntr3[1]),
+ .WRPNTR2(ddrphy_wrpntr3[2]),
+ .Q0(ddrphy_bitslip26_i[0]),
+ .Q1(ddrphy_bitslip26_i[1]),
+ .Q2(ddrphy_bitslip26_i[2]),
+ .Q3(ddrphy_bitslip26_i[3])
+);
+
+TSHX2DQA TSHX2DQA_26(
+ .DQSW270(ddrphy_dqsw2703),
+ .ECLK(sys2x_clk),
+ .RST(sys_rst),
+ .SCLK(sys_clk),
+ .T0((~ddrphy_dq_oe)),
+ .T1((~ddrphy_dq_oe)),
+ .Q(ddrphy_dq_oe_n26)
+);
+
+ODDRX2DQA ODDRX2DQA_31(
+ .D0(ddrphy_dq_o_data_muxed27[0]),
+ .D1(ddrphy_dq_o_data_muxed27[1]),
+ .D2(ddrphy_dq_o_data_muxed27[2]),
+ .D3(ddrphy_dq_o_data_muxed27[3]),
+ .DQSW270(ddrphy_dqsw2703),
+ .ECLK(sys2x_clk),
+ .RST(sys_rst),
+ .SCLK(sys_clk),
+ .Q(ddrphy_dq_o27)
+);
+
+DELAYG #(
+ .DEL_MODE("DQS_ALIGNED_X2")
+) DELAYG_54 (
+ .A(ddrphy_dq_i27),
+ .Z(ddrphy_dq_i_delayed27)
+);
+
+IDDRX2DQA IDDRX2DQA_27(
+ .D(ddrphy_dq_i_delayed27),
+ .DQSR90(ddrphy_dqsr903),
+ .ECLK(sys2x_clk),
+ .RDPNTR0(ddrphy_rdpntr3[0]),
+ .RDPNTR1(ddrphy_rdpntr3[1]),
+ .RDPNTR2(ddrphy_rdpntr3[2]),
+ .RST(sys_rst),
+ .SCLK(sys_clk),
+ .WRPNTR0(ddrphy_wrpntr3[0]),
+ .WRPNTR1(ddrphy_wrpntr3[1]),
+ .WRPNTR2(ddrphy_wrpntr3[2]),
+ .Q0(ddrphy_bitslip27_i[0]),
+ .Q1(ddrphy_bitslip27_i[1]),
+ .Q2(ddrphy_bitslip27_i[2]),
+ .Q3(ddrphy_bitslip27_i[3])
+);
+
+TSHX2DQA TSHX2DQA_27(
+ .DQSW270(ddrphy_dqsw2703),
+ .ECLK(sys2x_clk),
+ .RST(sys_rst),
+ .SCLK(sys_clk),
+ .T0((~ddrphy_dq_oe)),
+ .T1((~ddrphy_dq_oe)),
+ .Q(ddrphy_dq_oe_n27)
+);
+
+ODDRX2DQA ODDRX2DQA_32(
+ .D0(ddrphy_dq_o_data_muxed28[0]),
+ .D1(ddrphy_dq_o_data_muxed28[1]),
+ .D2(ddrphy_dq_o_data_muxed28[2]),
+ .D3(ddrphy_dq_o_data_muxed28[3]),
+ .DQSW270(ddrphy_dqsw2703),
+ .ECLK(sys2x_clk),
+ .RST(sys_rst),
+ .SCLK(sys_clk),
+ .Q(ddrphy_dq_o28)
+);
+
+DELAYG #(
+ .DEL_MODE("DQS_ALIGNED_X2")
+) DELAYG_55 (
+ .A(ddrphy_dq_i28),
+ .Z(ddrphy_dq_i_delayed28)
+);
+
+IDDRX2DQA IDDRX2DQA_28(
+ .D(ddrphy_dq_i_delayed28),
+ .DQSR90(ddrphy_dqsr903),
+ .ECLK(sys2x_clk),
+ .RDPNTR0(ddrphy_rdpntr3[0]),
+ .RDPNTR1(ddrphy_rdpntr3[1]),
+ .RDPNTR2(ddrphy_rdpntr3[2]),
+ .RST(sys_rst),
+ .SCLK(sys_clk),
+ .WRPNTR0(ddrphy_wrpntr3[0]),
+ .WRPNTR1(ddrphy_wrpntr3[1]),
+ .WRPNTR2(ddrphy_wrpntr3[2]),
+ .Q0(ddrphy_bitslip28_i[0]),
+ .Q1(ddrphy_bitslip28_i[1]),
+ .Q2(ddrphy_bitslip28_i[2]),
+ .Q3(ddrphy_bitslip28_i[3])
+);
+
+TSHX2DQA TSHX2DQA_28(
+ .DQSW270(ddrphy_dqsw2703),
+ .ECLK(sys2x_clk),
+ .RST(sys_rst),
+ .SCLK(sys_clk),
+ .T0((~ddrphy_dq_oe)),
+ .T1((~ddrphy_dq_oe)),
+ .Q(ddrphy_dq_oe_n28)
+);
+
+ODDRX2DQA ODDRX2DQA_33(
+ .D0(ddrphy_dq_o_data_muxed29[0]),
+ .D1(ddrphy_dq_o_data_muxed29[1]),
+ .D2(ddrphy_dq_o_data_muxed29[2]),
+ .D3(ddrphy_dq_o_data_muxed29[3]),
+ .DQSW270(ddrphy_dqsw2703),
+ .ECLK(sys2x_clk),
+ .RST(sys_rst),
+ .SCLK(sys_clk),
+ .Q(ddrphy_dq_o29)
+);
+
+DELAYG #(
+ .DEL_MODE("DQS_ALIGNED_X2")
+) DELAYG_56 (
+ .A(ddrphy_dq_i29),
+ .Z(ddrphy_dq_i_delayed29)
+);
+
+IDDRX2DQA IDDRX2DQA_29(
+ .D(ddrphy_dq_i_delayed29),
+ .DQSR90(ddrphy_dqsr903),
+ .ECLK(sys2x_clk),
+ .RDPNTR0(ddrphy_rdpntr3[0]),
+ .RDPNTR1(ddrphy_rdpntr3[1]),
+ .RDPNTR2(ddrphy_rdpntr3[2]),
+ .RST(sys_rst),
+ .SCLK(sys_clk),
+ .WRPNTR0(ddrphy_wrpntr3[0]),
+ .WRPNTR1(ddrphy_wrpntr3[1]),
+ .WRPNTR2(ddrphy_wrpntr3[2]),
+ .Q0(ddrphy_bitslip29_i[0]),
+ .Q1(ddrphy_bitslip29_i[1]),
+ .Q2(ddrphy_bitslip29_i[2]),
+ .Q3(ddrphy_bitslip29_i[3])
+);
+
+TSHX2DQA TSHX2DQA_29(
+ .DQSW270(ddrphy_dqsw2703),
+ .ECLK(sys2x_clk),
+ .RST(sys_rst),
+ .SCLK(sys_clk),
+ .T0((~ddrphy_dq_oe)),
+ .T1((~ddrphy_dq_oe)),
+ .Q(ddrphy_dq_oe_n29)
+);
+
+ODDRX2DQA ODDRX2DQA_34(
+ .D0(ddrphy_dq_o_data_muxed30[0]),
+ .D1(ddrphy_dq_o_data_muxed30[1]),
+ .D2(ddrphy_dq_o_data_muxed30[2]),
+ .D3(ddrphy_dq_o_data_muxed30[3]),
+ .DQSW270(ddrphy_dqsw2703),
+ .ECLK(sys2x_clk),
+ .RST(sys_rst),
+ .SCLK(sys_clk),
+ .Q(ddrphy_dq_o30)
+);
+
+DELAYG #(
+ .DEL_MODE("DQS_ALIGNED_X2")
+) DELAYG_57 (
+ .A(ddrphy_dq_i30),
+ .Z(ddrphy_dq_i_delayed30)
+);
+
+IDDRX2DQA IDDRX2DQA_30(
+ .D(ddrphy_dq_i_delayed30),
+ .DQSR90(ddrphy_dqsr903),
+ .ECLK(sys2x_clk),
+ .RDPNTR0(ddrphy_rdpntr3[0]),
+ .RDPNTR1(ddrphy_rdpntr3[1]),
+ .RDPNTR2(ddrphy_rdpntr3[2]),
+ .RST(sys_rst),
+ .SCLK(sys_clk),
+ .WRPNTR0(ddrphy_wrpntr3[0]),
+ .WRPNTR1(ddrphy_wrpntr3[1]),
+ .WRPNTR2(ddrphy_wrpntr3[2]),
+ .Q0(ddrphy_bitslip30_i[0]),
+ .Q1(ddrphy_bitslip30_i[1]),
+ .Q2(ddrphy_bitslip30_i[2]),
+ .Q3(ddrphy_bitslip30_i[3])
+);
+
+TSHX2DQA TSHX2DQA_30(
+ .DQSW270(ddrphy_dqsw2703),
+ .ECLK(sys2x_clk),
+ .RST(sys_rst),
+ .SCLK(sys_clk),
+ .T0((~ddrphy_dq_oe)),
+ .T1((~ddrphy_dq_oe)),
+ .Q(ddrphy_dq_oe_n30)
+);
+
+ODDRX2DQA ODDRX2DQA_35(
+ .D0(ddrphy_dq_o_data_muxed31[0]),
+ .D1(ddrphy_dq_o_data_muxed31[1]),
+ .D2(ddrphy_dq_o_data_muxed31[2]),
+ .D3(ddrphy_dq_o_data_muxed31[3]),
+ .DQSW270(ddrphy_dqsw2703),
+ .ECLK(sys2x_clk),
+ .RST(sys_rst),
+ .SCLK(sys_clk),
+ .Q(ddrphy_dq_o31)
+);
+
+DELAYG #(
+ .DEL_MODE("DQS_ALIGNED_X2")
+) DELAYG_58 (
+ .A(ddrphy_dq_i31),
+ .Z(ddrphy_dq_i_delayed31)
+);
+
+IDDRX2DQA IDDRX2DQA_31(
+ .D(ddrphy_dq_i_delayed31),
+ .DQSR90(ddrphy_dqsr903),
+ .ECLK(sys2x_clk),
+ .RDPNTR0(ddrphy_rdpntr3[0]),
+ .RDPNTR1(ddrphy_rdpntr3[1]),
+ .RDPNTR2(ddrphy_rdpntr3[2]),
+ .RST(sys_rst),
+ .SCLK(sys_clk),
+ .WRPNTR0(ddrphy_wrpntr3[0]),
+ .WRPNTR1(ddrphy_wrpntr3[1]),
+ .WRPNTR2(ddrphy_wrpntr3[2]),
+ .Q0(ddrphy_bitslip31_i[0]),
+ .Q1(ddrphy_bitslip31_i[1]),
+ .Q2(ddrphy_bitslip31_i[2]),
+ .Q3(ddrphy_bitslip31_i[3])
+);
+
+TSHX2DQA TSHX2DQA_31(
+ .DQSW270(ddrphy_dqsw2703),
+ .ECLK(sys2x_clk),
+ .RST(sys_rst),
+ .SCLK(sys_clk),
+ .T0((~ddrphy_dq_oe)),
+ .T1((~ddrphy_dq_oe)),
+ .Q(ddrphy_dq_oe_n31)
+);
+
+//------------------------------------------------------------------------------
+// Memory storage: 16-words x 25-bit
+//------------------------------------------------------------------------------
+// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 25
+// Port 1 | Read: Async | Write: ---- |
+reg [24:0] storage[0:15];
+reg [24:0] storage_dat0;
+always @(posedge sys_clk) begin
+ if (litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we)
+ storage[litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w;
+ storage_dat0 <= storage[litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr];
+end
+always @(posedge sys_clk) begin
+end
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_r = storage_dat0;
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_dat_r = storage[litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_adr];
+
+
+//------------------------------------------------------------------------------
+// Memory storage_1: 16-words x 25-bit
+//------------------------------------------------------------------------------
+// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 25
+// Port 1 | Read: Async | Write: ---- |
+reg [24:0] storage_1[0:15];
+reg [24:0] storage_1_dat0;
+always @(posedge sys_clk) begin
+ if (litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we)
+ storage_1[litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w;
+ storage_1_dat0 <= storage_1[litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr];
+end
+always @(posedge sys_clk) begin
+end
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_r = storage_1_dat0;
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_dat_r = storage_1[litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_adr];
+
+
+//------------------------------------------------------------------------------
+// Memory storage_2: 16-words x 25-bit
+//------------------------------------------------------------------------------
+// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 25
+// Port 1 | Read: Async | Write: ---- |
+reg [24:0] storage_2[0:15];
+reg [24:0] storage_2_dat0;
+always @(posedge sys_clk) begin
+ if (litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we)
+ storage_2[litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w;
+ storage_2_dat0 <= storage_2[litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr];
+end
+always @(posedge sys_clk) begin
+end
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_r = storage_2_dat0;
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_dat_r = storage_2[litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_adr];
+
+
+//------------------------------------------------------------------------------
+// Memory storage_3: 16-words x 25-bit
+//------------------------------------------------------------------------------
+// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 25
+// Port 1 | Read: Async | Write: ---- |
+reg [24:0] storage_3[0:15];
+reg [24:0] storage_3_dat0;
+always @(posedge sys_clk) begin
+ if (litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we)
+ storage_3[litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w;
+ storage_3_dat0 <= storage_3[litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr];
+end
+always @(posedge sys_clk) begin
+end
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_r = storage_3_dat0;
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_dat_r = storage_3[litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_adr];
+
+
+//------------------------------------------------------------------------------
+// Memory storage_4: 16-words x 25-bit
+//------------------------------------------------------------------------------
+// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 25
+// Port 1 | Read: Async | Write: ---- |
+reg [24:0] storage_4[0:15];
+reg [24:0] storage_4_dat0;
+always @(posedge sys_clk) begin
+ if (litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we)
+ storage_4[litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w;
+ storage_4_dat0 <= storage_4[litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr];
+end
+always @(posedge sys_clk) begin
+end
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_r = storage_4_dat0;
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_dat_r = storage_4[litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_adr];
+
+
+//------------------------------------------------------------------------------
+// Memory storage_5: 16-words x 25-bit
+//------------------------------------------------------------------------------
+// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 25
+// Port 1 | Read: Async | Write: ---- |
+reg [24:0] storage_5[0:15];
+reg [24:0] storage_5_dat0;
+always @(posedge sys_clk) begin
+ if (litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we)
+ storage_5[litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w;
+ storage_5_dat0 <= storage_5[litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr];
+end
+always @(posedge sys_clk) begin
+end
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_r = storage_5_dat0;
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_dat_r = storage_5[litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_adr];
+
+
+//------------------------------------------------------------------------------
+// Memory storage_6: 16-words x 25-bit
+//------------------------------------------------------------------------------
+// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 25
+// Port 1 | Read: Async | Write: ---- |
+reg [24:0] storage_6[0:15];
+reg [24:0] storage_6_dat0;
+always @(posedge sys_clk) begin
+ if (litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we)
+ storage_6[litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w;
+ storage_6_dat0 <= storage_6[litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr];
+end
+always @(posedge sys_clk) begin
+end
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_r = storage_6_dat0;
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_dat_r = storage_6[litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_adr];
+
+
+//------------------------------------------------------------------------------
+// Memory storage_7: 16-words x 25-bit
+//------------------------------------------------------------------------------
+// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 25
+// Port 1 | Read: Async | Write: ---- |
+reg [24:0] storage_7[0:15];
+reg [24:0] storage_7_dat0;
+always @(posedge sys_clk) begin
+ if (litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we)
+ storage_7[litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w;
+ storage_7_dat0 <= storage_7[litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr];
+end
+always @(posedge sys_clk) begin
+end
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_r = storage_7_dat0;
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_dat_r = storage_7[litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_adr];
+
+
+(* FREQUENCY_PIN_CLKI = "125.0", FREQUENCY_PIN_CLKOP = "96.0", FREQUENCY_PIN_CLKOS = "24.0", ICP_CURRENT = "6", LPF_RESISTOR = "16", MFG_ENABLE_FILTEROPAMP = "1", MFG_GMCREF_SEL = "2" *) EHXPLLL #(
+ .CLKFB_DIV(5'd16),
+ .CLKI_DIV(2'd3),
+ .CLKOP_CPHASE(3'd6),
+ .CLKOP_DIV(3'd7),
+ .CLKOP_ENABLE("ENABLED"),
+ .CLKOP_FPHASE(1'd0),
+ .CLKOS2_CPHASE(1'd0),
+ .CLKOS2_DIV(1'd1),
+ .CLKOS2_ENABLE("ENABLED"),
+ .CLKOS2_FPHASE(1'd0),
+ .CLKOS_CPHASE(5'd27),
+ .CLKOS_DIV(5'd28),
+ .CLKOS_ENABLE("ENABLED"),
+ .CLKOS_FPHASE(1'd0),
+ .FEEDBK_PATH("INT_OS2")
+) EHXPLLL (
+ .CLKI(crg_clkin),
+ .RST(crg_reset1),
+ .STDBY(crg_stdby),
+ .CLKOP(crg_clkout0),
+ .CLKOS(crg_clkout1),
+ .CLKOS2(litedramecp5ddrphycrg_ecp5pll),
+ .LOCK(litedramecp5ddrphycrg_locked)
+);
+
+FD1S3BX FD1S3BX(
+ .CK(sys2x_i_clk),
+ .D(1'd0),
+ .PD((~crg_locked)),
+ .Q(latticeecp5asyncresetsynchronizerimpl0_rst1)
+);
+
+FD1S3BX FD1S3BX_1(
+ .CK(sys2x_i_clk),
+ .D(latticeecp5asyncresetsynchronizerimpl0_rst1),
+ .PD((~crg_locked)),
+ .Q(latticeecp5asyncresetsynchronizerimpl0_expr)
+);
+
+FD1S3BX FD1S3BX_2(
+ .CK(init_clk),
+ .D(1'd0),
+ .PD((~crg_locked)),
+ .Q(latticeecp5asyncresetsynchronizerimpl1_rst1)
+);
+
+FD1S3BX FD1S3BX_3(
+ .CK(init_clk),
+ .D(latticeecp5asyncresetsynchronizerimpl1_rst1),
+ .PD((~crg_locked)),
+ .Q(init_rst)
+);
+
+FD1S3BX FD1S3BX_4(
+ .CK(sys_clk),
+ .D(1'd0),
+ .PD(((~crg_locked) | crg_reset0)),
+ .Q(latticeecp5asyncresetsynchronizerimpl2_rst1)
+);
+
+FD1S3BX FD1S3BX_5(
+ .CK(sys_clk),
+ .D(latticeecp5asyncresetsynchronizerimpl2_rst1),
+ .PD(((~crg_locked) | crg_reset0)),
+ .Q(sys_rst)
+);
+
+FD1S3BX FD1S3BX_6(
+ .CK(sys2x_clk),
+ .D(1'd0),
+ .PD(((~crg_locked) | crg_reset0)),
+ .Q(latticeecp5asyncresetsynchronizerimpl3_rst1)
+);
+
+FD1S3BX FD1S3BX_7(
+ .CK(sys2x_clk),
+ .D(latticeecp5asyncresetsynchronizerimpl3_rst1),
+ .PD(((~crg_locked) | crg_reset0)),
+ .Q(sys2x_rst)
+);
+
+TRELLIS_IO #(
+ .DIR("BIDIR")
+) TRELLIS_IO (
+ .B(ddram_dqs_p[0]),
+ .I(ddrphy_dqs0),
+ .T((~(~ddrphy_dqs_oe_n0))),
+ .O(ddrphy_dqs_i0)
+);
+
+TRELLIS_IO #(
+ .DIR("BIDIR")
+) TRELLIS_IO_1 (
+ .B(ddram_dq[0]),
+ .I(ddrphy_dq_o0),
+ .T((~(~ddrphy_dq_oe_n0))),
+ .O(ddrphy_dq_i0)
+);
+
+TRELLIS_IO #(
+ .DIR("BIDIR")
+) TRELLIS_IO_2 (
+ .B(ddram_dq[1]),
+ .I(ddrphy_dq_o1),
+ .T((~(~ddrphy_dq_oe_n1))),
+ .O(ddrphy_dq_i1)
+);
+
+TRELLIS_IO #(
+ .DIR("BIDIR")
+) TRELLIS_IO_3 (
+ .B(ddram_dq[2]),
+ .I(ddrphy_dq_o2),
+ .T((~(~ddrphy_dq_oe_n2))),
+ .O(ddrphy_dq_i2)
+);
+
+TRELLIS_IO #(
+ .DIR("BIDIR")
+) TRELLIS_IO_4 (
+ .B(ddram_dq[3]),
+ .I(ddrphy_dq_o3),
+ .T((~(~ddrphy_dq_oe_n3))),
+ .O(ddrphy_dq_i3)
+);
+
+TRELLIS_IO #(
+ .DIR("BIDIR")
+) TRELLIS_IO_5 (
+ .B(ddram_dq[4]),
+ .I(ddrphy_dq_o4),
+ .T((~(~ddrphy_dq_oe_n4))),
+ .O(ddrphy_dq_i4)
+);
+
+TRELLIS_IO #(
+ .DIR("BIDIR")
+) TRELLIS_IO_6 (
+ .B(ddram_dq[5]),
+ .I(ddrphy_dq_o5),
+ .T((~(~ddrphy_dq_oe_n5))),
+ .O(ddrphy_dq_i5)
+);
+
+TRELLIS_IO #(
+ .DIR("BIDIR")
+) TRELLIS_IO_7 (
+ .B(ddram_dq[6]),
+ .I(ddrphy_dq_o6),
+ .T((~(~ddrphy_dq_oe_n6))),
+ .O(ddrphy_dq_i6)
+);
+
+TRELLIS_IO #(
+ .DIR("BIDIR")
+) TRELLIS_IO_8 (
+ .B(ddram_dq[7]),
+ .I(ddrphy_dq_o7),
+ .T((~(~ddrphy_dq_oe_n7))),
+ .O(ddrphy_dq_i7)
+);
+
+TRELLIS_IO #(
+ .DIR("BIDIR")
+) TRELLIS_IO_9 (
+ .B(ddram_dqs_p[1]),
+ .I(ddrphy_dqs1),
+ .T((~(~ddrphy_dqs_oe_n1))),
+ .O(ddrphy_dqs_i1)
+);
+
+TRELLIS_IO #(
+ .DIR("BIDIR")
+) TRELLIS_IO_10 (
+ .B(ddram_dq[8]),
+ .I(ddrphy_dq_o8),
+ .T((~(~ddrphy_dq_oe_n8))),
+ .O(ddrphy_dq_i8)
+);
+
+TRELLIS_IO #(
+ .DIR("BIDIR")
+) TRELLIS_IO_11 (
+ .B(ddram_dq[9]),
+ .I(ddrphy_dq_o9),
+ .T((~(~ddrphy_dq_oe_n9))),
+ .O(ddrphy_dq_i9)
+);
+
+TRELLIS_IO #(
+ .DIR("BIDIR")
+) TRELLIS_IO_12 (
+ .B(ddram_dq[10]),
+ .I(ddrphy_dq_o10),
+ .T((~(~ddrphy_dq_oe_n10))),
+ .O(ddrphy_dq_i10)
+);
+
+TRELLIS_IO #(
+ .DIR("BIDIR")
+) TRELLIS_IO_13 (
+ .B(ddram_dq[11]),
+ .I(ddrphy_dq_o11),
+ .T((~(~ddrphy_dq_oe_n11))),
+ .O(ddrphy_dq_i11)
+);
+
+TRELLIS_IO #(
+ .DIR("BIDIR")
+) TRELLIS_IO_14 (
+ .B(ddram_dq[12]),
+ .I(ddrphy_dq_o12),
+ .T((~(~ddrphy_dq_oe_n12))),
+ .O(ddrphy_dq_i12)
+);
+
+TRELLIS_IO #(
+ .DIR("BIDIR")
+) TRELLIS_IO_15 (
+ .B(ddram_dq[13]),
+ .I(ddrphy_dq_o13),
+ .T((~(~ddrphy_dq_oe_n13))),
+ .O(ddrphy_dq_i13)
+);
+
+TRELLIS_IO #(
+ .DIR("BIDIR")
+) TRELLIS_IO_16 (
+ .B(ddram_dq[14]),
+ .I(ddrphy_dq_o14),
+ .T((~(~ddrphy_dq_oe_n14))),
+ .O(ddrphy_dq_i14)
+);
+
+TRELLIS_IO #(
+ .DIR("BIDIR")
+) TRELLIS_IO_17 (
+ .B(ddram_dq[15]),
+ .I(ddrphy_dq_o15),
+ .T((~(~ddrphy_dq_oe_n15))),
+ .O(ddrphy_dq_i15)
+);
+
+TRELLIS_IO #(
+ .DIR("BIDIR")
+) TRELLIS_IO_18 (
+ .B(ddram_dqs_p[2]),
+ .I(ddrphy_dqs2),
+ .T((~(~ddrphy_dqs_oe_n2))),
+ .O(ddrphy_dqs_i2)
+);
+
+TRELLIS_IO #(
+ .DIR("BIDIR")
+) TRELLIS_IO_19 (
+ .B(ddram_dq[16]),
+ .I(ddrphy_dq_o16),
+ .T((~(~ddrphy_dq_oe_n16))),
+ .O(ddrphy_dq_i16)
+);
+
+TRELLIS_IO #(
+ .DIR("BIDIR")
+) TRELLIS_IO_20 (
+ .B(ddram_dq[17]),
+ .I(ddrphy_dq_o17),
+ .T((~(~ddrphy_dq_oe_n17))),
+ .O(ddrphy_dq_i17)
+);
+
+TRELLIS_IO #(
+ .DIR("BIDIR")
+) TRELLIS_IO_21 (
+ .B(ddram_dq[18]),
+ .I(ddrphy_dq_o18),
+ .T((~(~ddrphy_dq_oe_n18))),
+ .O(ddrphy_dq_i18)
+);
+
+TRELLIS_IO #(
+ .DIR("BIDIR")
+) TRELLIS_IO_22 (
+ .B(ddram_dq[19]),
+ .I(ddrphy_dq_o19),
+ .T((~(~ddrphy_dq_oe_n19))),
+ .O(ddrphy_dq_i19)
+);
+
+TRELLIS_IO #(
+ .DIR("BIDIR")
+) TRELLIS_IO_23 (
+ .B(ddram_dq[20]),
+ .I(ddrphy_dq_o20),
+ .T((~(~ddrphy_dq_oe_n20))),
+ .O(ddrphy_dq_i20)
+);
+
+TRELLIS_IO #(
+ .DIR("BIDIR")
+) TRELLIS_IO_24 (
+ .B(ddram_dq[21]),
+ .I(ddrphy_dq_o21),
+ .T((~(~ddrphy_dq_oe_n21))),
+ .O(ddrphy_dq_i21)
+);
+
+TRELLIS_IO #(
+ .DIR("BIDIR")
+) TRELLIS_IO_25 (
+ .B(ddram_dq[22]),
+ .I(ddrphy_dq_o22),
+ .T((~(~ddrphy_dq_oe_n22))),
+ .O(ddrphy_dq_i22)
+);
+
+TRELLIS_IO #(
+ .DIR("BIDIR")
+) TRELLIS_IO_26 (
+ .B(ddram_dq[23]),
+ .I(ddrphy_dq_o23),
+ .T((~(~ddrphy_dq_oe_n23))),
+ .O(ddrphy_dq_i23)
+);
+
+TRELLIS_IO #(
+ .DIR("BIDIR")
+) TRELLIS_IO_27 (
+ .B(ddram_dqs_p[3]),
+ .I(ddrphy_dqs3),
+ .T((~(~ddrphy_dqs_oe_n3))),
+ .O(ddrphy_dqs_i3)
+);
+
+TRELLIS_IO #(
+ .DIR("BIDIR")
+) TRELLIS_IO_28 (
+ .B(ddram_dq[24]),
+ .I(ddrphy_dq_o24),
+ .T((~(~ddrphy_dq_oe_n24))),
+ .O(ddrphy_dq_i24)
+);
+
+TRELLIS_IO #(
+ .DIR("BIDIR")
+) TRELLIS_IO_29 (
+ .B(ddram_dq[25]),
+ .I(ddrphy_dq_o25),
+ .T((~(~ddrphy_dq_oe_n25))),
+ .O(ddrphy_dq_i25)
+);
+
+TRELLIS_IO #(
+ .DIR("BIDIR")
+) TRELLIS_IO_30 (
+ .B(ddram_dq[26]),
+ .I(ddrphy_dq_o26),
+ .T((~(~ddrphy_dq_oe_n26))),
+ .O(ddrphy_dq_i26)
+);
+
+TRELLIS_IO #(
+ .DIR("BIDIR")
+) TRELLIS_IO_31 (
+ .B(ddram_dq[27]),
+ .I(ddrphy_dq_o27),
+ .T((~(~ddrphy_dq_oe_n27))),
+ .O(ddrphy_dq_i27)
+);
+
+TRELLIS_IO #(
+ .DIR("BIDIR")
+) TRELLIS_IO_32 (
+ .B(ddram_dq[28]),
+ .I(ddrphy_dq_o28),
+ .T((~(~ddrphy_dq_oe_n28))),
+ .O(ddrphy_dq_i28)
+);
+
+TRELLIS_IO #(
+ .DIR("BIDIR")
+) TRELLIS_IO_33 (
+ .B(ddram_dq[29]),
+ .I(ddrphy_dq_o29),
+ .T((~(~ddrphy_dq_oe_n29))),
+ .O(ddrphy_dq_i29)
+);
+
+TRELLIS_IO #(
+ .DIR("BIDIR")
+) TRELLIS_IO_34 (
+ .B(ddram_dq[30]),
+ .I(ddrphy_dq_o30),
+ .T((~(~ddrphy_dq_oe_n30))),
+ .O(ddrphy_dq_i30)
+);
+
+TRELLIS_IO #(
+ .DIR("BIDIR")
+) TRELLIS_IO_35 (
+ .B(ddram_dq[31]),
+ .I(ddrphy_dq_o31),
+ .T((~(~ddrphy_dq_oe_n31))),
+ .O(ddrphy_dq_i31)
+);
+
+endmodule
+
+// -----------------------------------------------------------------------------
+// Auto-Generated by LiteX on 2022-02-21 23:17:58.
+//------------------------------------------------------------------------------
--- /dev/null
+// -----------------------------------------------------------------------------
+// Auto-Generated by: __ _ __ _ __
+// / / (_) /____ | |/_/
+// / /__/ / __/ -_)> <
+// /____/_/\__/\__/_/|_|
+// Build your hardware, easily!
+// https://github.com/enjoy-digital/litex
+//
+// Filename : liteeth_core.v
+// Device :
+// LiteX sha1 : 1b62f142
+// Date : 2022-02-22 13:54:55
+//------------------------------------------------------------------------------
+
+
+//------------------------------------------------------------------------------
+// Module
+//------------------------------------------------------------------------------
+
+module liteeth_core (
+ input wire sys_clock,
+ input wire sys_reset,
+ output wire rgmii_eth_clocks_tx,
+ input wire rgmii_eth_clocks_rx,
+ output wire rgmii_eth_rst_n,
+ input wire rgmii_eth_int_n,
+ inout wire rgmii_eth_mdio,
+ output wire rgmii_eth_mdc,
+ input wire rgmii_eth_rx_ctl,
+ input wire [3:0] rgmii_eth_rx_data,
+ output wire rgmii_eth_tx_ctl,
+ output wire [3:0] rgmii_eth_tx_data,
+ input wire [29:0] wishbone_adr,
+ input wire [31:0] wishbone_dat_w,
+ output wire [31:0] wishbone_dat_r,
+ input wire [3:0] wishbone_sel,
+ input wire wishbone_cyc,
+ input wire wishbone_stb,
+ output wire wishbone_ack,
+ input wire wishbone_we,
+ input wire [2:0] wishbone_cti,
+ input wire [1:0] wishbone_bte,
+ output wire wishbone_err,
+ output wire interrupt
+);
+
+
+//------------------------------------------------------------------------------
+// Signals
+//------------------------------------------------------------------------------
+
+reg main_maccore_maccore_soc_rst = 1'd0;
+wire main_maccore_maccore_cpu_rst;
+reg [1:0] main_maccore_maccore_reset_storage = 2'd0;
+reg main_maccore_maccore_reset_re = 1'd0;
+reg [31:0] main_maccore_maccore_scratch_storage = 32'd305419896;
+reg main_maccore_maccore_scratch_re = 1'd0;
+wire [31:0] main_maccore_maccore_bus_errors_status;
+wire main_maccore_maccore_bus_errors_we;
+reg main_maccore_maccore_bus_errors_re = 1'd0;
+wire main_maccore_maccore_bus_error;
+reg [31:0] main_maccore_maccore_bus_errors = 32'd0;
+wire sys_clk;
+wire sys_rst;
+wire por_clk;
+reg main_maccore_int_rst = 1'd1;
+reg main_maccore_ethphy_reset_storage = 1'd0;
+reg main_maccore_ethphy_reset_re = 1'd0;
+wire eth_rx_clk;
+wire eth_rx_rst;
+wire eth_tx_clk;
+wire eth_tx_rst;
+wire main_maccore_ethphy_eth_tx_clk_o;
+wire main_maccore_ethphy_reset;
+wire main_maccore_ethphy_sink_valid;
+wire main_maccore_ethphy_sink_ready;
+wire main_maccore_ethphy_sink_first;
+wire main_maccore_ethphy_sink_last;
+wire [7:0] main_maccore_ethphy_sink_payload_data;
+wire main_maccore_ethphy_sink_payload_last_be;
+wire main_maccore_ethphy_sink_payload_error;
+wire main_maccore_ethphy_tx_ctl_oddrx1f;
+wire [3:0] main_maccore_ethphy_tx_data_oddrx1f;
+reg main_maccore_ethphy_source_valid = 1'd0;
+wire main_maccore_ethphy_source_ready;
+reg main_maccore_ethphy_source_first = 1'd0;
+wire main_maccore_ethphy_source_last;
+reg [7:0] main_maccore_ethphy_source_payload_data = 8'd0;
+reg main_maccore_ethphy_source_payload_last_be = 1'd0;
+reg main_maccore_ethphy_source_payload_error = 1'd0;
+reg main_maccore_ethphy_link_status = 1'd0;
+reg main_maccore_ethphy_clock_speed = 1'd0;
+reg main_maccore_ethphy_duplex_status = 1'd0;
+reg [2:0] main_maccore_ethphy_status = 3'd0;
+wire main_maccore_ethphy_we;
+reg main_maccore_ethphy_re = 1'd0;
+wire main_maccore_ethphy_rx_ctl_delayf;
+wire [1:0] main_maccore_ethphy_rx_ctl;
+reg [1:0] main_maccore_ethphy_rx_ctl_reg = 2'd0;
+wire [3:0] main_maccore_ethphy_rx_data_delayf;
+wire [7:0] main_maccore_ethphy_rx_data;
+reg [7:0] main_maccore_ethphy_rx_data_reg = 8'd0;
+reg [1:0] main_maccore_ethphy_rx_ctl_reg_d = 2'd0;
+wire main_maccore_ethphy_last;
+wire main_maccore_ethphy_mdc;
+wire main_maccore_ethphy_oe;
+wire main_maccore_ethphy_w;
+reg [2:0] main_maccore_ethphy__w_storage = 3'd0;
+reg main_maccore_ethphy__w_re = 1'd0;
+reg main_maccore_ethphy_r = 1'd0;
+reg main_maccore_ethphy__r_status = 1'd0;
+wire main_maccore_ethphy__r_we;
+reg main_maccore_ethphy__r_re = 1'd0;
+wire main_maccore_ethphy_data_w;
+wire main_maccore_ethphy_data_oe;
+wire main_maccore_ethphy_data_r;
+wire main_tx_gap_inserter_sink_valid;
+reg main_tx_gap_inserter_sink_ready = 1'd0;
+wire main_tx_gap_inserter_sink_first;
+wire main_tx_gap_inserter_sink_last;
+wire [7:0] main_tx_gap_inserter_sink_payload_data;
+wire main_tx_gap_inserter_sink_payload_last_be;
+wire main_tx_gap_inserter_sink_payload_error;
+reg main_tx_gap_inserter_source_valid = 1'd0;
+wire main_tx_gap_inserter_source_ready;
+reg main_tx_gap_inserter_source_first = 1'd0;
+reg main_tx_gap_inserter_source_last = 1'd0;
+reg [7:0] main_tx_gap_inserter_source_payload_data = 8'd0;
+reg main_tx_gap_inserter_source_payload_last_be = 1'd0;
+reg main_tx_gap_inserter_source_payload_error = 1'd0;
+reg [3:0] main_tx_gap_inserter_counter = 4'd0;
+reg main_preamble_crc_status = 1'd1;
+wire main_preamble_crc_we;
+reg main_preamble_crc_re = 1'd0;
+reg [31:0] main_preamble_errors_status = 32'd0;
+wire main_preamble_errors_we;
+reg main_preamble_errors_re = 1'd0;
+reg [31:0] main_crc_errors_status = 32'd0;
+wire main_crc_errors_we;
+reg main_crc_errors_re = 1'd0;
+wire main_preamble_inserter_sink_valid;
+reg main_preamble_inserter_sink_ready = 1'd0;
+wire main_preamble_inserter_sink_first;
+wire main_preamble_inserter_sink_last;
+wire [7:0] main_preamble_inserter_sink_payload_data;
+wire main_preamble_inserter_sink_payload_last_be;
+wire main_preamble_inserter_sink_payload_error;
+reg main_preamble_inserter_source_valid = 1'd0;
+wire main_preamble_inserter_source_ready;
+reg main_preamble_inserter_source_first = 1'd0;
+reg main_preamble_inserter_source_last = 1'd0;
+reg [7:0] main_preamble_inserter_source_payload_data = 8'd0;
+wire main_preamble_inserter_source_payload_last_be;
+reg main_preamble_inserter_source_payload_error = 1'd0;
+reg [63:0] main_preamble_inserter_preamble = 64'd15372286728091293013;
+reg [2:0] main_preamble_inserter_count = 3'd0;
+wire main_preamble_checker_sink_valid;
+reg main_preamble_checker_sink_ready = 1'd0;
+wire main_preamble_checker_sink_first;
+wire main_preamble_checker_sink_last;
+wire [7:0] main_preamble_checker_sink_payload_data;
+wire main_preamble_checker_sink_payload_last_be;
+wire main_preamble_checker_sink_payload_error;
+reg main_preamble_checker_source_valid = 1'd0;
+wire main_preamble_checker_source_ready;
+reg main_preamble_checker_source_first = 1'd0;
+reg main_preamble_checker_source_last = 1'd0;
+wire [7:0] main_preamble_checker_source_payload_data;
+wire main_preamble_checker_source_payload_last_be;
+reg main_preamble_checker_source_payload_error = 1'd0;
+reg main_preamble_checker_error = 1'd0;
+wire main_liteethmaccrc32inserter_sink_valid;
+reg main_liteethmaccrc32inserter_sink_ready = 1'd0;
+wire main_liteethmaccrc32inserter_sink_first;
+wire main_liteethmaccrc32inserter_sink_last;
+wire [7:0] main_liteethmaccrc32inserter_sink_payload_data;
+wire main_liteethmaccrc32inserter_sink_payload_last_be;
+wire main_liteethmaccrc32inserter_sink_payload_error;
+reg main_liteethmaccrc32inserter_source_valid = 1'd0;
+wire main_liteethmaccrc32inserter_source_ready;
+reg main_liteethmaccrc32inserter_source_first = 1'd0;
+reg main_liteethmaccrc32inserter_source_last = 1'd0;
+reg [7:0] main_liteethmaccrc32inserter_source_payload_data = 8'd0;
+reg main_liteethmaccrc32inserter_source_payload_last_be = 1'd0;
+reg main_liteethmaccrc32inserter_source_payload_error = 1'd0;
+reg [7:0] main_liteethmaccrc32inserter_data0 = 8'd0;
+wire [31:0] main_liteethmaccrc32inserter_value;
+wire main_liteethmaccrc32inserter_error;
+wire [7:0] main_liteethmaccrc32inserter_data1;
+wire [31:0] main_liteethmaccrc32inserter_last;
+reg [31:0] main_liteethmaccrc32inserter_next = 32'd0;
+reg [31:0] main_liteethmaccrc32inserter_reg = 32'd4294967295;
+reg main_liteethmaccrc32inserter_ce = 1'd0;
+reg main_liteethmaccrc32inserter_reset = 1'd0;
+reg [1:0] main_liteethmaccrc32inserter_cnt = 2'd3;
+wire main_liteethmaccrc32inserter_cnt_done;
+reg main_liteethmaccrc32inserter_is_ongoing0 = 1'd0;
+reg main_liteethmaccrc32inserter_is_ongoing1 = 1'd0;
+wire main_crc32_inserter_sink_valid;
+wire main_crc32_inserter_sink_ready;
+wire main_crc32_inserter_sink_first;
+wire main_crc32_inserter_sink_last;
+wire [7:0] main_crc32_inserter_sink_payload_data;
+wire main_crc32_inserter_sink_payload_last_be;
+wire main_crc32_inserter_sink_payload_error;
+reg main_crc32_inserter_source_valid = 1'd0;
+wire main_crc32_inserter_source_ready;
+reg main_crc32_inserter_source_first = 1'd0;
+reg main_crc32_inserter_source_last = 1'd0;
+reg [7:0] main_crc32_inserter_source_payload_data = 8'd0;
+reg main_crc32_inserter_source_payload_last_be = 1'd0;
+reg main_crc32_inserter_source_payload_error = 1'd0;
+wire main_liteethmaccrc32checker_sink_sink_valid;
+reg main_liteethmaccrc32checker_sink_sink_ready = 1'd0;
+wire main_liteethmaccrc32checker_sink_sink_first;
+wire main_liteethmaccrc32checker_sink_sink_last;
+wire [7:0] main_liteethmaccrc32checker_sink_sink_payload_data;
+wire main_liteethmaccrc32checker_sink_sink_payload_last_be;
+wire main_liteethmaccrc32checker_sink_sink_payload_error;
+wire main_liteethmaccrc32checker_source_source_valid;
+wire main_liteethmaccrc32checker_source_source_ready;
+reg main_liteethmaccrc32checker_source_source_first = 1'd0;
+wire main_liteethmaccrc32checker_source_source_last;
+wire [7:0] main_liteethmaccrc32checker_source_source_payload_data;
+wire main_liteethmaccrc32checker_source_source_payload_last_be;
+reg main_liteethmaccrc32checker_source_source_payload_error = 1'd0;
+wire main_liteethmaccrc32checker_error;
+wire [7:0] main_liteethmaccrc32checker_crc_data0;
+wire [31:0] main_liteethmaccrc32checker_crc_value;
+wire main_liteethmaccrc32checker_crc_error;
+wire [7:0] main_liteethmaccrc32checker_crc_data1;
+wire [31:0] main_liteethmaccrc32checker_crc_last;
+reg [31:0] main_liteethmaccrc32checker_crc_next = 32'd0;
+reg [31:0] main_liteethmaccrc32checker_crc_reg = 32'd4294967295;
+reg main_liteethmaccrc32checker_crc_ce = 1'd0;
+reg main_liteethmaccrc32checker_crc_reset = 1'd0;
+reg main_liteethmaccrc32checker_syncfifo_sink_valid = 1'd0;
+wire main_liteethmaccrc32checker_syncfifo_sink_ready;
+wire main_liteethmaccrc32checker_syncfifo_sink_first;
+wire main_liteethmaccrc32checker_syncfifo_sink_last;
+wire [7:0] main_liteethmaccrc32checker_syncfifo_sink_payload_data;
+wire main_liteethmaccrc32checker_syncfifo_sink_payload_last_be;
+wire main_liteethmaccrc32checker_syncfifo_sink_payload_error;
+wire main_liteethmaccrc32checker_syncfifo_source_valid;
+wire main_liteethmaccrc32checker_syncfifo_source_ready;
+wire main_liteethmaccrc32checker_syncfifo_source_first;
+wire main_liteethmaccrc32checker_syncfifo_source_last;
+wire [7:0] main_liteethmaccrc32checker_syncfifo_source_payload_data;
+wire main_liteethmaccrc32checker_syncfifo_source_payload_last_be;
+wire main_liteethmaccrc32checker_syncfifo_source_payload_error;
+wire main_liteethmaccrc32checker_syncfifo_syncfifo_we;
+wire main_liteethmaccrc32checker_syncfifo_syncfifo_writable;
+wire main_liteethmaccrc32checker_syncfifo_syncfifo_re;
+wire main_liteethmaccrc32checker_syncfifo_syncfifo_readable;
+wire [11:0] main_liteethmaccrc32checker_syncfifo_syncfifo_din;
+wire [11:0] main_liteethmaccrc32checker_syncfifo_syncfifo_dout;
+reg [2:0] main_liteethmaccrc32checker_syncfifo_level = 3'd0;
+reg main_liteethmaccrc32checker_syncfifo_replace = 1'd0;
+reg [2:0] main_liteethmaccrc32checker_syncfifo_produce = 3'd0;
+reg [2:0] main_liteethmaccrc32checker_syncfifo_consume = 3'd0;
+reg [2:0] main_liteethmaccrc32checker_syncfifo_wrport_adr = 3'd0;
+wire [11:0] main_liteethmaccrc32checker_syncfifo_wrport_dat_r;
+wire main_liteethmaccrc32checker_syncfifo_wrport_we;
+wire [11:0] main_liteethmaccrc32checker_syncfifo_wrport_dat_w;
+wire main_liteethmaccrc32checker_syncfifo_do_read;
+wire [2:0] main_liteethmaccrc32checker_syncfifo_rdport_adr;
+wire [11:0] main_liteethmaccrc32checker_syncfifo_rdport_dat_r;
+wire [7:0] main_liteethmaccrc32checker_syncfifo_fifo_in_payload_data;
+wire main_liteethmaccrc32checker_syncfifo_fifo_in_payload_last_be;
+wire main_liteethmaccrc32checker_syncfifo_fifo_in_payload_error;
+wire main_liteethmaccrc32checker_syncfifo_fifo_in_first;
+wire main_liteethmaccrc32checker_syncfifo_fifo_in_last;
+wire [7:0] main_liteethmaccrc32checker_syncfifo_fifo_out_payload_data;
+wire main_liteethmaccrc32checker_syncfifo_fifo_out_payload_last_be;
+wire main_liteethmaccrc32checker_syncfifo_fifo_out_payload_error;
+wire main_liteethmaccrc32checker_syncfifo_fifo_out_first;
+wire main_liteethmaccrc32checker_syncfifo_fifo_out_last;
+reg main_liteethmaccrc32checker_fifo_reset = 1'd0;
+wire main_liteethmaccrc32checker_fifo_in;
+wire main_liteethmaccrc32checker_fifo_out;
+wire main_liteethmaccrc32checker_fifo_full;
+wire main_crc32_checker_sink_valid;
+wire main_crc32_checker_sink_ready;
+wire main_crc32_checker_sink_first;
+wire main_crc32_checker_sink_last;
+wire [7:0] main_crc32_checker_sink_payload_data;
+wire main_crc32_checker_sink_payload_last_be;
+wire main_crc32_checker_sink_payload_error;
+reg main_crc32_checker_source_valid = 1'd0;
+wire main_crc32_checker_source_ready;
+reg main_crc32_checker_source_first = 1'd0;
+reg main_crc32_checker_source_last = 1'd0;
+reg [7:0] main_crc32_checker_source_payload_data = 8'd0;
+reg main_crc32_checker_source_payload_last_be = 1'd0;
+reg main_crc32_checker_source_payload_error = 1'd0;
+wire main_ps_preamble_error_i;
+wire main_ps_preamble_error_o;
+reg main_ps_preamble_error_toggle_i = 1'd0;
+wire main_ps_preamble_error_toggle_o;
+reg main_ps_preamble_error_toggle_o_r = 1'd0;
+wire main_ps_crc_error_i;
+wire main_ps_crc_error_o;
+reg main_ps_crc_error_toggle_i = 1'd0;
+wire main_ps_crc_error_toggle_o;
+reg main_ps_crc_error_toggle_o_r = 1'd0;
+wire main_padding_inserter_sink_valid;
+reg main_padding_inserter_sink_ready = 1'd0;
+wire main_padding_inserter_sink_first;
+wire main_padding_inserter_sink_last;
+wire [7:0] main_padding_inserter_sink_payload_data;
+wire main_padding_inserter_sink_payload_last_be;
+wire main_padding_inserter_sink_payload_error;
+reg main_padding_inserter_source_valid = 1'd0;
+wire main_padding_inserter_source_ready;
+reg main_padding_inserter_source_first = 1'd0;
+reg main_padding_inserter_source_last = 1'd0;
+reg [7:0] main_padding_inserter_source_payload_data = 8'd0;
+reg main_padding_inserter_source_payload_last_be = 1'd0;
+reg main_padding_inserter_source_payload_error = 1'd0;
+reg [15:0] main_padding_inserter_counter = 16'd0;
+wire main_padding_inserter_counter_done;
+wire main_padding_checker_sink_valid;
+wire main_padding_checker_sink_ready;
+wire main_padding_checker_sink_first;
+wire main_padding_checker_sink_last;
+wire [7:0] main_padding_checker_sink_payload_data;
+wire main_padding_checker_sink_payload_last_be;
+wire main_padding_checker_sink_payload_error;
+wire main_padding_checker_source_valid;
+wire main_padding_checker_source_ready;
+wire main_padding_checker_source_first;
+wire main_padding_checker_source_last;
+wire [7:0] main_padding_checker_source_payload_data;
+wire main_padding_checker_source_payload_last_be;
+wire main_padding_checker_source_payload_error;
+wire main_tx_last_be_sink_valid;
+reg main_tx_last_be_sink_ready = 1'd0;
+wire main_tx_last_be_sink_first;
+wire main_tx_last_be_sink_last;
+wire [7:0] main_tx_last_be_sink_payload_data;
+wire main_tx_last_be_sink_payload_last_be;
+wire main_tx_last_be_sink_payload_error;
+reg main_tx_last_be_source_valid = 1'd0;
+wire main_tx_last_be_source_ready;
+reg main_tx_last_be_source_first = 1'd0;
+reg main_tx_last_be_source_last = 1'd0;
+reg [7:0] main_tx_last_be_source_payload_data = 8'd0;
+reg main_tx_last_be_source_payload_last_be = 1'd0;
+reg main_tx_last_be_source_payload_error = 1'd0;
+wire main_rx_last_be_sink_valid;
+wire main_rx_last_be_sink_ready;
+wire main_rx_last_be_sink_first;
+wire main_rx_last_be_sink_last;
+wire [7:0] main_rx_last_be_sink_payload_data;
+wire main_rx_last_be_sink_payload_last_be;
+wire main_rx_last_be_sink_payload_error;
+wire main_rx_last_be_source_valid;
+wire main_rx_last_be_source_ready;
+wire main_rx_last_be_source_first;
+wire main_rx_last_be_source_last;
+wire [7:0] main_rx_last_be_source_payload_data;
+reg main_rx_last_be_source_payload_last_be = 1'd0;
+wire main_rx_last_be_source_payload_error;
+wire main_tx_converter_sink_valid;
+wire main_tx_converter_sink_ready;
+wire main_tx_converter_sink_first;
+wire main_tx_converter_sink_last;
+wire [31:0] main_tx_converter_sink_payload_data;
+wire [3:0] main_tx_converter_sink_payload_last_be;
+wire [3:0] main_tx_converter_sink_payload_error;
+wire main_tx_converter_source_valid;
+wire main_tx_converter_source_ready;
+wire main_tx_converter_source_first;
+wire main_tx_converter_source_last;
+wire [7:0] main_tx_converter_source_payload_data;
+wire main_tx_converter_source_payload_last_be;
+wire main_tx_converter_source_payload_error;
+wire main_tx_converter_converter_sink_valid;
+wire main_tx_converter_converter_sink_ready;
+wire main_tx_converter_converter_sink_first;
+wire main_tx_converter_converter_sink_last;
+reg [39:0] main_tx_converter_converter_sink_payload_data = 40'd0;
+wire main_tx_converter_converter_source_valid;
+wire main_tx_converter_converter_source_ready;
+wire main_tx_converter_converter_source_first;
+wire main_tx_converter_converter_source_last;
+reg [9:0] main_tx_converter_converter_source_payload_data = 10'd0;
+wire main_tx_converter_converter_source_payload_valid_token_count;
+reg [1:0] main_tx_converter_converter_mux = 2'd0;
+wire main_tx_converter_converter_first;
+wire main_tx_converter_converter_last;
+wire main_tx_converter_source_source_valid;
+wire main_tx_converter_source_source_ready;
+wire main_tx_converter_source_source_first;
+wire main_tx_converter_source_source_last;
+wire [9:0] main_tx_converter_source_source_payload_data;
+wire main_rx_converter_sink_valid;
+wire main_rx_converter_sink_ready;
+wire main_rx_converter_sink_first;
+wire main_rx_converter_sink_last;
+wire [7:0] main_rx_converter_sink_payload_data;
+wire main_rx_converter_sink_payload_last_be;
+wire main_rx_converter_sink_payload_error;
+wire main_rx_converter_source_valid;
+wire main_rx_converter_source_ready;
+wire main_rx_converter_source_first;
+wire main_rx_converter_source_last;
+reg [31:0] main_rx_converter_source_payload_data = 32'd0;
+reg [3:0] main_rx_converter_source_payload_last_be = 4'd0;
+reg [3:0] main_rx_converter_source_payload_error = 4'd0;
+wire main_rx_converter_converter_sink_valid;
+wire main_rx_converter_converter_sink_ready;
+wire main_rx_converter_converter_sink_first;
+wire main_rx_converter_converter_sink_last;
+wire [9:0] main_rx_converter_converter_sink_payload_data;
+wire main_rx_converter_converter_source_valid;
+wire main_rx_converter_converter_source_ready;
+reg main_rx_converter_converter_source_first = 1'd0;
+reg main_rx_converter_converter_source_last = 1'd0;
+reg [39:0] main_rx_converter_converter_source_payload_data = 40'd0;
+reg [2:0] main_rx_converter_converter_source_payload_valid_token_count = 3'd0;
+reg [1:0] main_rx_converter_converter_demux = 2'd0;
+wire main_rx_converter_converter_load_part;
+reg main_rx_converter_converter_strobe_all = 1'd0;
+wire main_rx_converter_source_source_valid;
+wire main_rx_converter_source_source_ready;
+wire main_rx_converter_source_source_first;
+wire main_rx_converter_source_source_last;
+wire [39:0] main_rx_converter_source_source_payload_data;
+wire main_tx_cdc_sink_sink_valid;
+wire main_tx_cdc_sink_sink_ready;
+wire main_tx_cdc_sink_sink_first;
+wire main_tx_cdc_sink_sink_last;
+wire [31:0] main_tx_cdc_sink_sink_payload_data;
+wire [3:0] main_tx_cdc_sink_sink_payload_last_be;
+wire [3:0] main_tx_cdc_sink_sink_payload_error;
+wire main_tx_cdc_source_source_valid;
+wire main_tx_cdc_source_source_ready;
+wire main_tx_cdc_source_source_first;
+wire main_tx_cdc_source_source_last;
+wire [31:0] main_tx_cdc_source_source_payload_data;
+wire [3:0] main_tx_cdc_source_source_payload_last_be;
+wire [3:0] main_tx_cdc_source_source_payload_error;
+wire main_tx_cdc_cdc_sink_valid;
+wire main_tx_cdc_cdc_sink_ready;
+wire main_tx_cdc_cdc_sink_first;
+wire main_tx_cdc_cdc_sink_last;
+wire [31:0] main_tx_cdc_cdc_sink_payload_data;
+wire [3:0] main_tx_cdc_cdc_sink_payload_last_be;
+wire [3:0] main_tx_cdc_cdc_sink_payload_error;
+wire main_tx_cdc_cdc_source_valid;
+wire main_tx_cdc_cdc_source_ready;
+wire main_tx_cdc_cdc_source_first;
+wire main_tx_cdc_cdc_source_last;
+wire [31:0] main_tx_cdc_cdc_source_payload_data;
+wire [3:0] main_tx_cdc_cdc_source_payload_last_be;
+wire [3:0] main_tx_cdc_cdc_source_payload_error;
+wire main_tx_cdc_cdc_asyncfifo_we;
+wire main_tx_cdc_cdc_asyncfifo_writable;
+wire main_tx_cdc_cdc_asyncfifo_re;
+wire main_tx_cdc_cdc_asyncfifo_readable;
+wire [41:0] main_tx_cdc_cdc_asyncfifo_din;
+wire [41:0] main_tx_cdc_cdc_asyncfifo_dout;
+wire main_tx_cdc_cdc_graycounter0_ce;
+(* syn_no_retiming = "true" *) reg [5:0] main_tx_cdc_cdc_graycounter0_q = 6'd0;
+wire [5:0] main_tx_cdc_cdc_graycounter0_q_next;
+reg [5:0] main_tx_cdc_cdc_graycounter0_q_binary = 6'd0;
+reg [5:0] main_tx_cdc_cdc_graycounter0_q_next_binary = 6'd0;
+wire main_tx_cdc_cdc_graycounter1_ce;
+(* syn_no_retiming = "true" *) reg [5:0] main_tx_cdc_cdc_graycounter1_q = 6'd0;
+wire [5:0] main_tx_cdc_cdc_graycounter1_q_next;
+reg [5:0] main_tx_cdc_cdc_graycounter1_q_binary = 6'd0;
+reg [5:0] main_tx_cdc_cdc_graycounter1_q_next_binary = 6'd0;
+wire [5:0] main_tx_cdc_cdc_produce_rdomain;
+wire [5:0] main_tx_cdc_cdc_consume_wdomain;
+wire [4:0] main_tx_cdc_cdc_wrport_adr;
+wire [41:0] main_tx_cdc_cdc_wrport_dat_r;
+wire main_tx_cdc_cdc_wrport_we;
+wire [41:0] main_tx_cdc_cdc_wrport_dat_w;
+wire [4:0] main_tx_cdc_cdc_rdport_adr;
+wire [41:0] main_tx_cdc_cdc_rdport_dat_r;
+wire [31:0] main_tx_cdc_cdc_fifo_in_payload_data;
+wire [3:0] main_tx_cdc_cdc_fifo_in_payload_last_be;
+wire [3:0] main_tx_cdc_cdc_fifo_in_payload_error;
+wire main_tx_cdc_cdc_fifo_in_first;
+wire main_tx_cdc_cdc_fifo_in_last;
+wire [31:0] main_tx_cdc_cdc_fifo_out_payload_data;
+wire [3:0] main_tx_cdc_cdc_fifo_out_payload_last_be;
+wire [3:0] main_tx_cdc_cdc_fifo_out_payload_error;
+wire main_tx_cdc_cdc_fifo_out_first;
+wire main_tx_cdc_cdc_fifo_out_last;
+wire main_rx_cdc_sink_sink_valid;
+wire main_rx_cdc_sink_sink_ready;
+wire main_rx_cdc_sink_sink_first;
+wire main_rx_cdc_sink_sink_last;
+wire [31:0] main_rx_cdc_sink_sink_payload_data;
+wire [3:0] main_rx_cdc_sink_sink_payload_last_be;
+wire [3:0] main_rx_cdc_sink_sink_payload_error;
+wire main_rx_cdc_source_source_valid;
+wire main_rx_cdc_source_source_ready;
+wire main_rx_cdc_source_source_first;
+wire main_rx_cdc_source_source_last;
+wire [31:0] main_rx_cdc_source_source_payload_data;
+wire [3:0] main_rx_cdc_source_source_payload_last_be;
+wire [3:0] main_rx_cdc_source_source_payload_error;
+wire main_rx_cdc_cdc_sink_valid;
+wire main_rx_cdc_cdc_sink_ready;
+wire main_rx_cdc_cdc_sink_first;
+wire main_rx_cdc_cdc_sink_last;
+wire [31:0] main_rx_cdc_cdc_sink_payload_data;
+wire [3:0] main_rx_cdc_cdc_sink_payload_last_be;
+wire [3:0] main_rx_cdc_cdc_sink_payload_error;
+wire main_rx_cdc_cdc_source_valid;
+wire main_rx_cdc_cdc_source_ready;
+wire main_rx_cdc_cdc_source_first;
+wire main_rx_cdc_cdc_source_last;
+wire [31:0] main_rx_cdc_cdc_source_payload_data;
+wire [3:0] main_rx_cdc_cdc_source_payload_last_be;
+wire [3:0] main_rx_cdc_cdc_source_payload_error;
+wire main_rx_cdc_cdc_asyncfifo_we;
+wire main_rx_cdc_cdc_asyncfifo_writable;
+wire main_rx_cdc_cdc_asyncfifo_re;
+wire main_rx_cdc_cdc_asyncfifo_readable;
+wire [41:0] main_rx_cdc_cdc_asyncfifo_din;
+wire [41:0] main_rx_cdc_cdc_asyncfifo_dout;
+wire main_rx_cdc_cdc_graycounter0_ce;
+(* syn_no_retiming = "true" *) reg [5:0] main_rx_cdc_cdc_graycounter0_q = 6'd0;
+wire [5:0] main_rx_cdc_cdc_graycounter0_q_next;
+reg [5:0] main_rx_cdc_cdc_graycounter0_q_binary = 6'd0;
+reg [5:0] main_rx_cdc_cdc_graycounter0_q_next_binary = 6'd0;
+wire main_rx_cdc_cdc_graycounter1_ce;
+(* syn_no_retiming = "true" *) reg [5:0] main_rx_cdc_cdc_graycounter1_q = 6'd0;
+wire [5:0] main_rx_cdc_cdc_graycounter1_q_next;
+reg [5:0] main_rx_cdc_cdc_graycounter1_q_binary = 6'd0;
+reg [5:0] main_rx_cdc_cdc_graycounter1_q_next_binary = 6'd0;
+wire [5:0] main_rx_cdc_cdc_produce_rdomain;
+wire [5:0] main_rx_cdc_cdc_consume_wdomain;
+wire [4:0] main_rx_cdc_cdc_wrport_adr;
+wire [41:0] main_rx_cdc_cdc_wrport_dat_r;
+wire main_rx_cdc_cdc_wrport_we;
+wire [41:0] main_rx_cdc_cdc_wrport_dat_w;
+wire [4:0] main_rx_cdc_cdc_rdport_adr;
+wire [41:0] main_rx_cdc_cdc_rdport_dat_r;
+wire [31:0] main_rx_cdc_cdc_fifo_in_payload_data;
+wire [3:0] main_rx_cdc_cdc_fifo_in_payload_last_be;
+wire [3:0] main_rx_cdc_cdc_fifo_in_payload_error;
+wire main_rx_cdc_cdc_fifo_in_first;
+wire main_rx_cdc_cdc_fifo_in_last;
+wire [31:0] main_rx_cdc_cdc_fifo_out_payload_data;
+wire [3:0] main_rx_cdc_cdc_fifo_out_payload_last_be;
+wire [3:0] main_rx_cdc_cdc_fifo_out_payload_error;
+wire main_rx_cdc_cdc_fifo_out_first;
+wire main_rx_cdc_cdc_fifo_out_last;
+wire main_sink_valid;
+wire main_sink_ready;
+wire main_sink_first;
+wire main_sink_last;
+wire [31:0] main_sink_payload_data;
+wire [3:0] main_sink_payload_last_be;
+wire [3:0] main_sink_payload_error;
+wire main_source_valid;
+wire main_source_ready;
+wire main_source_first;
+wire main_source_last;
+wire [31:0] main_source_payload_data;
+wire [3:0] main_source_payload_last_be;
+wire [3:0] main_source_payload_error;
+wire [29:0] main_bus_adr;
+wire [31:0] main_bus_dat_w;
+wire [31:0] main_bus_dat_r;
+wire [3:0] main_bus_sel;
+wire main_bus_cyc;
+wire main_bus_stb;
+wire main_bus_ack;
+wire main_bus_we;
+wire [2:0] main_bus_cti;
+wire [1:0] main_bus_bte;
+wire main_bus_err;
+wire main_writer_sink_sink_valid;
+reg main_writer_sink_sink_ready = 1'd1;
+wire main_writer_sink_sink_first;
+wire main_writer_sink_sink_last;
+wire [31:0] main_writer_sink_sink_payload_data;
+wire [3:0] main_writer_sink_sink_payload_last_be;
+wire [3:0] main_writer_sink_sink_payload_error;
+wire main_writer_slot_status;
+wire main_writer_slot_we;
+reg main_writer_slot_re = 1'd0;
+wire [31:0] main_writer_length_status;
+wire main_writer_length_we;
+reg main_writer_length_re = 1'd0;
+reg [31:0] main_writer_errors_status = 32'd0;
+wire main_writer_errors_we;
+reg main_writer_errors_re = 1'd0;
+wire main_writer_irq;
+wire main_writer_available_status;
+wire main_writer_available_pending;
+wire main_writer_available_trigger;
+reg main_writer_available_clear = 1'd0;
+wire main_writer_available0;
+wire main_writer_status_status;
+wire main_writer_status_we;
+reg main_writer_status_re = 1'd0;
+wire main_writer_available1;
+wire main_writer_pending_status;
+wire main_writer_pending_we;
+reg main_writer_pending_re = 1'd0;
+reg main_writer_pending_r = 1'd0;
+wire main_writer_available2;
+reg main_writer_enable_storage = 1'd0;
+reg main_writer_enable_re = 1'd0;
+reg [2:0] main_writer_decoded = 3'd0;
+reg [31:0] main_writer_counter = 32'd0;
+reg main_writer_slot = 1'd0;
+reg main_writer_slot_ce = 1'd0;
+reg main_writer_start = 1'd0;
+reg main_writer_ongoing = 1'd0;
+reg main_writer_stat_fifo_sink_valid = 1'd0;
+wire main_writer_stat_fifo_sink_ready;
+reg main_writer_stat_fifo_sink_first = 1'd0;
+reg main_writer_stat_fifo_sink_last = 1'd0;
+wire main_writer_stat_fifo_sink_payload_slot;
+wire [31:0] main_writer_stat_fifo_sink_payload_length;
+wire main_writer_stat_fifo_source_valid;
+wire main_writer_stat_fifo_source_ready;
+wire main_writer_stat_fifo_source_first;
+wire main_writer_stat_fifo_source_last;
+wire main_writer_stat_fifo_source_payload_slot;
+wire [31:0] main_writer_stat_fifo_source_payload_length;
+wire main_writer_stat_fifo_syncfifo_we;
+wire main_writer_stat_fifo_syncfifo_writable;
+wire main_writer_stat_fifo_syncfifo_re;
+wire main_writer_stat_fifo_syncfifo_readable;
+wire [34:0] main_writer_stat_fifo_syncfifo_din;
+wire [34:0] main_writer_stat_fifo_syncfifo_dout;
+reg [1:0] main_writer_stat_fifo_level = 2'd0;
+reg main_writer_stat_fifo_replace = 1'd0;
+reg main_writer_stat_fifo_produce = 1'd0;
+reg main_writer_stat_fifo_consume = 1'd0;
+reg main_writer_stat_fifo_wrport_adr = 1'd0;
+wire [34:0] main_writer_stat_fifo_wrport_dat_r;
+wire main_writer_stat_fifo_wrport_we;
+wire [34:0] main_writer_stat_fifo_wrport_dat_w;
+wire main_writer_stat_fifo_do_read;
+wire main_writer_stat_fifo_rdport_adr;
+wire [34:0] main_writer_stat_fifo_rdport_dat_r;
+wire main_writer_stat_fifo_fifo_in_payload_slot;
+wire [31:0] main_writer_stat_fifo_fifo_in_payload_length;
+wire main_writer_stat_fifo_fifo_in_first;
+wire main_writer_stat_fifo_fifo_in_last;
+wire main_writer_stat_fifo_fifo_out_payload_slot;
+wire [31:0] main_writer_stat_fifo_fifo_out_payload_length;
+wire main_writer_stat_fifo_fifo_out_first;
+wire main_writer_stat_fifo_fifo_out_last;
+reg [8:0] main_writer_memory0_adr = 9'd0;
+wire [31:0] main_writer_memory0_dat_r;
+reg main_writer_memory0_we = 1'd0;
+reg [31:0] main_writer_memory0_dat_w = 32'd0;
+reg [8:0] main_writer_memory1_adr = 9'd0;
+wire [31:0] main_writer_memory1_dat_r;
+reg main_writer_memory1_we = 1'd0;
+reg [31:0] main_writer_memory1_dat_w = 32'd0;
+reg main_reader_source_source_valid = 1'd0;
+wire main_reader_source_source_ready;
+reg main_reader_source_source_first = 1'd0;
+reg main_reader_source_source_last = 1'd0;
+reg [31:0] main_reader_source_source_payload_data = 32'd0;
+reg [3:0] main_reader_source_source_payload_last_be = 4'd0;
+reg [3:0] main_reader_source_source_payload_error = 4'd0;
+reg main_reader_start_start_re = 1'd0;
+wire main_reader_start_start_r;
+reg main_reader_start_start_we = 1'd0;
+reg main_reader_start_start_w = 1'd0;
+wire main_reader_ready_status;
+wire main_reader_ready_we;
+reg main_reader_ready_re = 1'd0;
+wire [1:0] main_reader_level_status;
+wire main_reader_level_we;
+reg main_reader_level_re = 1'd0;
+reg main_reader_slot_storage = 1'd0;
+reg main_reader_slot_re = 1'd0;
+reg [10:0] main_reader_length_storage = 11'd0;
+reg main_reader_length_re = 1'd0;
+wire main_reader_irq;
+wire main_reader_eventsourcepulse_status;
+reg main_reader_eventsourcepulse_pending = 1'd0;
+reg main_reader_eventsourcepulse_trigger = 1'd0;
+reg main_reader_eventsourcepulse_clear = 1'd0;
+wire main_reader_event00;
+wire main_reader_status_status;
+wire main_reader_status_we;
+reg main_reader_status_re = 1'd0;
+wire main_reader_event01;
+wire main_reader_pending_status;
+wire main_reader_pending_we;
+reg main_reader_pending_re = 1'd0;
+reg main_reader_pending_r = 1'd0;
+wire main_reader_event02;
+reg main_reader_enable_storage = 1'd0;
+reg main_reader_enable_re = 1'd0;
+reg main_reader_start = 1'd0;
+wire main_reader_cmd_fifo_sink_valid;
+wire main_reader_cmd_fifo_sink_ready;
+reg main_reader_cmd_fifo_sink_first = 1'd0;
+reg main_reader_cmd_fifo_sink_last = 1'd0;
+wire main_reader_cmd_fifo_sink_payload_slot;
+wire [10:0] main_reader_cmd_fifo_sink_payload_length;
+wire main_reader_cmd_fifo_source_valid;
+reg main_reader_cmd_fifo_source_ready = 1'd0;
+wire main_reader_cmd_fifo_source_first;
+wire main_reader_cmd_fifo_source_last;
+wire main_reader_cmd_fifo_source_payload_slot;
+wire [10:0] main_reader_cmd_fifo_source_payload_length;
+wire main_reader_cmd_fifo_syncfifo_we;
+wire main_reader_cmd_fifo_syncfifo_writable;
+wire main_reader_cmd_fifo_syncfifo_re;
+wire main_reader_cmd_fifo_syncfifo_readable;
+wire [13:0] main_reader_cmd_fifo_syncfifo_din;
+wire [13:0] main_reader_cmd_fifo_syncfifo_dout;
+reg [1:0] main_reader_cmd_fifo_level = 2'd0;
+reg main_reader_cmd_fifo_replace = 1'd0;
+reg main_reader_cmd_fifo_produce = 1'd0;
+reg main_reader_cmd_fifo_consume = 1'd0;
+reg main_reader_cmd_fifo_wrport_adr = 1'd0;
+wire [13:0] main_reader_cmd_fifo_wrport_dat_r;
+wire main_reader_cmd_fifo_wrport_we;
+wire [13:0] main_reader_cmd_fifo_wrport_dat_w;
+wire main_reader_cmd_fifo_do_read;
+wire main_reader_cmd_fifo_rdport_adr;
+wire [13:0] main_reader_cmd_fifo_rdport_dat_r;
+wire main_reader_cmd_fifo_fifo_in_payload_slot;
+wire [10:0] main_reader_cmd_fifo_fifo_in_payload_length;
+wire main_reader_cmd_fifo_fifo_in_first;
+wire main_reader_cmd_fifo_fifo_in_last;
+wire main_reader_cmd_fifo_fifo_out_payload_slot;
+wire [10:0] main_reader_cmd_fifo_fifo_out_payload_length;
+wire main_reader_cmd_fifo_fifo_out_first;
+wire main_reader_cmd_fifo_fifo_out_last;
+reg [10:0] main_reader_read_address = 11'd0;
+reg [10:0] main_reader_counter = 11'd0;
+reg [3:0] main_reader_encoded = 4'd0;
+wire [8:0] main_reader_memory0_adr;
+wire [31:0] main_reader_memory0_dat_r;
+wire [8:0] main_reader_memory1_adr;
+wire [31:0] main_reader_memory1_dat_r;
+wire main_ev_irq;
+wire [29:0] main_interface0_adr;
+wire [31:0] main_interface0_dat_w;
+wire [31:0] main_interface0_dat_r;
+wire [3:0] main_interface0_sel;
+wire main_interface0_cyc;
+wire main_interface0_stb;
+reg main_interface0_ack = 1'd0;
+wire main_interface0_we;
+wire [2:0] main_interface0_cti;
+wire [1:0] main_interface0_bte;
+reg main_interface0_err = 1'd0;
+wire [8:0] main_sram0_adr0;
+wire [31:0] main_sram0_dat_r0;
+wire [29:0] main_interface0_writer_sram_converted_width_adr;
+wire [31:0] main_interface0_writer_sram_converted_width_dat_w;
+wire [31:0] main_interface0_writer_sram_converted_width_dat_r;
+wire [3:0] main_interface0_writer_sram_converted_width_sel;
+wire main_interface0_writer_sram_converted_width_cyc;
+wire main_interface0_writer_sram_converted_width_stb;
+wire main_interface0_writer_sram_converted_width_ack;
+wire main_interface0_writer_sram_converted_width_we;
+wire [2:0] main_interface0_writer_sram_converted_width_cti;
+wire [1:0] main_interface0_writer_sram_converted_width_bte;
+wire main_interface0_writer_sram_converted_width_err;
+wire [29:0] main_interface1_adr;
+wire [31:0] main_interface1_dat_w;
+wire [31:0] main_interface1_dat_r;
+wire [3:0] main_interface1_sel;
+wire main_interface1_cyc;
+wire main_interface1_stb;
+reg main_interface1_ack = 1'd0;
+wire main_interface1_we;
+wire [2:0] main_interface1_cti;
+wire [1:0] main_interface1_bte;
+reg main_interface1_err = 1'd0;
+wire [8:0] main_sram1_adr0;
+wire [31:0] main_sram1_dat_r0;
+wire [29:0] main_interface1_writer_sram_converted_width_adr;
+wire [31:0] main_interface1_writer_sram_converted_width_dat_w;
+wire [31:0] main_interface1_writer_sram_converted_width_dat_r;
+wire [3:0] main_interface1_writer_sram_converted_width_sel;
+wire main_interface1_writer_sram_converted_width_cyc;
+wire main_interface1_writer_sram_converted_width_stb;
+wire main_interface1_writer_sram_converted_width_ack;
+wire main_interface1_writer_sram_converted_width_we;
+wire [2:0] main_interface1_writer_sram_converted_width_cti;
+wire [1:0] main_interface1_writer_sram_converted_width_bte;
+wire main_interface1_writer_sram_converted_width_err;
+wire [29:0] main_interface2_adr;
+wire [31:0] main_interface2_dat_w;
+wire [31:0] main_interface2_dat_r;
+wire [3:0] main_interface2_sel;
+wire main_interface2_cyc;
+wire main_interface2_stb;
+reg main_interface2_ack = 1'd0;
+wire main_interface2_we;
+wire [2:0] main_interface2_cti;
+wire [1:0] main_interface2_bte;
+reg main_interface2_err = 1'd0;
+wire [8:0] main_sram0_adr1;
+wire [31:0] main_sram0_dat_r1;
+reg [3:0] main_sram0_we = 4'd0;
+wire [31:0] main_sram0_dat_w;
+wire [29:0] main_interface0_reader_sram_converted_width_adr;
+wire [31:0] main_interface0_reader_sram_converted_width_dat_w;
+wire [31:0] main_interface0_reader_sram_converted_width_dat_r;
+wire [3:0] main_interface0_reader_sram_converted_width_sel;
+wire main_interface0_reader_sram_converted_width_cyc;
+wire main_interface0_reader_sram_converted_width_stb;
+wire main_interface0_reader_sram_converted_width_ack;
+wire main_interface0_reader_sram_converted_width_we;
+wire [2:0] main_interface0_reader_sram_converted_width_cti;
+wire [1:0] main_interface0_reader_sram_converted_width_bte;
+wire main_interface0_reader_sram_converted_width_err;
+wire [29:0] main_interface3_adr;
+wire [31:0] main_interface3_dat_w;
+wire [31:0] main_interface3_dat_r;
+wire [3:0] main_interface3_sel;
+wire main_interface3_cyc;
+wire main_interface3_stb;
+reg main_interface3_ack = 1'd0;
+wire main_interface3_we;
+wire [2:0] main_interface3_cti;
+wire [1:0] main_interface3_bte;
+reg main_interface3_err = 1'd0;
+wire [8:0] main_sram1_adr1;
+wire [31:0] main_sram1_dat_r1;
+reg [3:0] main_sram1_we = 4'd0;
+wire [31:0] main_sram1_dat_w;
+wire [29:0] main_interface1_reader_sram_converted_width_adr;
+wire [31:0] main_interface1_reader_sram_converted_width_dat_w;
+wire [31:0] main_interface1_reader_sram_converted_width_dat_r;
+wire [3:0] main_interface1_reader_sram_converted_width_sel;
+wire main_interface1_reader_sram_converted_width_cyc;
+wire main_interface1_reader_sram_converted_width_stb;
+wire main_interface1_reader_sram_converted_width_ack;
+wire main_interface1_reader_sram_converted_width_we;
+wire [2:0] main_interface1_reader_sram_converted_width_cti;
+wire [1:0] main_interface1_reader_sram_converted_width_bte;
+wire main_interface1_reader_sram_converted_width_err;
+reg [3:0] main_slave_sel = 4'd0;
+reg [3:0] main_slave_sel_r = 4'd0;
+wire [29:0] main_wb_bus_adr;
+wire [31:0] main_wb_bus_dat_w;
+wire [31:0] main_wb_bus_dat_r;
+wire [3:0] main_wb_bus_sel;
+wire main_wb_bus_cyc;
+wire main_wb_bus_stb;
+wire main_wb_bus_ack;
+wire main_wb_bus_we;
+wire [2:0] main_wb_bus_cti;
+wire [1:0] main_wb_bus_bte;
+wire main_wb_bus_err;
+reg builder_liteethmacgap_state = 1'd0;
+reg builder_liteethmacgap_next_state = 1'd0;
+reg [3:0] main_tx_gap_inserter_counter_liteethmacgap_next_value = 4'd0;
+reg main_tx_gap_inserter_counter_liteethmacgap_next_value_ce = 1'd0;
+reg [1:0] builder_liteethmacpreambleinserter_state = 2'd0;
+reg [1:0] builder_liteethmacpreambleinserter_next_state = 2'd0;
+reg [2:0] main_preamble_inserter_count_liteethmacpreambleinserter_next_value = 3'd0;
+reg main_preamble_inserter_count_liteethmacpreambleinserter_next_value_ce = 1'd0;
+reg builder_liteethmacpreamblechecker_state = 1'd0;
+reg builder_liteethmacpreamblechecker_next_state = 1'd0;
+reg [1:0] builder_liteethmaccrc32inserter_state = 2'd0;
+reg [1:0] builder_liteethmaccrc32inserter_next_state = 2'd0;
+reg [1:0] builder_liteethmaccrc32checker_state = 2'd0;
+reg [1:0] builder_liteethmaccrc32checker_next_state = 2'd0;
+reg builder_liteethmacpaddinginserter_state = 1'd0;
+reg builder_liteethmacpaddinginserter_next_state = 1'd0;
+reg [15:0] main_padding_inserter_counter_liteethmacpaddinginserter_next_value = 16'd0;
+reg main_padding_inserter_counter_liteethmacpaddinginserter_next_value_ce = 1'd0;
+reg builder_liteethmactxlastbe_state = 1'd0;
+reg builder_liteethmactxlastbe_next_state = 1'd0;
+reg [2:0] builder_liteethmacsramwriter_state = 3'd0;
+reg [2:0] builder_liteethmacsramwriter_next_state = 3'd0;
+reg [31:0] main_writer_counter_t_next_value = 32'd0;
+reg main_writer_counter_t_next_value_ce = 1'd0;
+reg [31:0] main_writer_errors_status_f_next_value = 32'd0;
+reg main_writer_errors_status_f_next_value_ce = 1'd0;
+reg [1:0] builder_liteethmacsramreader_state = 2'd0;
+reg [1:0] builder_liteethmacsramreader_next_state = 2'd0;
+reg [10:0] main_reader_counter_next_value = 11'd0;
+reg main_reader_counter_next_value_ce = 1'd0;
+reg [13:0] builder_maccore_adr = 14'd0;
+reg builder_maccore_we = 1'd0;
+reg [31:0] builder_maccore_dat_w = 32'd0;
+wire [31:0] builder_maccore_dat_r;
+wire [29:0] builder_maccore_wishbone_adr;
+wire [31:0] builder_maccore_wishbone_dat_w;
+reg [31:0] builder_maccore_wishbone_dat_r = 32'd0;
+wire [3:0] builder_maccore_wishbone_sel;
+wire builder_maccore_wishbone_cyc;
+wire builder_maccore_wishbone_stb;
+reg builder_maccore_wishbone_ack = 1'd0;
+wire builder_maccore_wishbone_we;
+wire [2:0] builder_maccore_wishbone_cti;
+wire [1:0] builder_maccore_wishbone_bte;
+reg builder_maccore_wishbone_err = 1'd0;
+wire [29:0] builder_shared_adr;
+wire [31:0] builder_shared_dat_w;
+reg [31:0] builder_shared_dat_r = 32'd0;
+wire [3:0] builder_shared_sel;
+wire builder_shared_cyc;
+wire builder_shared_stb;
+reg builder_shared_ack = 1'd0;
+wire builder_shared_we;
+wire [2:0] builder_shared_cti;
+wire [1:0] builder_shared_bte;
+wire builder_shared_err;
+wire builder_request;
+wire builder_grant;
+reg [1:0] builder_slave_sel = 2'd0;
+reg [1:0] builder_slave_sel_r = 2'd0;
+reg builder_error = 1'd0;
+wire builder_wait;
+wire builder_done;
+reg [19:0] builder_count = 20'd1000000;
+wire [13:0] builder_interface0_bank_bus_adr;
+wire builder_interface0_bank_bus_we;
+wire [31:0] builder_interface0_bank_bus_dat_w;
+reg [31:0] builder_interface0_bank_bus_dat_r = 32'd0;
+reg builder_csrbank0_reset0_re = 1'd0;
+wire [1:0] builder_csrbank0_reset0_r;
+reg builder_csrbank0_reset0_we = 1'd0;
+wire [1:0] builder_csrbank0_reset0_w;
+reg builder_csrbank0_scratch0_re = 1'd0;
+wire [31:0] builder_csrbank0_scratch0_r;
+reg builder_csrbank0_scratch0_we = 1'd0;
+wire [31:0] builder_csrbank0_scratch0_w;
+reg builder_csrbank0_bus_errors_re = 1'd0;
+wire [31:0] builder_csrbank0_bus_errors_r;
+reg builder_csrbank0_bus_errors_we = 1'd0;
+wire [31:0] builder_csrbank0_bus_errors_w;
+wire builder_csrbank0_sel;
+wire [13:0] builder_interface1_bank_bus_adr;
+wire builder_interface1_bank_bus_we;
+wire [31:0] builder_interface1_bank_bus_dat_w;
+reg [31:0] builder_interface1_bank_bus_dat_r = 32'd0;
+reg builder_csrbank1_sram_writer_slot_re = 1'd0;
+wire builder_csrbank1_sram_writer_slot_r;
+reg builder_csrbank1_sram_writer_slot_we = 1'd0;
+wire builder_csrbank1_sram_writer_slot_w;
+reg builder_csrbank1_sram_writer_length_re = 1'd0;
+wire [31:0] builder_csrbank1_sram_writer_length_r;
+reg builder_csrbank1_sram_writer_length_we = 1'd0;
+wire [31:0] builder_csrbank1_sram_writer_length_w;
+reg builder_csrbank1_sram_writer_errors_re = 1'd0;
+wire [31:0] builder_csrbank1_sram_writer_errors_r;
+reg builder_csrbank1_sram_writer_errors_we = 1'd0;
+wire [31:0] builder_csrbank1_sram_writer_errors_w;
+reg builder_csrbank1_sram_writer_ev_status_re = 1'd0;
+wire builder_csrbank1_sram_writer_ev_status_r;
+reg builder_csrbank1_sram_writer_ev_status_we = 1'd0;
+wire builder_csrbank1_sram_writer_ev_status_w;
+reg builder_csrbank1_sram_writer_ev_pending_re = 1'd0;
+wire builder_csrbank1_sram_writer_ev_pending_r;
+reg builder_csrbank1_sram_writer_ev_pending_we = 1'd0;
+wire builder_csrbank1_sram_writer_ev_pending_w;
+reg builder_csrbank1_sram_writer_ev_enable0_re = 1'd0;
+wire builder_csrbank1_sram_writer_ev_enable0_r;
+reg builder_csrbank1_sram_writer_ev_enable0_we = 1'd0;
+wire builder_csrbank1_sram_writer_ev_enable0_w;
+reg builder_csrbank1_sram_reader_ready_re = 1'd0;
+wire builder_csrbank1_sram_reader_ready_r;
+reg builder_csrbank1_sram_reader_ready_we = 1'd0;
+wire builder_csrbank1_sram_reader_ready_w;
+reg builder_csrbank1_sram_reader_level_re = 1'd0;
+wire [1:0] builder_csrbank1_sram_reader_level_r;
+reg builder_csrbank1_sram_reader_level_we = 1'd0;
+wire [1:0] builder_csrbank1_sram_reader_level_w;
+reg builder_csrbank1_sram_reader_slot0_re = 1'd0;
+wire builder_csrbank1_sram_reader_slot0_r;
+reg builder_csrbank1_sram_reader_slot0_we = 1'd0;
+wire builder_csrbank1_sram_reader_slot0_w;
+reg builder_csrbank1_sram_reader_length0_re = 1'd0;
+wire [10:0] builder_csrbank1_sram_reader_length0_r;
+reg builder_csrbank1_sram_reader_length0_we = 1'd0;
+wire [10:0] builder_csrbank1_sram_reader_length0_w;
+reg builder_csrbank1_sram_reader_ev_status_re = 1'd0;
+wire builder_csrbank1_sram_reader_ev_status_r;
+reg builder_csrbank1_sram_reader_ev_status_we = 1'd0;
+wire builder_csrbank1_sram_reader_ev_status_w;
+reg builder_csrbank1_sram_reader_ev_pending_re = 1'd0;
+wire builder_csrbank1_sram_reader_ev_pending_r;
+reg builder_csrbank1_sram_reader_ev_pending_we = 1'd0;
+wire builder_csrbank1_sram_reader_ev_pending_w;
+reg builder_csrbank1_sram_reader_ev_enable0_re = 1'd0;
+wire builder_csrbank1_sram_reader_ev_enable0_r;
+reg builder_csrbank1_sram_reader_ev_enable0_we = 1'd0;
+wire builder_csrbank1_sram_reader_ev_enable0_w;
+reg builder_csrbank1_preamble_crc_re = 1'd0;
+wire builder_csrbank1_preamble_crc_r;
+reg builder_csrbank1_preamble_crc_we = 1'd0;
+wire builder_csrbank1_preamble_crc_w;
+reg builder_csrbank1_preamble_errors_re = 1'd0;
+wire [31:0] builder_csrbank1_preamble_errors_r;
+reg builder_csrbank1_preamble_errors_we = 1'd0;
+wire [31:0] builder_csrbank1_preamble_errors_w;
+reg builder_csrbank1_crc_errors_re = 1'd0;
+wire [31:0] builder_csrbank1_crc_errors_r;
+reg builder_csrbank1_crc_errors_we = 1'd0;
+wire [31:0] builder_csrbank1_crc_errors_w;
+wire builder_csrbank1_sel;
+wire [13:0] builder_interface2_bank_bus_adr;
+wire builder_interface2_bank_bus_we;
+wire [31:0] builder_interface2_bank_bus_dat_w;
+reg [31:0] builder_interface2_bank_bus_dat_r = 32'd0;
+reg builder_csrbank2_crg_reset0_re = 1'd0;
+wire builder_csrbank2_crg_reset0_r;
+reg builder_csrbank2_crg_reset0_we = 1'd0;
+wire builder_csrbank2_crg_reset0_w;
+reg builder_csrbank2_rx_inband_status_re = 1'd0;
+wire [2:0] builder_csrbank2_rx_inband_status_r;
+reg builder_csrbank2_rx_inband_status_we = 1'd0;
+wire [2:0] builder_csrbank2_rx_inband_status_w;
+reg builder_csrbank2_mdio_w0_re = 1'd0;
+wire [2:0] builder_csrbank2_mdio_w0_r;
+reg builder_csrbank2_mdio_w0_we = 1'd0;
+wire [2:0] builder_csrbank2_mdio_w0_w;
+reg builder_csrbank2_mdio_r_re = 1'd0;
+wire builder_csrbank2_mdio_r_r;
+reg builder_csrbank2_mdio_r_we = 1'd0;
+wire builder_csrbank2_mdio_r_w;
+wire builder_csrbank2_sel;
+wire [13:0] builder_csr_interconnect_adr;
+wire builder_csr_interconnect_we;
+wire [31:0] builder_csr_interconnect_dat_w;
+wire [31:0] builder_csr_interconnect_dat_r;
+reg builder_state = 1'd0;
+reg builder_next_state = 1'd0;
+reg [29:0] builder_array_muxed0 = 30'd0;
+reg [31:0] builder_array_muxed1 = 32'd0;
+reg [3:0] builder_array_muxed2 = 4'd0;
+reg builder_array_muxed3 = 1'd0;
+reg builder_array_muxed4 = 1'd0;
+reg builder_array_muxed5 = 1'd0;
+reg [2:0] builder_array_muxed6 = 3'd0;
+reg [1:0] builder_array_muxed7 = 2'd0;
+wire builder_rst10;
+wire builder_rst11;
+(* syn_no_retiming = "true" *) reg builder_multiregimpl0_regs0 = 1'd0;
+(* syn_no_retiming = "true" *) reg builder_multiregimpl0_regs1 = 1'd0;
+(* syn_no_retiming = "true" *) reg builder_multiregimpl1_regs0 = 1'd0;
+(* syn_no_retiming = "true" *) reg builder_multiregimpl1_regs1 = 1'd0;
+(* syn_no_retiming = "true" *) reg builder_multiregimpl2_regs0 = 1'd0;
+(* syn_no_retiming = "true" *) reg builder_multiregimpl2_regs1 = 1'd0;
+(* syn_no_retiming = "true" *) reg [5:0] builder_multiregimpl3_regs0 = 6'd0;
+(* syn_no_retiming = "true" *) reg [5:0] builder_multiregimpl3_regs1 = 6'd0;
+(* syn_no_retiming = "true" *) reg [5:0] builder_multiregimpl4_regs0 = 6'd0;
+(* syn_no_retiming = "true" *) reg [5:0] builder_multiregimpl4_regs1 = 6'd0;
+(* syn_no_retiming = "true" *) reg [5:0] builder_multiregimpl5_regs0 = 6'd0;
+(* syn_no_retiming = "true" *) reg [5:0] builder_multiregimpl5_regs1 = 6'd0;
+(* syn_no_retiming = "true" *) reg [5:0] builder_multiregimpl6_regs0 = 6'd0;
+(* syn_no_retiming = "true" *) reg [5:0] builder_multiregimpl6_regs1 = 6'd0;
+
+//------------------------------------------------------------------------------
+// Combinatorial Logic
+//------------------------------------------------------------------------------
+
+assign main_wb_bus_adr = wishbone_adr;
+assign main_wb_bus_dat_w = wishbone_dat_w;
+assign wishbone_dat_r = main_wb_bus_dat_r;
+assign main_wb_bus_sel = wishbone_sel;
+assign main_wb_bus_cyc = wishbone_cyc;
+assign main_wb_bus_stb = wishbone_stb;
+assign wishbone_ack = main_wb_bus_ack;
+assign main_wb_bus_we = wishbone_we;
+assign main_wb_bus_cti = wishbone_cti;
+assign main_wb_bus_bte = wishbone_bte;
+assign wishbone_err = main_wb_bus_err;
+assign interrupt = main_ev_irq;
+assign main_maccore_maccore_bus_error = builder_error;
+assign main_maccore_maccore_bus_errors_status = main_maccore_maccore_bus_errors;
+assign sys_clk = sys_clock;
+assign por_clk = sys_clock;
+assign sys_rst = main_maccore_int_rst;
+assign eth_rx_clk = rgmii_eth_clocks_rx;
+assign eth_tx_clk = eth_rx_clk;
+assign main_maccore_ethphy_reset = main_maccore_ethphy_reset_storage;
+assign rgmii_eth_rst_n = (~main_maccore_ethphy_reset);
+assign main_maccore_ethphy_sink_ready = 1'd1;
+assign main_maccore_ethphy_last = ((~main_maccore_ethphy_rx_ctl_reg[0]) & main_maccore_ethphy_rx_ctl_reg_d[0]);
+assign main_maccore_ethphy_source_last = main_maccore_ethphy_last;
+assign rgmii_eth_mdc = main_maccore_ethphy__w_storage[0];
+assign main_maccore_ethphy_data_oe = main_maccore_ethphy__w_storage[1];
+assign main_maccore_ethphy_data_w = main_maccore_ethphy__w_storage[2];
+assign main_tx_cdc_sink_sink_valid = main_source_valid;
+assign main_source_ready = main_tx_cdc_sink_sink_ready;
+assign main_tx_cdc_sink_sink_first = main_source_first;
+assign main_tx_cdc_sink_sink_last = main_source_last;
+assign main_tx_cdc_sink_sink_payload_data = main_source_payload_data;
+assign main_tx_cdc_sink_sink_payload_last_be = main_source_payload_last_be;
+assign main_tx_cdc_sink_sink_payload_error = main_source_payload_error;
+assign main_sink_valid = main_rx_cdc_source_source_valid;
+assign main_rx_cdc_source_source_ready = main_sink_ready;
+assign main_sink_first = main_rx_cdc_source_source_first;
+assign main_sink_last = main_rx_cdc_source_source_last;
+assign main_sink_payload_data = main_rx_cdc_source_source_payload_data;
+assign main_sink_payload_last_be = main_rx_cdc_source_source_payload_last_be;
+assign main_sink_payload_error = main_rx_cdc_source_source_payload_error;
+assign main_ps_preamble_error_i = main_preamble_checker_error;
+assign main_ps_crc_error_i = main_liteethmaccrc32checker_error;
+always @(*) begin
+ main_tx_gap_inserter_sink_ready <= 1'd0;
+ builder_liteethmacgap_next_state <= 1'd0;
+ main_tx_gap_inserter_counter_liteethmacgap_next_value <= 4'd0;
+ main_tx_gap_inserter_counter_liteethmacgap_next_value_ce <= 1'd0;
+ main_tx_gap_inserter_source_valid <= 1'd0;
+ main_tx_gap_inserter_source_first <= 1'd0;
+ main_tx_gap_inserter_source_last <= 1'd0;
+ main_tx_gap_inserter_source_payload_data <= 8'd0;
+ main_tx_gap_inserter_source_payload_last_be <= 1'd0;
+ main_tx_gap_inserter_source_payload_error <= 1'd0;
+ builder_liteethmacgap_next_state <= builder_liteethmacgap_state;
+ case (builder_liteethmacgap_state)
+ 1'd1: begin
+ main_tx_gap_inserter_counter_liteethmacgap_next_value <= (main_tx_gap_inserter_counter + 1'd1);
+ main_tx_gap_inserter_counter_liteethmacgap_next_value_ce <= 1'd1;
+ if ((main_tx_gap_inserter_counter == 4'd11)) begin
+ builder_liteethmacgap_next_state <= 1'd0;
+ end
+ end
+ default: begin
+ main_tx_gap_inserter_counter_liteethmacgap_next_value <= 1'd0;
+ main_tx_gap_inserter_counter_liteethmacgap_next_value_ce <= 1'd1;
+ main_tx_gap_inserter_source_valid <= main_tx_gap_inserter_sink_valid;
+ main_tx_gap_inserter_sink_ready <= main_tx_gap_inserter_source_ready;
+ main_tx_gap_inserter_source_first <= main_tx_gap_inserter_sink_first;
+ main_tx_gap_inserter_source_last <= main_tx_gap_inserter_sink_last;
+ main_tx_gap_inserter_source_payload_data <= main_tx_gap_inserter_sink_payload_data;
+ main_tx_gap_inserter_source_payload_last_be <= main_tx_gap_inserter_sink_payload_last_be;
+ main_tx_gap_inserter_source_payload_error <= main_tx_gap_inserter_sink_payload_error;
+ if (((main_tx_gap_inserter_sink_valid & main_tx_gap_inserter_sink_last) & main_tx_gap_inserter_sink_ready)) begin
+ builder_liteethmacgap_next_state <= 1'd1;
+ end
+ end
+ endcase
+end
+assign main_preamble_inserter_source_payload_last_be = main_preamble_inserter_sink_payload_last_be;
+always @(*) begin
+ builder_liteethmacpreambleinserter_next_state <= 2'd0;
+ main_preamble_inserter_count_liteethmacpreambleinserter_next_value <= 3'd0;
+ main_preamble_inserter_count_liteethmacpreambleinserter_next_value_ce <= 1'd0;
+ main_preamble_inserter_source_valid <= 1'd0;
+ main_preamble_inserter_source_first <= 1'd0;
+ main_preamble_inserter_source_last <= 1'd0;
+ main_preamble_inserter_source_payload_data <= 8'd0;
+ main_preamble_inserter_source_payload_error <= 1'd0;
+ main_preamble_inserter_sink_ready <= 1'd0;
+ main_preamble_inserter_source_payload_data <= main_preamble_inserter_sink_payload_data;
+ builder_liteethmacpreambleinserter_next_state <= builder_liteethmacpreambleinserter_state;
+ case (builder_liteethmacpreambleinserter_state)
+ 1'd1: begin
+ main_preamble_inserter_source_valid <= 1'd1;
+ case (main_preamble_inserter_count)
+ 1'd0: begin
+ main_preamble_inserter_source_payload_data <= main_preamble_inserter_preamble[7:0];
+ end
+ 1'd1: begin
+ main_preamble_inserter_source_payload_data <= main_preamble_inserter_preamble[15:8];
+ end
+ 2'd2: begin
+ main_preamble_inserter_source_payload_data <= main_preamble_inserter_preamble[23:16];
+ end
+ 2'd3: begin
+ main_preamble_inserter_source_payload_data <= main_preamble_inserter_preamble[31:24];
+ end
+ 3'd4: begin
+ main_preamble_inserter_source_payload_data <= main_preamble_inserter_preamble[39:32];
+ end
+ 3'd5: begin
+ main_preamble_inserter_source_payload_data <= main_preamble_inserter_preamble[47:40];
+ end
+ 3'd6: begin
+ main_preamble_inserter_source_payload_data <= main_preamble_inserter_preamble[55:48];
+ end
+ default: begin
+ main_preamble_inserter_source_payload_data <= main_preamble_inserter_preamble[63:56];
+ end
+ endcase
+ if (main_preamble_inserter_source_ready) begin
+ if ((main_preamble_inserter_count == 3'd7)) begin
+ builder_liteethmacpreambleinserter_next_state <= 2'd2;
+ end else begin
+ main_preamble_inserter_count_liteethmacpreambleinserter_next_value <= (main_preamble_inserter_count + 1'd1);
+ main_preamble_inserter_count_liteethmacpreambleinserter_next_value_ce <= 1'd1;
+ end
+ end
+ end
+ 2'd2: begin
+ main_preamble_inserter_source_valid <= main_preamble_inserter_sink_valid;
+ main_preamble_inserter_sink_ready <= main_preamble_inserter_source_ready;
+ main_preamble_inserter_source_first <= main_preamble_inserter_sink_first;
+ main_preamble_inserter_source_last <= main_preamble_inserter_sink_last;
+ main_preamble_inserter_source_payload_error <= main_preamble_inserter_sink_payload_error;
+ if (((main_preamble_inserter_sink_valid & main_preamble_inserter_sink_last) & main_preamble_inserter_source_ready)) begin
+ builder_liteethmacpreambleinserter_next_state <= 1'd0;
+ end
+ end
+ default: begin
+ main_preamble_inserter_sink_ready <= 1'd1;
+ main_preamble_inserter_count_liteethmacpreambleinserter_next_value <= 1'd0;
+ main_preamble_inserter_count_liteethmacpreambleinserter_next_value_ce <= 1'd1;
+ if (main_preamble_inserter_sink_valid) begin
+ main_preamble_inserter_sink_ready <= 1'd0;
+ builder_liteethmacpreambleinserter_next_state <= 1'd1;
+ end
+ end
+ endcase
+end
+assign main_preamble_checker_source_payload_data = main_preamble_checker_sink_payload_data;
+assign main_preamble_checker_source_payload_last_be = main_preamble_checker_sink_payload_last_be;
+always @(*) begin
+ main_preamble_checker_error <= 1'd0;
+ main_preamble_checker_source_valid <= 1'd0;
+ main_preamble_checker_source_first <= 1'd0;
+ main_preamble_checker_sink_ready <= 1'd0;
+ main_preamble_checker_source_last <= 1'd0;
+ main_preamble_checker_source_payload_error <= 1'd0;
+ builder_liteethmacpreamblechecker_next_state <= 1'd0;
+ builder_liteethmacpreamblechecker_next_state <= builder_liteethmacpreamblechecker_state;
+ case (builder_liteethmacpreamblechecker_state)
+ 1'd1: begin
+ main_preamble_checker_source_valid <= main_preamble_checker_sink_valid;
+ main_preamble_checker_sink_ready <= main_preamble_checker_source_ready;
+ main_preamble_checker_source_first <= main_preamble_checker_sink_first;
+ main_preamble_checker_source_last <= main_preamble_checker_sink_last;
+ main_preamble_checker_source_payload_error <= main_preamble_checker_sink_payload_error;
+ if (((main_preamble_checker_source_valid & main_preamble_checker_source_last) & main_preamble_checker_source_ready)) begin
+ builder_liteethmacpreamblechecker_next_state <= 1'd0;
+ end
+ end
+ default: begin
+ main_preamble_checker_sink_ready <= 1'd1;
+ if (((main_preamble_checker_sink_valid & (~main_preamble_checker_sink_last)) & (main_preamble_checker_sink_payload_data == 8'd213))) begin
+ builder_liteethmacpreamblechecker_next_state <= 1'd1;
+ end
+ if ((main_preamble_checker_sink_valid & main_preamble_checker_sink_last)) begin
+ main_preamble_checker_error <= 1'd1;
+ end
+ end
+ endcase
+end
+assign main_liteethmaccrc32inserter_cnt_done = (main_liteethmaccrc32inserter_cnt == 1'd0);
+assign main_liteethmaccrc32inserter_sink_valid = main_crc32_inserter_source_valid;
+assign main_crc32_inserter_source_ready = main_liteethmaccrc32inserter_sink_ready;
+assign main_liteethmaccrc32inserter_sink_first = main_crc32_inserter_source_first;
+assign main_liteethmaccrc32inserter_sink_last = main_crc32_inserter_source_last;
+assign main_liteethmaccrc32inserter_sink_payload_data = main_crc32_inserter_source_payload_data;
+assign main_liteethmaccrc32inserter_sink_payload_last_be = main_crc32_inserter_source_payload_last_be;
+assign main_liteethmaccrc32inserter_sink_payload_error = main_crc32_inserter_source_payload_error;
+assign main_liteethmaccrc32inserter_data1 = main_liteethmaccrc32inserter_data0;
+assign main_liteethmaccrc32inserter_last = main_liteethmaccrc32inserter_reg;
+assign main_liteethmaccrc32inserter_value = (~{main_liteethmaccrc32inserter_reg[0], main_liteethmaccrc32inserter_reg[1], main_liteethmaccrc32inserter_reg[2], main_liteethmaccrc32inserter_reg[3], main_liteethmaccrc32inserter_reg[4], main_liteethmaccrc32inserter_reg[5], main_liteethmaccrc32inserter_reg[6], main_liteethmaccrc32inserter_reg[7], main_liteethmaccrc32inserter_reg[8], main_liteethmaccrc32inserter_reg[9], main_liteethmaccrc32inserter_reg[10], main_liteethmaccrc32inserter_reg[11], main_liteethmaccrc32inserter_reg[12], main_liteethmaccrc32inserter_reg[13], main_liteethmaccrc32inserter_reg[14], main_liteethmaccrc32inserter_reg[15], main_liteethmaccrc32inserter_reg[16], main_liteethmaccrc32inserter_reg[17], main_liteethmaccrc32inserter_reg[18], main_liteethmaccrc32inserter_reg[19], main_liteethmaccrc32inserter_reg[20], main_liteethmaccrc32inserter_reg[21], main_liteethmaccrc32inserter_reg[22], main_liteethmaccrc32inserter_reg[23], main_liteethmaccrc32inserter_reg[24], main_liteethmaccrc32inserter_reg[25], main_liteethmaccrc32inserter_reg[26], main_liteethmaccrc32inserter_reg[27], main_liteethmaccrc32inserter_reg[28], main_liteethmaccrc32inserter_reg[29], main_liteethmaccrc32inserter_reg[30], main_liteethmaccrc32inserter_reg[31]});
+assign main_liteethmaccrc32inserter_error = (main_liteethmaccrc32inserter_next != 32'd3338984827);
+always @(*) begin
+ main_liteethmaccrc32inserter_next <= 32'd0;
+ main_liteethmaccrc32inserter_next[0] <= (((main_liteethmaccrc32inserter_last[24] ^ main_liteethmaccrc32inserter_last[30]) ^ main_liteethmaccrc32inserter_data1[1]) ^ main_liteethmaccrc32inserter_data1[7]);
+ main_liteethmaccrc32inserter_next[1] <= (((((((main_liteethmaccrc32inserter_last[25] ^ main_liteethmaccrc32inserter_last[31]) ^ main_liteethmaccrc32inserter_data1[0]) ^ main_liteethmaccrc32inserter_data1[6]) ^ main_liteethmaccrc32inserter_last[24]) ^ main_liteethmaccrc32inserter_last[30]) ^ main_liteethmaccrc32inserter_data1[1]) ^ main_liteethmaccrc32inserter_data1[7]);
+ main_liteethmaccrc32inserter_next[2] <= (((((((((main_liteethmaccrc32inserter_last[26] ^ main_liteethmaccrc32inserter_data1[5]) ^ main_liteethmaccrc32inserter_last[25]) ^ main_liteethmaccrc32inserter_last[31]) ^ main_liteethmaccrc32inserter_data1[0]) ^ main_liteethmaccrc32inserter_data1[6]) ^ main_liteethmaccrc32inserter_last[24]) ^ main_liteethmaccrc32inserter_last[30]) ^ main_liteethmaccrc32inserter_data1[1]) ^ main_liteethmaccrc32inserter_data1[7]);
+ main_liteethmaccrc32inserter_next[3] <= (((((((main_liteethmaccrc32inserter_last[27] ^ main_liteethmaccrc32inserter_data1[4]) ^ main_liteethmaccrc32inserter_last[26]) ^ main_liteethmaccrc32inserter_data1[5]) ^ main_liteethmaccrc32inserter_last[25]) ^ main_liteethmaccrc32inserter_last[31]) ^ main_liteethmaccrc32inserter_data1[0]) ^ main_liteethmaccrc32inserter_data1[6]);
+ main_liteethmaccrc32inserter_next[4] <= (((((((((main_liteethmaccrc32inserter_last[28] ^ main_liteethmaccrc32inserter_data1[3]) ^ main_liteethmaccrc32inserter_last[27]) ^ main_liteethmaccrc32inserter_data1[4]) ^ main_liteethmaccrc32inserter_last[26]) ^ main_liteethmaccrc32inserter_data1[5]) ^ main_liteethmaccrc32inserter_last[24]) ^ main_liteethmaccrc32inserter_last[30]) ^ main_liteethmaccrc32inserter_data1[1]) ^ main_liteethmaccrc32inserter_data1[7]);
+ main_liteethmaccrc32inserter_next[5] <= (((((((((((((main_liteethmaccrc32inserter_last[29] ^ main_liteethmaccrc32inserter_data1[2]) ^ main_liteethmaccrc32inserter_last[28]) ^ main_liteethmaccrc32inserter_data1[3]) ^ main_liteethmaccrc32inserter_last[27]) ^ main_liteethmaccrc32inserter_data1[4]) ^ main_liteethmaccrc32inserter_last[25]) ^ main_liteethmaccrc32inserter_last[31]) ^ main_liteethmaccrc32inserter_data1[0]) ^ main_liteethmaccrc32inserter_data1[6]) ^ main_liteethmaccrc32inserter_last[24]) ^ main_liteethmaccrc32inserter_last[30]) ^ main_liteethmaccrc32inserter_data1[1]) ^ main_liteethmaccrc32inserter_data1[7]);
+ main_liteethmaccrc32inserter_next[6] <= (((((((((((main_liteethmaccrc32inserter_last[30] ^ main_liteethmaccrc32inserter_data1[1]) ^ main_liteethmaccrc32inserter_last[29]) ^ main_liteethmaccrc32inserter_data1[2]) ^ main_liteethmaccrc32inserter_last[28]) ^ main_liteethmaccrc32inserter_data1[3]) ^ main_liteethmaccrc32inserter_last[26]) ^ main_liteethmaccrc32inserter_data1[5]) ^ main_liteethmaccrc32inserter_last[25]) ^ main_liteethmaccrc32inserter_last[31]) ^ main_liteethmaccrc32inserter_data1[0]) ^ main_liteethmaccrc32inserter_data1[6]);
+ main_liteethmaccrc32inserter_next[7] <= (((((((((main_liteethmaccrc32inserter_last[31] ^ main_liteethmaccrc32inserter_data1[0]) ^ main_liteethmaccrc32inserter_last[29]) ^ main_liteethmaccrc32inserter_data1[2]) ^ main_liteethmaccrc32inserter_last[27]) ^ main_liteethmaccrc32inserter_data1[4]) ^ main_liteethmaccrc32inserter_last[26]) ^ main_liteethmaccrc32inserter_data1[5]) ^ main_liteethmaccrc32inserter_last[24]) ^ main_liteethmaccrc32inserter_data1[7]);
+ main_liteethmaccrc32inserter_next[8] <= ((((((((main_liteethmaccrc32inserter_last[0] ^ main_liteethmaccrc32inserter_last[28]) ^ main_liteethmaccrc32inserter_data1[3]) ^ main_liteethmaccrc32inserter_last[27]) ^ main_liteethmaccrc32inserter_data1[4]) ^ main_liteethmaccrc32inserter_last[25]) ^ main_liteethmaccrc32inserter_data1[6]) ^ main_liteethmaccrc32inserter_last[24]) ^ main_liteethmaccrc32inserter_data1[7]);
+ main_liteethmaccrc32inserter_next[9] <= ((((((((main_liteethmaccrc32inserter_last[1] ^ main_liteethmaccrc32inserter_last[29]) ^ main_liteethmaccrc32inserter_data1[2]) ^ main_liteethmaccrc32inserter_last[28]) ^ main_liteethmaccrc32inserter_data1[3]) ^ main_liteethmaccrc32inserter_last[26]) ^ main_liteethmaccrc32inserter_data1[5]) ^ main_liteethmaccrc32inserter_last[25]) ^ main_liteethmaccrc32inserter_data1[6]);
+ main_liteethmaccrc32inserter_next[10] <= ((((((((main_liteethmaccrc32inserter_last[2] ^ main_liteethmaccrc32inserter_last[29]) ^ main_liteethmaccrc32inserter_data1[2]) ^ main_liteethmaccrc32inserter_last[27]) ^ main_liteethmaccrc32inserter_data1[4]) ^ main_liteethmaccrc32inserter_last[26]) ^ main_liteethmaccrc32inserter_data1[5]) ^ main_liteethmaccrc32inserter_last[24]) ^ main_liteethmaccrc32inserter_data1[7]);
+ main_liteethmaccrc32inserter_next[11] <= ((((((((main_liteethmaccrc32inserter_last[3] ^ main_liteethmaccrc32inserter_last[28]) ^ main_liteethmaccrc32inserter_data1[3]) ^ main_liteethmaccrc32inserter_last[27]) ^ main_liteethmaccrc32inserter_data1[4]) ^ main_liteethmaccrc32inserter_last[25]) ^ main_liteethmaccrc32inserter_data1[6]) ^ main_liteethmaccrc32inserter_last[24]) ^ main_liteethmaccrc32inserter_data1[7]);
+ main_liteethmaccrc32inserter_next[12] <= ((((((((((((main_liteethmaccrc32inserter_last[4] ^ main_liteethmaccrc32inserter_last[29]) ^ main_liteethmaccrc32inserter_data1[2]) ^ main_liteethmaccrc32inserter_last[28]) ^ main_liteethmaccrc32inserter_data1[3]) ^ main_liteethmaccrc32inserter_last[26]) ^ main_liteethmaccrc32inserter_data1[5]) ^ main_liteethmaccrc32inserter_last[25]) ^ main_liteethmaccrc32inserter_data1[6]) ^ main_liteethmaccrc32inserter_last[24]) ^ main_liteethmaccrc32inserter_last[30]) ^ main_liteethmaccrc32inserter_data1[1]) ^ main_liteethmaccrc32inserter_data1[7]);
+ main_liteethmaccrc32inserter_next[13] <= ((((((((((((main_liteethmaccrc32inserter_last[5] ^ main_liteethmaccrc32inserter_last[30]) ^ main_liteethmaccrc32inserter_data1[1]) ^ main_liteethmaccrc32inserter_last[29]) ^ main_liteethmaccrc32inserter_data1[2]) ^ main_liteethmaccrc32inserter_last[27]) ^ main_liteethmaccrc32inserter_data1[4]) ^ main_liteethmaccrc32inserter_last[26]) ^ main_liteethmaccrc32inserter_data1[5]) ^ main_liteethmaccrc32inserter_last[25]) ^ main_liteethmaccrc32inserter_last[31]) ^ main_liteethmaccrc32inserter_data1[0]) ^ main_liteethmaccrc32inserter_data1[6]);
+ main_liteethmaccrc32inserter_next[14] <= ((((((((((main_liteethmaccrc32inserter_last[6] ^ main_liteethmaccrc32inserter_last[31]) ^ main_liteethmaccrc32inserter_data1[0]) ^ main_liteethmaccrc32inserter_last[30]) ^ main_liteethmaccrc32inserter_data1[1]) ^ main_liteethmaccrc32inserter_last[28]) ^ main_liteethmaccrc32inserter_data1[3]) ^ main_liteethmaccrc32inserter_last[27]) ^ main_liteethmaccrc32inserter_data1[4]) ^ main_liteethmaccrc32inserter_last[26]) ^ main_liteethmaccrc32inserter_data1[5]);
+ main_liteethmaccrc32inserter_next[15] <= ((((((((main_liteethmaccrc32inserter_last[7] ^ main_liteethmaccrc32inserter_last[31]) ^ main_liteethmaccrc32inserter_data1[0]) ^ main_liteethmaccrc32inserter_last[29]) ^ main_liteethmaccrc32inserter_data1[2]) ^ main_liteethmaccrc32inserter_last[28]) ^ main_liteethmaccrc32inserter_data1[3]) ^ main_liteethmaccrc32inserter_last[27]) ^ main_liteethmaccrc32inserter_data1[4]);
+ main_liteethmaccrc32inserter_next[16] <= ((((((main_liteethmaccrc32inserter_last[8] ^ main_liteethmaccrc32inserter_last[29]) ^ main_liteethmaccrc32inserter_data1[2]) ^ main_liteethmaccrc32inserter_last[28]) ^ main_liteethmaccrc32inserter_data1[3]) ^ main_liteethmaccrc32inserter_last[24]) ^ main_liteethmaccrc32inserter_data1[7]);
+ main_liteethmaccrc32inserter_next[17] <= ((((((main_liteethmaccrc32inserter_last[9] ^ main_liteethmaccrc32inserter_last[30]) ^ main_liteethmaccrc32inserter_data1[1]) ^ main_liteethmaccrc32inserter_last[29]) ^ main_liteethmaccrc32inserter_data1[2]) ^ main_liteethmaccrc32inserter_last[25]) ^ main_liteethmaccrc32inserter_data1[6]);
+ main_liteethmaccrc32inserter_next[18] <= ((((((main_liteethmaccrc32inserter_last[10] ^ main_liteethmaccrc32inserter_last[31]) ^ main_liteethmaccrc32inserter_data1[0]) ^ main_liteethmaccrc32inserter_last[30]) ^ main_liteethmaccrc32inserter_data1[1]) ^ main_liteethmaccrc32inserter_last[26]) ^ main_liteethmaccrc32inserter_data1[5]);
+ main_liteethmaccrc32inserter_next[19] <= ((((main_liteethmaccrc32inserter_last[11] ^ main_liteethmaccrc32inserter_last[31]) ^ main_liteethmaccrc32inserter_data1[0]) ^ main_liteethmaccrc32inserter_last[27]) ^ main_liteethmaccrc32inserter_data1[4]);
+ main_liteethmaccrc32inserter_next[20] <= ((main_liteethmaccrc32inserter_last[12] ^ main_liteethmaccrc32inserter_last[28]) ^ main_liteethmaccrc32inserter_data1[3]);
+ main_liteethmaccrc32inserter_next[21] <= ((main_liteethmaccrc32inserter_last[13] ^ main_liteethmaccrc32inserter_last[29]) ^ main_liteethmaccrc32inserter_data1[2]);
+ main_liteethmaccrc32inserter_next[22] <= ((main_liteethmaccrc32inserter_last[14] ^ main_liteethmaccrc32inserter_last[24]) ^ main_liteethmaccrc32inserter_data1[7]);
+ main_liteethmaccrc32inserter_next[23] <= ((((((main_liteethmaccrc32inserter_last[15] ^ main_liteethmaccrc32inserter_last[25]) ^ main_liteethmaccrc32inserter_data1[6]) ^ main_liteethmaccrc32inserter_last[24]) ^ main_liteethmaccrc32inserter_last[30]) ^ main_liteethmaccrc32inserter_data1[1]) ^ main_liteethmaccrc32inserter_data1[7]);
+ main_liteethmaccrc32inserter_next[24] <= ((((((main_liteethmaccrc32inserter_last[16] ^ main_liteethmaccrc32inserter_last[26]) ^ main_liteethmaccrc32inserter_data1[5]) ^ main_liteethmaccrc32inserter_last[25]) ^ main_liteethmaccrc32inserter_last[31]) ^ main_liteethmaccrc32inserter_data1[0]) ^ main_liteethmaccrc32inserter_data1[6]);
+ main_liteethmaccrc32inserter_next[25] <= ((((main_liteethmaccrc32inserter_last[17] ^ main_liteethmaccrc32inserter_last[27]) ^ main_liteethmaccrc32inserter_data1[4]) ^ main_liteethmaccrc32inserter_last[26]) ^ main_liteethmaccrc32inserter_data1[5]);
+ main_liteethmaccrc32inserter_next[26] <= ((((((((main_liteethmaccrc32inserter_last[18] ^ main_liteethmaccrc32inserter_last[28]) ^ main_liteethmaccrc32inserter_data1[3]) ^ main_liteethmaccrc32inserter_last[27]) ^ main_liteethmaccrc32inserter_data1[4]) ^ main_liteethmaccrc32inserter_last[24]) ^ main_liteethmaccrc32inserter_last[30]) ^ main_liteethmaccrc32inserter_data1[1]) ^ main_liteethmaccrc32inserter_data1[7]);
+ main_liteethmaccrc32inserter_next[27] <= ((((((((main_liteethmaccrc32inserter_last[19] ^ main_liteethmaccrc32inserter_last[29]) ^ main_liteethmaccrc32inserter_data1[2]) ^ main_liteethmaccrc32inserter_last[28]) ^ main_liteethmaccrc32inserter_data1[3]) ^ main_liteethmaccrc32inserter_last[25]) ^ main_liteethmaccrc32inserter_last[31]) ^ main_liteethmaccrc32inserter_data1[0]) ^ main_liteethmaccrc32inserter_data1[6]);
+ main_liteethmaccrc32inserter_next[28] <= ((((((main_liteethmaccrc32inserter_last[20] ^ main_liteethmaccrc32inserter_last[30]) ^ main_liteethmaccrc32inserter_data1[1]) ^ main_liteethmaccrc32inserter_last[29]) ^ main_liteethmaccrc32inserter_data1[2]) ^ main_liteethmaccrc32inserter_last[26]) ^ main_liteethmaccrc32inserter_data1[5]);
+ main_liteethmaccrc32inserter_next[29] <= ((((((main_liteethmaccrc32inserter_last[21] ^ main_liteethmaccrc32inserter_last[31]) ^ main_liteethmaccrc32inserter_data1[0]) ^ main_liteethmaccrc32inserter_last[30]) ^ main_liteethmaccrc32inserter_data1[1]) ^ main_liteethmaccrc32inserter_last[27]) ^ main_liteethmaccrc32inserter_data1[4]);
+ main_liteethmaccrc32inserter_next[30] <= ((((main_liteethmaccrc32inserter_last[22] ^ main_liteethmaccrc32inserter_last[31]) ^ main_liteethmaccrc32inserter_data1[0]) ^ main_liteethmaccrc32inserter_last[28]) ^ main_liteethmaccrc32inserter_data1[3]);
+ main_liteethmaccrc32inserter_next[31] <= ((main_liteethmaccrc32inserter_last[23] ^ main_liteethmaccrc32inserter_last[29]) ^ main_liteethmaccrc32inserter_data1[2]);
+end
+always @(*) begin
+ main_liteethmaccrc32inserter_is_ongoing1 <= 1'd0;
+ main_liteethmaccrc32inserter_ce <= 1'd0;
+ main_liteethmaccrc32inserter_reset <= 1'd0;
+ main_liteethmaccrc32inserter_source_valid <= 1'd0;
+ main_liteethmaccrc32inserter_source_first <= 1'd0;
+ main_liteethmaccrc32inserter_source_last <= 1'd0;
+ builder_liteethmaccrc32inserter_next_state <= 2'd0;
+ main_liteethmaccrc32inserter_source_payload_data <= 8'd0;
+ main_liteethmaccrc32inserter_source_payload_last_be <= 1'd0;
+ main_liteethmaccrc32inserter_source_payload_error <= 1'd0;
+ main_liteethmaccrc32inserter_data0 <= 8'd0;
+ main_liteethmaccrc32inserter_is_ongoing0 <= 1'd0;
+ main_liteethmaccrc32inserter_sink_ready <= 1'd0;
+ builder_liteethmaccrc32inserter_next_state <= builder_liteethmaccrc32inserter_state;
+ case (builder_liteethmaccrc32inserter_state)
+ 1'd1: begin
+ main_liteethmaccrc32inserter_ce <= (main_liteethmaccrc32inserter_sink_valid & main_liteethmaccrc32inserter_source_ready);
+ main_liteethmaccrc32inserter_data0 <= main_liteethmaccrc32inserter_sink_payload_data;
+ main_liteethmaccrc32inserter_source_valid <= main_liteethmaccrc32inserter_sink_valid;
+ main_liteethmaccrc32inserter_sink_ready <= main_liteethmaccrc32inserter_source_ready;
+ main_liteethmaccrc32inserter_source_first <= main_liteethmaccrc32inserter_sink_first;
+ main_liteethmaccrc32inserter_source_last <= main_liteethmaccrc32inserter_sink_last;
+ main_liteethmaccrc32inserter_source_payload_data <= main_liteethmaccrc32inserter_sink_payload_data;
+ main_liteethmaccrc32inserter_source_payload_last_be <= main_liteethmaccrc32inserter_sink_payload_last_be;
+ main_liteethmaccrc32inserter_source_payload_error <= main_liteethmaccrc32inserter_sink_payload_error;
+ main_liteethmaccrc32inserter_source_last <= 1'd0;
+ if (((main_liteethmaccrc32inserter_sink_valid & main_liteethmaccrc32inserter_sink_last) & main_liteethmaccrc32inserter_source_ready)) begin
+ builder_liteethmaccrc32inserter_next_state <= 2'd2;
+ end
+ end
+ 2'd2: begin
+ main_liteethmaccrc32inserter_source_valid <= 1'd1;
+ case (main_liteethmaccrc32inserter_cnt)
+ 1'd0: begin
+ main_liteethmaccrc32inserter_source_payload_data <= main_liteethmaccrc32inserter_value[31:24];
+ end
+ 1'd1: begin
+ main_liteethmaccrc32inserter_source_payload_data <= main_liteethmaccrc32inserter_value[23:16];
+ end
+ 2'd2: begin
+ main_liteethmaccrc32inserter_source_payload_data <= main_liteethmaccrc32inserter_value[15:8];
+ end
+ default: begin
+ main_liteethmaccrc32inserter_source_payload_data <= main_liteethmaccrc32inserter_value[7:0];
+ end
+ endcase
+ if (main_liteethmaccrc32inserter_cnt_done) begin
+ main_liteethmaccrc32inserter_source_last <= 1'd1;
+ if (main_liteethmaccrc32inserter_source_ready) begin
+ builder_liteethmaccrc32inserter_next_state <= 1'd0;
+ end
+ end
+ main_liteethmaccrc32inserter_is_ongoing1 <= 1'd1;
+ end
+ default: begin
+ main_liteethmaccrc32inserter_reset <= 1'd1;
+ main_liteethmaccrc32inserter_sink_ready <= 1'd1;
+ if (main_liteethmaccrc32inserter_sink_valid) begin
+ main_liteethmaccrc32inserter_sink_ready <= 1'd0;
+ builder_liteethmaccrc32inserter_next_state <= 1'd1;
+ end
+ main_liteethmaccrc32inserter_is_ongoing0 <= 1'd1;
+ end
+ endcase
+end
+assign main_crc32_inserter_sink_ready = ((~main_crc32_inserter_source_valid) | main_crc32_inserter_source_ready);
+assign main_liteethmaccrc32checker_fifo_full = (main_liteethmaccrc32checker_syncfifo_level == 3'd4);
+assign main_liteethmaccrc32checker_fifo_in = (main_liteethmaccrc32checker_sink_sink_valid & ((~main_liteethmaccrc32checker_fifo_full) | main_liteethmaccrc32checker_fifo_out));
+assign main_liteethmaccrc32checker_fifo_out = (main_liteethmaccrc32checker_source_source_valid & main_liteethmaccrc32checker_source_source_ready);
+assign main_liteethmaccrc32checker_syncfifo_sink_first = main_liteethmaccrc32checker_sink_sink_first;
+assign main_liteethmaccrc32checker_syncfifo_sink_last = main_liteethmaccrc32checker_sink_sink_last;
+assign main_liteethmaccrc32checker_syncfifo_sink_payload_data = main_liteethmaccrc32checker_sink_sink_payload_data;
+assign main_liteethmaccrc32checker_syncfifo_sink_payload_last_be = main_liteethmaccrc32checker_sink_sink_payload_last_be;
+assign main_liteethmaccrc32checker_syncfifo_sink_payload_error = main_liteethmaccrc32checker_sink_sink_payload_error;
+always @(*) begin
+ main_liteethmaccrc32checker_syncfifo_sink_valid <= 1'd0;
+ main_liteethmaccrc32checker_syncfifo_sink_valid <= main_liteethmaccrc32checker_sink_sink_valid;
+ main_liteethmaccrc32checker_syncfifo_sink_valid <= main_liteethmaccrc32checker_fifo_in;
+end
+always @(*) begin
+ main_liteethmaccrc32checker_sink_sink_ready <= 1'd0;
+ main_liteethmaccrc32checker_sink_sink_ready <= main_liteethmaccrc32checker_syncfifo_sink_ready;
+ main_liteethmaccrc32checker_sink_sink_ready <= main_liteethmaccrc32checker_fifo_in;
+end
+assign main_liteethmaccrc32checker_source_source_valid = (main_liteethmaccrc32checker_sink_sink_valid & main_liteethmaccrc32checker_fifo_full);
+assign main_liteethmaccrc32checker_source_source_last = main_liteethmaccrc32checker_sink_sink_last;
+assign main_liteethmaccrc32checker_syncfifo_source_ready = main_liteethmaccrc32checker_fifo_out;
+assign main_liteethmaccrc32checker_source_source_payload_data = main_liteethmaccrc32checker_syncfifo_source_payload_data;
+assign main_liteethmaccrc32checker_source_source_payload_last_be = main_liteethmaccrc32checker_syncfifo_source_payload_last_be;
+always @(*) begin
+ main_liteethmaccrc32checker_source_source_payload_error <= 1'd0;
+ main_liteethmaccrc32checker_source_source_payload_error <= main_liteethmaccrc32checker_syncfifo_source_payload_error;
+ main_liteethmaccrc32checker_source_source_payload_error <= (main_liteethmaccrc32checker_sink_sink_payload_error | main_liteethmaccrc32checker_crc_error);
+end
+assign main_liteethmaccrc32checker_error = ((main_liteethmaccrc32checker_source_source_valid & main_liteethmaccrc32checker_source_source_last) & main_liteethmaccrc32checker_crc_error);
+assign main_liteethmaccrc32checker_crc_data0 = main_liteethmaccrc32checker_sink_sink_payload_data;
+assign main_liteethmaccrc32checker_sink_sink_valid = main_crc32_checker_source_valid;
+assign main_crc32_checker_source_ready = main_liteethmaccrc32checker_sink_sink_ready;
+assign main_liteethmaccrc32checker_sink_sink_first = main_crc32_checker_source_first;
+assign main_liteethmaccrc32checker_sink_sink_last = main_crc32_checker_source_last;
+assign main_liteethmaccrc32checker_sink_sink_payload_data = main_crc32_checker_source_payload_data;
+assign main_liteethmaccrc32checker_sink_sink_payload_last_be = main_crc32_checker_source_payload_last_be;
+assign main_liteethmaccrc32checker_sink_sink_payload_error = main_crc32_checker_source_payload_error;
+assign main_liteethmaccrc32checker_crc_data1 = main_liteethmaccrc32checker_crc_data0;
+assign main_liteethmaccrc32checker_crc_last = main_liteethmaccrc32checker_crc_reg;
+assign main_liteethmaccrc32checker_crc_value = (~{main_liteethmaccrc32checker_crc_reg[0], main_liteethmaccrc32checker_crc_reg[1], main_liteethmaccrc32checker_crc_reg[2], main_liteethmaccrc32checker_crc_reg[3], main_liteethmaccrc32checker_crc_reg[4], main_liteethmaccrc32checker_crc_reg[5], main_liteethmaccrc32checker_crc_reg[6], main_liteethmaccrc32checker_crc_reg[7], main_liteethmaccrc32checker_crc_reg[8], main_liteethmaccrc32checker_crc_reg[9], main_liteethmaccrc32checker_crc_reg[10], main_liteethmaccrc32checker_crc_reg[11], main_liteethmaccrc32checker_crc_reg[12], main_liteethmaccrc32checker_crc_reg[13], main_liteethmaccrc32checker_crc_reg[14], main_liteethmaccrc32checker_crc_reg[15], main_liteethmaccrc32checker_crc_reg[16], main_liteethmaccrc32checker_crc_reg[17], main_liteethmaccrc32checker_crc_reg[18], main_liteethmaccrc32checker_crc_reg[19], main_liteethmaccrc32checker_crc_reg[20], main_liteethmaccrc32checker_crc_reg[21], main_liteethmaccrc32checker_crc_reg[22], main_liteethmaccrc32checker_crc_reg[23], main_liteethmaccrc32checker_crc_reg[24], main_liteethmaccrc32checker_crc_reg[25], main_liteethmaccrc32checker_crc_reg[26], main_liteethmaccrc32checker_crc_reg[27], main_liteethmaccrc32checker_crc_reg[28], main_liteethmaccrc32checker_crc_reg[29], main_liteethmaccrc32checker_crc_reg[30], main_liteethmaccrc32checker_crc_reg[31]});
+assign main_liteethmaccrc32checker_crc_error = (main_liteethmaccrc32checker_crc_next != 32'd3338984827);
+always @(*) begin
+ main_liteethmaccrc32checker_crc_next <= 32'd0;
+ main_liteethmaccrc32checker_crc_next[0] <= (((main_liteethmaccrc32checker_crc_last[24] ^ main_liteethmaccrc32checker_crc_last[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_data1[7]);
+ main_liteethmaccrc32checker_crc_next[1] <= (((((((main_liteethmaccrc32checker_crc_last[25] ^ main_liteethmaccrc32checker_crc_last[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_data1[6]) ^ main_liteethmaccrc32checker_crc_last[24]) ^ main_liteethmaccrc32checker_crc_last[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_data1[7]);
+ main_liteethmaccrc32checker_crc_next[2] <= (((((((((main_liteethmaccrc32checker_crc_last[26] ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_last[25]) ^ main_liteethmaccrc32checker_crc_last[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_data1[6]) ^ main_liteethmaccrc32checker_crc_last[24]) ^ main_liteethmaccrc32checker_crc_last[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_data1[7]);
+ main_liteethmaccrc32checker_crc_next[3] <= (((((((main_liteethmaccrc32checker_crc_last[27] ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_last[26]) ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_last[25]) ^ main_liteethmaccrc32checker_crc_last[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_data1[6]);
+ main_liteethmaccrc32checker_crc_next[4] <= (((((((((main_liteethmaccrc32checker_crc_last[28] ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_last[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_last[26]) ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_last[24]) ^ main_liteethmaccrc32checker_crc_last[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_data1[7]);
+ main_liteethmaccrc32checker_crc_next[5] <= (((((((((((((main_liteethmaccrc32checker_crc_last[29] ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_last[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_last[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_last[25]) ^ main_liteethmaccrc32checker_crc_last[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_data1[6]) ^ main_liteethmaccrc32checker_crc_last[24]) ^ main_liteethmaccrc32checker_crc_last[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_data1[7]);
+ main_liteethmaccrc32checker_crc_next[6] <= (((((((((((main_liteethmaccrc32checker_crc_last[30] ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_last[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_last[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_last[26]) ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_last[25]) ^ main_liteethmaccrc32checker_crc_last[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_data1[6]);
+ main_liteethmaccrc32checker_crc_next[7] <= (((((((((main_liteethmaccrc32checker_crc_last[31] ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_last[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_last[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_last[26]) ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_last[24]) ^ main_liteethmaccrc32checker_crc_data1[7]);
+ main_liteethmaccrc32checker_crc_next[8] <= ((((((((main_liteethmaccrc32checker_crc_last[0] ^ main_liteethmaccrc32checker_crc_last[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_last[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_last[25]) ^ main_liteethmaccrc32checker_crc_data1[6]) ^ main_liteethmaccrc32checker_crc_last[24]) ^ main_liteethmaccrc32checker_crc_data1[7]);
+ main_liteethmaccrc32checker_crc_next[9] <= ((((((((main_liteethmaccrc32checker_crc_last[1] ^ main_liteethmaccrc32checker_crc_last[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_last[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_last[26]) ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_last[25]) ^ main_liteethmaccrc32checker_crc_data1[6]);
+ main_liteethmaccrc32checker_crc_next[10] <= ((((((((main_liteethmaccrc32checker_crc_last[2] ^ main_liteethmaccrc32checker_crc_last[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_last[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_last[26]) ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_last[24]) ^ main_liteethmaccrc32checker_crc_data1[7]);
+ main_liteethmaccrc32checker_crc_next[11] <= ((((((((main_liteethmaccrc32checker_crc_last[3] ^ main_liteethmaccrc32checker_crc_last[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_last[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_last[25]) ^ main_liteethmaccrc32checker_crc_data1[6]) ^ main_liteethmaccrc32checker_crc_last[24]) ^ main_liteethmaccrc32checker_crc_data1[7]);
+ main_liteethmaccrc32checker_crc_next[12] <= ((((((((((((main_liteethmaccrc32checker_crc_last[4] ^ main_liteethmaccrc32checker_crc_last[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_last[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_last[26]) ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_last[25]) ^ main_liteethmaccrc32checker_crc_data1[6]) ^ main_liteethmaccrc32checker_crc_last[24]) ^ main_liteethmaccrc32checker_crc_last[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_data1[7]);
+ main_liteethmaccrc32checker_crc_next[13] <= ((((((((((((main_liteethmaccrc32checker_crc_last[5] ^ main_liteethmaccrc32checker_crc_last[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_last[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_last[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_last[26]) ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_last[25]) ^ main_liteethmaccrc32checker_crc_last[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_data1[6]);
+ main_liteethmaccrc32checker_crc_next[14] <= ((((((((((main_liteethmaccrc32checker_crc_last[6] ^ main_liteethmaccrc32checker_crc_last[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_last[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_last[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_last[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_last[26]) ^ main_liteethmaccrc32checker_crc_data1[5]);
+ main_liteethmaccrc32checker_crc_next[15] <= ((((((((main_liteethmaccrc32checker_crc_last[7] ^ main_liteethmaccrc32checker_crc_last[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_last[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_last[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_last[27]) ^ main_liteethmaccrc32checker_crc_data1[4]);
+ main_liteethmaccrc32checker_crc_next[16] <= ((((((main_liteethmaccrc32checker_crc_last[8] ^ main_liteethmaccrc32checker_crc_last[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_last[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_last[24]) ^ main_liteethmaccrc32checker_crc_data1[7]);
+ main_liteethmaccrc32checker_crc_next[17] <= ((((((main_liteethmaccrc32checker_crc_last[9] ^ main_liteethmaccrc32checker_crc_last[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_last[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_last[25]) ^ main_liteethmaccrc32checker_crc_data1[6]);
+ main_liteethmaccrc32checker_crc_next[18] <= ((((((main_liteethmaccrc32checker_crc_last[10] ^ main_liteethmaccrc32checker_crc_last[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_last[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_last[26]) ^ main_liteethmaccrc32checker_crc_data1[5]);
+ main_liteethmaccrc32checker_crc_next[19] <= ((((main_liteethmaccrc32checker_crc_last[11] ^ main_liteethmaccrc32checker_crc_last[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_last[27]) ^ main_liteethmaccrc32checker_crc_data1[4]);
+ main_liteethmaccrc32checker_crc_next[20] <= ((main_liteethmaccrc32checker_crc_last[12] ^ main_liteethmaccrc32checker_crc_last[28]) ^ main_liteethmaccrc32checker_crc_data1[3]);
+ main_liteethmaccrc32checker_crc_next[21] <= ((main_liteethmaccrc32checker_crc_last[13] ^ main_liteethmaccrc32checker_crc_last[29]) ^ main_liteethmaccrc32checker_crc_data1[2]);
+ main_liteethmaccrc32checker_crc_next[22] <= ((main_liteethmaccrc32checker_crc_last[14] ^ main_liteethmaccrc32checker_crc_last[24]) ^ main_liteethmaccrc32checker_crc_data1[7]);
+ main_liteethmaccrc32checker_crc_next[23] <= ((((((main_liteethmaccrc32checker_crc_last[15] ^ main_liteethmaccrc32checker_crc_last[25]) ^ main_liteethmaccrc32checker_crc_data1[6]) ^ main_liteethmaccrc32checker_crc_last[24]) ^ main_liteethmaccrc32checker_crc_last[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_data1[7]);
+ main_liteethmaccrc32checker_crc_next[24] <= ((((((main_liteethmaccrc32checker_crc_last[16] ^ main_liteethmaccrc32checker_crc_last[26]) ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_last[25]) ^ main_liteethmaccrc32checker_crc_last[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_data1[6]);
+ main_liteethmaccrc32checker_crc_next[25] <= ((((main_liteethmaccrc32checker_crc_last[17] ^ main_liteethmaccrc32checker_crc_last[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_last[26]) ^ main_liteethmaccrc32checker_crc_data1[5]);
+ main_liteethmaccrc32checker_crc_next[26] <= ((((((((main_liteethmaccrc32checker_crc_last[18] ^ main_liteethmaccrc32checker_crc_last[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_last[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_last[24]) ^ main_liteethmaccrc32checker_crc_last[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_data1[7]);
+ main_liteethmaccrc32checker_crc_next[27] <= ((((((((main_liteethmaccrc32checker_crc_last[19] ^ main_liteethmaccrc32checker_crc_last[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_last[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_last[25]) ^ main_liteethmaccrc32checker_crc_last[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_data1[6]);
+ main_liteethmaccrc32checker_crc_next[28] <= ((((((main_liteethmaccrc32checker_crc_last[20] ^ main_liteethmaccrc32checker_crc_last[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_last[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_last[26]) ^ main_liteethmaccrc32checker_crc_data1[5]);
+ main_liteethmaccrc32checker_crc_next[29] <= ((((((main_liteethmaccrc32checker_crc_last[21] ^ main_liteethmaccrc32checker_crc_last[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_last[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_last[27]) ^ main_liteethmaccrc32checker_crc_data1[4]);
+ main_liteethmaccrc32checker_crc_next[30] <= ((((main_liteethmaccrc32checker_crc_last[22] ^ main_liteethmaccrc32checker_crc_last[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_last[28]) ^ main_liteethmaccrc32checker_crc_data1[3]);
+ main_liteethmaccrc32checker_crc_next[31] <= ((main_liteethmaccrc32checker_crc_last[23] ^ main_liteethmaccrc32checker_crc_last[29]) ^ main_liteethmaccrc32checker_crc_data1[2]);
+end
+assign main_liteethmaccrc32checker_syncfifo_syncfifo_din = {main_liteethmaccrc32checker_syncfifo_fifo_in_last, main_liteethmaccrc32checker_syncfifo_fifo_in_first, main_liteethmaccrc32checker_syncfifo_fifo_in_payload_error, main_liteethmaccrc32checker_syncfifo_fifo_in_payload_last_be, main_liteethmaccrc32checker_syncfifo_fifo_in_payload_data};
+assign {main_liteethmaccrc32checker_syncfifo_fifo_out_last, main_liteethmaccrc32checker_syncfifo_fifo_out_first, main_liteethmaccrc32checker_syncfifo_fifo_out_payload_error, main_liteethmaccrc32checker_syncfifo_fifo_out_payload_last_be, main_liteethmaccrc32checker_syncfifo_fifo_out_payload_data} = main_liteethmaccrc32checker_syncfifo_syncfifo_dout;
+assign main_liteethmaccrc32checker_syncfifo_sink_ready = main_liteethmaccrc32checker_syncfifo_syncfifo_writable;
+assign main_liteethmaccrc32checker_syncfifo_syncfifo_we = main_liteethmaccrc32checker_syncfifo_sink_valid;
+assign main_liteethmaccrc32checker_syncfifo_fifo_in_first = main_liteethmaccrc32checker_syncfifo_sink_first;
+assign main_liteethmaccrc32checker_syncfifo_fifo_in_last = main_liteethmaccrc32checker_syncfifo_sink_last;
+assign main_liteethmaccrc32checker_syncfifo_fifo_in_payload_data = main_liteethmaccrc32checker_syncfifo_sink_payload_data;
+assign main_liteethmaccrc32checker_syncfifo_fifo_in_payload_last_be = main_liteethmaccrc32checker_syncfifo_sink_payload_last_be;
+assign main_liteethmaccrc32checker_syncfifo_fifo_in_payload_error = main_liteethmaccrc32checker_syncfifo_sink_payload_error;
+assign main_liteethmaccrc32checker_syncfifo_source_valid = main_liteethmaccrc32checker_syncfifo_syncfifo_readable;
+assign main_liteethmaccrc32checker_syncfifo_source_first = main_liteethmaccrc32checker_syncfifo_fifo_out_first;
+assign main_liteethmaccrc32checker_syncfifo_source_last = main_liteethmaccrc32checker_syncfifo_fifo_out_last;
+assign main_liteethmaccrc32checker_syncfifo_source_payload_data = main_liteethmaccrc32checker_syncfifo_fifo_out_payload_data;
+assign main_liteethmaccrc32checker_syncfifo_source_payload_last_be = main_liteethmaccrc32checker_syncfifo_fifo_out_payload_last_be;
+assign main_liteethmaccrc32checker_syncfifo_source_payload_error = main_liteethmaccrc32checker_syncfifo_fifo_out_payload_error;
+assign main_liteethmaccrc32checker_syncfifo_syncfifo_re = main_liteethmaccrc32checker_syncfifo_source_ready;
+always @(*) begin
+ main_liteethmaccrc32checker_syncfifo_wrport_adr <= 3'd0;
+ if (main_liteethmaccrc32checker_syncfifo_replace) begin
+ main_liteethmaccrc32checker_syncfifo_wrport_adr <= (main_liteethmaccrc32checker_syncfifo_produce - 1'd1);
+ end else begin
+ main_liteethmaccrc32checker_syncfifo_wrport_adr <= main_liteethmaccrc32checker_syncfifo_produce;
+ end
+end
+assign main_liteethmaccrc32checker_syncfifo_wrport_dat_w = main_liteethmaccrc32checker_syncfifo_syncfifo_din;
+assign main_liteethmaccrc32checker_syncfifo_wrport_we = (main_liteethmaccrc32checker_syncfifo_syncfifo_we & (main_liteethmaccrc32checker_syncfifo_syncfifo_writable | main_liteethmaccrc32checker_syncfifo_replace));
+assign main_liteethmaccrc32checker_syncfifo_do_read = (main_liteethmaccrc32checker_syncfifo_syncfifo_readable & main_liteethmaccrc32checker_syncfifo_syncfifo_re);
+assign main_liteethmaccrc32checker_syncfifo_rdport_adr = main_liteethmaccrc32checker_syncfifo_consume;
+assign main_liteethmaccrc32checker_syncfifo_syncfifo_dout = main_liteethmaccrc32checker_syncfifo_rdport_dat_r;
+assign main_liteethmaccrc32checker_syncfifo_syncfifo_writable = (main_liteethmaccrc32checker_syncfifo_level != 3'd5);
+assign main_liteethmaccrc32checker_syncfifo_syncfifo_readable = (main_liteethmaccrc32checker_syncfifo_level != 1'd0);
+always @(*) begin
+ main_liteethmaccrc32checker_crc_reset <= 1'd0;
+ builder_liteethmaccrc32checker_next_state <= 2'd0;
+ main_liteethmaccrc32checker_fifo_reset <= 1'd0;
+ main_liteethmaccrc32checker_crc_ce <= 1'd0;
+ builder_liteethmaccrc32checker_next_state <= builder_liteethmaccrc32checker_state;
+ case (builder_liteethmaccrc32checker_state)
+ 1'd1: begin
+ if ((main_liteethmaccrc32checker_sink_sink_valid & main_liteethmaccrc32checker_sink_sink_ready)) begin
+ main_liteethmaccrc32checker_crc_ce <= 1'd1;
+ builder_liteethmaccrc32checker_next_state <= 2'd2;
+ end
+ end
+ 2'd2: begin
+ if ((main_liteethmaccrc32checker_sink_sink_valid & main_liteethmaccrc32checker_sink_sink_ready)) begin
+ main_liteethmaccrc32checker_crc_ce <= 1'd1;
+ if (main_liteethmaccrc32checker_sink_sink_last) begin
+ builder_liteethmaccrc32checker_next_state <= 1'd0;
+ end
+ end
+ end
+ default: begin
+ main_liteethmaccrc32checker_crc_reset <= 1'd1;
+ main_liteethmaccrc32checker_fifo_reset <= 1'd1;
+ builder_liteethmaccrc32checker_next_state <= 1'd1;
+ end
+ endcase
+end
+assign main_crc32_checker_sink_ready = ((~main_crc32_checker_source_valid) | main_crc32_checker_source_ready);
+assign main_ps_preamble_error_o = (main_ps_preamble_error_toggle_o ^ main_ps_preamble_error_toggle_o_r);
+assign main_ps_crc_error_o = (main_ps_crc_error_toggle_o ^ main_ps_crc_error_toggle_o_r);
+assign main_padding_inserter_counter_done = (main_padding_inserter_counter >= 6'd59);
+always @(*) begin
+ main_padding_inserter_sink_ready <= 1'd0;
+ main_padding_inserter_counter_liteethmacpaddinginserter_next_value <= 16'd0;
+ main_padding_inserter_source_valid <= 1'd0;
+ main_padding_inserter_counter_liteethmacpaddinginserter_next_value_ce <= 1'd0;
+ main_padding_inserter_source_first <= 1'd0;
+ main_padding_inserter_source_last <= 1'd0;
+ builder_liteethmacpaddinginserter_next_state <= 1'd0;
+ main_padding_inserter_source_payload_data <= 8'd0;
+ main_padding_inserter_source_payload_last_be <= 1'd0;
+ main_padding_inserter_source_payload_error <= 1'd0;
+ builder_liteethmacpaddinginserter_next_state <= builder_liteethmacpaddinginserter_state;
+ case (builder_liteethmacpaddinginserter_state)
+ 1'd1: begin
+ main_padding_inserter_source_valid <= 1'd1;
+ main_padding_inserter_source_last <= main_padding_inserter_counter_done;
+ main_padding_inserter_source_payload_data <= 1'd0;
+ if ((main_padding_inserter_source_valid & main_padding_inserter_source_ready)) begin
+ main_padding_inserter_counter_liteethmacpaddinginserter_next_value <= (main_padding_inserter_counter + 1'd1);
+ main_padding_inserter_counter_liteethmacpaddinginserter_next_value_ce <= 1'd1;
+ if (main_padding_inserter_counter_done) begin
+ main_padding_inserter_counter_liteethmacpaddinginserter_next_value <= 1'd0;
+ main_padding_inserter_counter_liteethmacpaddinginserter_next_value_ce <= 1'd1;
+ builder_liteethmacpaddinginserter_next_state <= 1'd0;
+ end
+ end
+ end
+ default: begin
+ main_padding_inserter_source_valid <= main_padding_inserter_sink_valid;
+ main_padding_inserter_sink_ready <= main_padding_inserter_source_ready;
+ main_padding_inserter_source_first <= main_padding_inserter_sink_first;
+ main_padding_inserter_source_last <= main_padding_inserter_sink_last;
+ main_padding_inserter_source_payload_data <= main_padding_inserter_sink_payload_data;
+ main_padding_inserter_source_payload_last_be <= main_padding_inserter_sink_payload_last_be;
+ main_padding_inserter_source_payload_error <= main_padding_inserter_sink_payload_error;
+ if ((main_padding_inserter_source_valid & main_padding_inserter_source_ready)) begin
+ main_padding_inserter_counter_liteethmacpaddinginserter_next_value <= (main_padding_inserter_counter + 1'd1);
+ main_padding_inserter_counter_liteethmacpaddinginserter_next_value_ce <= 1'd1;
+ if (main_padding_inserter_sink_last) begin
+ if ((~main_padding_inserter_counter_done)) begin
+ main_padding_inserter_source_last <= 1'd0;
+ builder_liteethmacpaddinginserter_next_state <= 1'd1;
+ end else begin
+ main_padding_inserter_counter_liteethmacpaddinginserter_next_value <= 1'd0;
+ main_padding_inserter_counter_liteethmacpaddinginserter_next_value_ce <= 1'd1;
+ end
+ end
+ end
+ end
+ endcase
+end
+assign main_padding_checker_source_valid = main_padding_checker_sink_valid;
+assign main_padding_checker_sink_ready = main_padding_checker_source_ready;
+assign main_padding_checker_source_first = main_padding_checker_sink_first;
+assign main_padding_checker_source_last = main_padding_checker_sink_last;
+assign main_padding_checker_source_payload_data = main_padding_checker_sink_payload_data;
+assign main_padding_checker_source_payload_last_be = main_padding_checker_sink_payload_last_be;
+assign main_padding_checker_source_payload_error = main_padding_checker_sink_payload_error;
+always @(*) begin
+ main_tx_last_be_source_payload_error <= 1'd0;
+ main_tx_last_be_source_valid <= 1'd0;
+ main_tx_last_be_source_last <= 1'd0;
+ main_tx_last_be_sink_ready <= 1'd0;
+ main_tx_last_be_source_first <= 1'd0;
+ builder_liteethmactxlastbe_next_state <= 1'd0;
+ main_tx_last_be_source_payload_data <= 8'd0;
+ builder_liteethmactxlastbe_next_state <= builder_liteethmactxlastbe_state;
+ case (builder_liteethmactxlastbe_state)
+ 1'd1: begin
+ main_tx_last_be_sink_ready <= 1'd1;
+ if ((main_tx_last_be_sink_valid & main_tx_last_be_sink_last)) begin
+ builder_liteethmactxlastbe_next_state <= 1'd0;
+ end
+ end
+ default: begin
+ main_tx_last_be_source_valid <= main_tx_last_be_sink_valid;
+ main_tx_last_be_sink_ready <= main_tx_last_be_source_ready;
+ main_tx_last_be_source_first <= main_tx_last_be_sink_first;
+ main_tx_last_be_source_payload_data <= main_tx_last_be_sink_payload_data;
+ main_tx_last_be_source_payload_error <= main_tx_last_be_sink_payload_error;
+ main_tx_last_be_source_last <= main_tx_last_be_sink_payload_last_be;
+ if ((main_tx_last_be_sink_valid & main_tx_last_be_sink_ready)) begin
+ if ((main_tx_last_be_sink_payload_last_be & (~main_tx_last_be_sink_last))) begin
+ builder_liteethmactxlastbe_next_state <= 1'd1;
+ end
+ end
+ end
+ endcase
+end
+assign main_rx_last_be_source_valid = main_rx_last_be_sink_valid;
+assign main_rx_last_be_sink_ready = main_rx_last_be_source_ready;
+assign main_rx_last_be_source_first = main_rx_last_be_sink_first;
+assign main_rx_last_be_source_last = main_rx_last_be_sink_last;
+assign main_rx_last_be_source_payload_data = main_rx_last_be_sink_payload_data;
+assign main_rx_last_be_source_payload_error = main_rx_last_be_sink_payload_error;
+always @(*) begin
+ main_rx_last_be_source_payload_last_be <= 1'd0;
+ main_rx_last_be_source_payload_last_be <= main_rx_last_be_sink_payload_last_be;
+ main_rx_last_be_source_payload_last_be <= main_rx_last_be_sink_last;
+end
+assign main_tx_converter_converter_sink_valid = main_tx_converter_sink_valid;
+assign main_tx_converter_converter_sink_first = main_tx_converter_sink_first;
+assign main_tx_converter_converter_sink_last = main_tx_converter_sink_last;
+assign main_tx_converter_sink_ready = main_tx_converter_converter_sink_ready;
+always @(*) begin
+ main_tx_converter_converter_sink_payload_data <= 40'd0;
+ main_tx_converter_converter_sink_payload_data[7:0] <= main_tx_converter_sink_payload_data[7:0];
+ main_tx_converter_converter_sink_payload_data[8] <= main_tx_converter_sink_payload_last_be[0];
+ main_tx_converter_converter_sink_payload_data[9] <= main_tx_converter_sink_payload_error[0];
+ main_tx_converter_converter_sink_payload_data[17:10] <= main_tx_converter_sink_payload_data[15:8];
+ main_tx_converter_converter_sink_payload_data[18] <= main_tx_converter_sink_payload_last_be[1];
+ main_tx_converter_converter_sink_payload_data[19] <= main_tx_converter_sink_payload_error[1];
+ main_tx_converter_converter_sink_payload_data[27:20] <= main_tx_converter_sink_payload_data[23:16];
+ main_tx_converter_converter_sink_payload_data[28] <= main_tx_converter_sink_payload_last_be[2];
+ main_tx_converter_converter_sink_payload_data[29] <= main_tx_converter_sink_payload_error[2];
+ main_tx_converter_converter_sink_payload_data[37:30] <= main_tx_converter_sink_payload_data[31:24];
+ main_tx_converter_converter_sink_payload_data[38] <= main_tx_converter_sink_payload_last_be[3];
+ main_tx_converter_converter_sink_payload_data[39] <= main_tx_converter_sink_payload_error[3];
+end
+assign main_tx_converter_source_valid = main_tx_converter_source_source_valid;
+assign main_tx_converter_source_first = main_tx_converter_source_source_first;
+assign main_tx_converter_source_last = main_tx_converter_source_source_last;
+assign main_tx_converter_source_source_ready = main_tx_converter_source_ready;
+assign {main_tx_converter_source_payload_error, main_tx_converter_source_payload_last_be, main_tx_converter_source_payload_data} = main_tx_converter_source_source_payload_data;
+assign main_tx_converter_source_source_valid = main_tx_converter_converter_source_valid;
+assign main_tx_converter_converter_source_ready = main_tx_converter_source_source_ready;
+assign main_tx_converter_source_source_first = main_tx_converter_converter_source_first;
+assign main_tx_converter_source_source_last = main_tx_converter_converter_source_last;
+assign main_tx_converter_source_source_payload_data = main_tx_converter_converter_source_payload_data;
+assign main_tx_converter_converter_first = (main_tx_converter_converter_mux == 1'd0);
+assign main_tx_converter_converter_last = (main_tx_converter_converter_mux == 2'd3);
+assign main_tx_converter_converter_source_valid = main_tx_converter_converter_sink_valid;
+assign main_tx_converter_converter_source_first = (main_tx_converter_converter_sink_first & main_tx_converter_converter_first);
+assign main_tx_converter_converter_source_last = (main_tx_converter_converter_sink_last & main_tx_converter_converter_last);
+assign main_tx_converter_converter_sink_ready = (main_tx_converter_converter_last & main_tx_converter_converter_source_ready);
+always @(*) begin
+ main_tx_converter_converter_source_payload_data <= 10'd0;
+ case (main_tx_converter_converter_mux)
+ 1'd0: begin
+ main_tx_converter_converter_source_payload_data <= main_tx_converter_converter_sink_payload_data[9:0];
+ end
+ 1'd1: begin
+ main_tx_converter_converter_source_payload_data <= main_tx_converter_converter_sink_payload_data[19:10];
+ end
+ 2'd2: begin
+ main_tx_converter_converter_source_payload_data <= main_tx_converter_converter_sink_payload_data[29:20];
+ end
+ default: begin
+ main_tx_converter_converter_source_payload_data <= main_tx_converter_converter_sink_payload_data[39:30];
+ end
+ endcase
+end
+assign main_tx_converter_converter_source_payload_valid_token_count = main_tx_converter_converter_last;
+assign main_rx_converter_converter_sink_valid = main_rx_converter_sink_valid;
+assign main_rx_converter_converter_sink_first = main_rx_converter_sink_first;
+assign main_rx_converter_converter_sink_last = main_rx_converter_sink_last;
+assign main_rx_converter_sink_ready = main_rx_converter_converter_sink_ready;
+assign main_rx_converter_converter_sink_payload_data = {main_rx_converter_sink_payload_error, main_rx_converter_sink_payload_last_be, main_rx_converter_sink_payload_data};
+assign main_rx_converter_source_valid = main_rx_converter_source_source_valid;
+assign main_rx_converter_source_first = main_rx_converter_source_source_first;
+assign main_rx_converter_source_last = main_rx_converter_source_source_last;
+assign main_rx_converter_source_source_ready = main_rx_converter_source_ready;
+always @(*) begin
+ main_rx_converter_source_payload_data <= 32'd0;
+ main_rx_converter_source_payload_data[7:0] <= main_rx_converter_source_source_payload_data[7:0];
+ main_rx_converter_source_payload_data[15:8] <= main_rx_converter_source_source_payload_data[17:10];
+ main_rx_converter_source_payload_data[23:16] <= main_rx_converter_source_source_payload_data[27:20];
+ main_rx_converter_source_payload_data[31:24] <= main_rx_converter_source_source_payload_data[37:30];
+end
+always @(*) begin
+ main_rx_converter_source_payload_last_be <= 4'd0;
+ main_rx_converter_source_payload_last_be[0] <= main_rx_converter_source_source_payload_data[8];
+ main_rx_converter_source_payload_last_be[1] <= main_rx_converter_source_source_payload_data[18];
+ main_rx_converter_source_payload_last_be[2] <= main_rx_converter_source_source_payload_data[28];
+ main_rx_converter_source_payload_last_be[3] <= main_rx_converter_source_source_payload_data[38];
+end
+always @(*) begin
+ main_rx_converter_source_payload_error <= 4'd0;
+ main_rx_converter_source_payload_error[0] <= main_rx_converter_source_source_payload_data[9];
+ main_rx_converter_source_payload_error[1] <= main_rx_converter_source_source_payload_data[19];
+ main_rx_converter_source_payload_error[2] <= main_rx_converter_source_source_payload_data[29];
+ main_rx_converter_source_payload_error[3] <= main_rx_converter_source_source_payload_data[39];
+end
+assign main_rx_converter_source_source_valid = main_rx_converter_converter_source_valid;
+assign main_rx_converter_converter_source_ready = main_rx_converter_source_source_ready;
+assign main_rx_converter_source_source_first = main_rx_converter_converter_source_first;
+assign main_rx_converter_source_source_last = main_rx_converter_converter_source_last;
+assign main_rx_converter_source_source_payload_data = main_rx_converter_converter_source_payload_data;
+assign main_rx_converter_converter_sink_ready = ((~main_rx_converter_converter_strobe_all) | main_rx_converter_converter_source_ready);
+assign main_rx_converter_converter_source_valid = main_rx_converter_converter_strobe_all;
+assign main_rx_converter_converter_load_part = (main_rx_converter_converter_sink_valid & main_rx_converter_converter_sink_ready);
+assign main_tx_cdc_cdc_sink_valid = main_tx_cdc_sink_sink_valid;
+assign main_tx_cdc_sink_sink_ready = main_tx_cdc_cdc_sink_ready;
+assign main_tx_cdc_cdc_sink_first = main_tx_cdc_sink_sink_first;
+assign main_tx_cdc_cdc_sink_last = main_tx_cdc_sink_sink_last;
+assign main_tx_cdc_cdc_sink_payload_data = main_tx_cdc_sink_sink_payload_data;
+assign main_tx_cdc_cdc_sink_payload_last_be = main_tx_cdc_sink_sink_payload_last_be;
+assign main_tx_cdc_cdc_sink_payload_error = main_tx_cdc_sink_sink_payload_error;
+assign main_tx_cdc_source_source_valid = main_tx_cdc_cdc_source_valid;
+assign main_tx_cdc_cdc_source_ready = main_tx_cdc_source_source_ready;
+assign main_tx_cdc_source_source_first = main_tx_cdc_cdc_source_first;
+assign main_tx_cdc_source_source_last = main_tx_cdc_cdc_source_last;
+assign main_tx_cdc_source_source_payload_data = main_tx_cdc_cdc_source_payload_data;
+assign main_tx_cdc_source_source_payload_last_be = main_tx_cdc_cdc_source_payload_last_be;
+assign main_tx_cdc_source_source_payload_error = main_tx_cdc_cdc_source_payload_error;
+assign main_tx_cdc_cdc_asyncfifo_din = {main_tx_cdc_cdc_fifo_in_last, main_tx_cdc_cdc_fifo_in_first, main_tx_cdc_cdc_fifo_in_payload_error, main_tx_cdc_cdc_fifo_in_payload_last_be, main_tx_cdc_cdc_fifo_in_payload_data};
+assign {main_tx_cdc_cdc_fifo_out_last, main_tx_cdc_cdc_fifo_out_first, main_tx_cdc_cdc_fifo_out_payload_error, main_tx_cdc_cdc_fifo_out_payload_last_be, main_tx_cdc_cdc_fifo_out_payload_data} = main_tx_cdc_cdc_asyncfifo_dout;
+assign main_tx_cdc_cdc_sink_ready = main_tx_cdc_cdc_asyncfifo_writable;
+assign main_tx_cdc_cdc_asyncfifo_we = main_tx_cdc_cdc_sink_valid;
+assign main_tx_cdc_cdc_fifo_in_first = main_tx_cdc_cdc_sink_first;
+assign main_tx_cdc_cdc_fifo_in_last = main_tx_cdc_cdc_sink_last;
+assign main_tx_cdc_cdc_fifo_in_payload_data = main_tx_cdc_cdc_sink_payload_data;
+assign main_tx_cdc_cdc_fifo_in_payload_last_be = main_tx_cdc_cdc_sink_payload_last_be;
+assign main_tx_cdc_cdc_fifo_in_payload_error = main_tx_cdc_cdc_sink_payload_error;
+assign main_tx_cdc_cdc_source_valid = main_tx_cdc_cdc_asyncfifo_readable;
+assign main_tx_cdc_cdc_source_first = main_tx_cdc_cdc_fifo_out_first;
+assign main_tx_cdc_cdc_source_last = main_tx_cdc_cdc_fifo_out_last;
+assign main_tx_cdc_cdc_source_payload_data = main_tx_cdc_cdc_fifo_out_payload_data;
+assign main_tx_cdc_cdc_source_payload_last_be = main_tx_cdc_cdc_fifo_out_payload_last_be;
+assign main_tx_cdc_cdc_source_payload_error = main_tx_cdc_cdc_fifo_out_payload_error;
+assign main_tx_cdc_cdc_asyncfifo_re = main_tx_cdc_cdc_source_ready;
+assign main_tx_cdc_cdc_graycounter0_ce = (main_tx_cdc_cdc_asyncfifo_writable & main_tx_cdc_cdc_asyncfifo_we);
+assign main_tx_cdc_cdc_graycounter1_ce = (main_tx_cdc_cdc_asyncfifo_readable & main_tx_cdc_cdc_asyncfifo_re);
+assign main_tx_cdc_cdc_asyncfifo_writable = (((main_tx_cdc_cdc_graycounter0_q[5] == main_tx_cdc_cdc_consume_wdomain[5]) | (main_tx_cdc_cdc_graycounter0_q[4] == main_tx_cdc_cdc_consume_wdomain[4])) | (main_tx_cdc_cdc_graycounter0_q[3:0] != main_tx_cdc_cdc_consume_wdomain[3:0]));
+assign main_tx_cdc_cdc_asyncfifo_readable = (main_tx_cdc_cdc_graycounter1_q != main_tx_cdc_cdc_produce_rdomain);
+assign main_tx_cdc_cdc_wrport_adr = main_tx_cdc_cdc_graycounter0_q_binary[4:0];
+assign main_tx_cdc_cdc_wrport_dat_w = main_tx_cdc_cdc_asyncfifo_din;
+assign main_tx_cdc_cdc_wrport_we = main_tx_cdc_cdc_graycounter0_ce;
+assign main_tx_cdc_cdc_rdport_adr = main_tx_cdc_cdc_graycounter1_q_next_binary[4:0];
+assign main_tx_cdc_cdc_asyncfifo_dout = main_tx_cdc_cdc_rdport_dat_r;
+always @(*) begin
+ main_tx_cdc_cdc_graycounter0_q_next_binary <= 6'd0;
+ if (main_tx_cdc_cdc_graycounter0_ce) begin
+ main_tx_cdc_cdc_graycounter0_q_next_binary <= (main_tx_cdc_cdc_graycounter0_q_binary + 1'd1);
+ end else begin
+ main_tx_cdc_cdc_graycounter0_q_next_binary <= main_tx_cdc_cdc_graycounter0_q_binary;
+ end
+end
+assign main_tx_cdc_cdc_graycounter0_q_next = (main_tx_cdc_cdc_graycounter0_q_next_binary ^ main_tx_cdc_cdc_graycounter0_q_next_binary[5:1]);
+always @(*) begin
+ main_tx_cdc_cdc_graycounter1_q_next_binary <= 6'd0;
+ if (main_tx_cdc_cdc_graycounter1_ce) begin
+ main_tx_cdc_cdc_graycounter1_q_next_binary <= (main_tx_cdc_cdc_graycounter1_q_binary + 1'd1);
+ end else begin
+ main_tx_cdc_cdc_graycounter1_q_next_binary <= main_tx_cdc_cdc_graycounter1_q_binary;
+ end
+end
+assign main_tx_cdc_cdc_graycounter1_q_next = (main_tx_cdc_cdc_graycounter1_q_next_binary ^ main_tx_cdc_cdc_graycounter1_q_next_binary[5:1]);
+assign main_rx_cdc_cdc_sink_valid = main_rx_cdc_sink_sink_valid;
+assign main_rx_cdc_sink_sink_ready = main_rx_cdc_cdc_sink_ready;
+assign main_rx_cdc_cdc_sink_first = main_rx_cdc_sink_sink_first;
+assign main_rx_cdc_cdc_sink_last = main_rx_cdc_sink_sink_last;
+assign main_rx_cdc_cdc_sink_payload_data = main_rx_cdc_sink_sink_payload_data;
+assign main_rx_cdc_cdc_sink_payload_last_be = main_rx_cdc_sink_sink_payload_last_be;
+assign main_rx_cdc_cdc_sink_payload_error = main_rx_cdc_sink_sink_payload_error;
+assign main_rx_cdc_source_source_valid = main_rx_cdc_cdc_source_valid;
+assign main_rx_cdc_cdc_source_ready = main_rx_cdc_source_source_ready;
+assign main_rx_cdc_source_source_first = main_rx_cdc_cdc_source_first;
+assign main_rx_cdc_source_source_last = main_rx_cdc_cdc_source_last;
+assign main_rx_cdc_source_source_payload_data = main_rx_cdc_cdc_source_payload_data;
+assign main_rx_cdc_source_source_payload_last_be = main_rx_cdc_cdc_source_payload_last_be;
+assign main_rx_cdc_source_source_payload_error = main_rx_cdc_cdc_source_payload_error;
+assign main_rx_cdc_cdc_asyncfifo_din = {main_rx_cdc_cdc_fifo_in_last, main_rx_cdc_cdc_fifo_in_first, main_rx_cdc_cdc_fifo_in_payload_error, main_rx_cdc_cdc_fifo_in_payload_last_be, main_rx_cdc_cdc_fifo_in_payload_data};
+assign {main_rx_cdc_cdc_fifo_out_last, main_rx_cdc_cdc_fifo_out_first, main_rx_cdc_cdc_fifo_out_payload_error, main_rx_cdc_cdc_fifo_out_payload_last_be, main_rx_cdc_cdc_fifo_out_payload_data} = main_rx_cdc_cdc_asyncfifo_dout;
+assign main_rx_cdc_cdc_sink_ready = main_rx_cdc_cdc_asyncfifo_writable;
+assign main_rx_cdc_cdc_asyncfifo_we = main_rx_cdc_cdc_sink_valid;
+assign main_rx_cdc_cdc_fifo_in_first = main_rx_cdc_cdc_sink_first;
+assign main_rx_cdc_cdc_fifo_in_last = main_rx_cdc_cdc_sink_last;
+assign main_rx_cdc_cdc_fifo_in_payload_data = main_rx_cdc_cdc_sink_payload_data;
+assign main_rx_cdc_cdc_fifo_in_payload_last_be = main_rx_cdc_cdc_sink_payload_last_be;
+assign main_rx_cdc_cdc_fifo_in_payload_error = main_rx_cdc_cdc_sink_payload_error;
+assign main_rx_cdc_cdc_source_valid = main_rx_cdc_cdc_asyncfifo_readable;
+assign main_rx_cdc_cdc_source_first = main_rx_cdc_cdc_fifo_out_first;
+assign main_rx_cdc_cdc_source_last = main_rx_cdc_cdc_fifo_out_last;
+assign main_rx_cdc_cdc_source_payload_data = main_rx_cdc_cdc_fifo_out_payload_data;
+assign main_rx_cdc_cdc_source_payload_last_be = main_rx_cdc_cdc_fifo_out_payload_last_be;
+assign main_rx_cdc_cdc_source_payload_error = main_rx_cdc_cdc_fifo_out_payload_error;
+assign main_rx_cdc_cdc_asyncfifo_re = main_rx_cdc_cdc_source_ready;
+assign main_rx_cdc_cdc_graycounter0_ce = (main_rx_cdc_cdc_asyncfifo_writable & main_rx_cdc_cdc_asyncfifo_we);
+assign main_rx_cdc_cdc_graycounter1_ce = (main_rx_cdc_cdc_asyncfifo_readable & main_rx_cdc_cdc_asyncfifo_re);
+assign main_rx_cdc_cdc_asyncfifo_writable = (((main_rx_cdc_cdc_graycounter0_q[5] == main_rx_cdc_cdc_consume_wdomain[5]) | (main_rx_cdc_cdc_graycounter0_q[4] == main_rx_cdc_cdc_consume_wdomain[4])) | (main_rx_cdc_cdc_graycounter0_q[3:0] != main_rx_cdc_cdc_consume_wdomain[3:0]));
+assign main_rx_cdc_cdc_asyncfifo_readable = (main_rx_cdc_cdc_graycounter1_q != main_rx_cdc_cdc_produce_rdomain);
+assign main_rx_cdc_cdc_wrport_adr = main_rx_cdc_cdc_graycounter0_q_binary[4:0];
+assign main_rx_cdc_cdc_wrport_dat_w = main_rx_cdc_cdc_asyncfifo_din;
+assign main_rx_cdc_cdc_wrport_we = main_rx_cdc_cdc_graycounter0_ce;
+assign main_rx_cdc_cdc_rdport_adr = main_rx_cdc_cdc_graycounter1_q_next_binary[4:0];
+assign main_rx_cdc_cdc_asyncfifo_dout = main_rx_cdc_cdc_rdport_dat_r;
+always @(*) begin
+ main_rx_cdc_cdc_graycounter0_q_next_binary <= 6'd0;
+ if (main_rx_cdc_cdc_graycounter0_ce) begin
+ main_rx_cdc_cdc_graycounter0_q_next_binary <= (main_rx_cdc_cdc_graycounter0_q_binary + 1'd1);
+ end else begin
+ main_rx_cdc_cdc_graycounter0_q_next_binary <= main_rx_cdc_cdc_graycounter0_q_binary;
+ end
+end
+assign main_rx_cdc_cdc_graycounter0_q_next = (main_rx_cdc_cdc_graycounter0_q_next_binary ^ main_rx_cdc_cdc_graycounter0_q_next_binary[5:1]);
+always @(*) begin
+ main_rx_cdc_cdc_graycounter1_q_next_binary <= 6'd0;
+ if (main_rx_cdc_cdc_graycounter1_ce) begin
+ main_rx_cdc_cdc_graycounter1_q_next_binary <= (main_rx_cdc_cdc_graycounter1_q_binary + 1'd1);
+ end else begin
+ main_rx_cdc_cdc_graycounter1_q_next_binary <= main_rx_cdc_cdc_graycounter1_q_binary;
+ end
+end
+assign main_rx_cdc_cdc_graycounter1_q_next = (main_rx_cdc_cdc_graycounter1_q_next_binary ^ main_rx_cdc_cdc_graycounter1_q_next_binary[5:1]);
+assign main_tx_converter_sink_valid = main_tx_cdc_source_source_valid;
+assign main_tx_cdc_source_source_ready = main_tx_converter_sink_ready;
+assign main_tx_converter_sink_first = main_tx_cdc_source_source_first;
+assign main_tx_converter_sink_last = main_tx_cdc_source_source_last;
+assign main_tx_converter_sink_payload_data = main_tx_cdc_source_source_payload_data;
+assign main_tx_converter_sink_payload_last_be = main_tx_cdc_source_source_payload_last_be;
+assign main_tx_converter_sink_payload_error = main_tx_cdc_source_source_payload_error;
+assign main_tx_last_be_sink_valid = main_tx_converter_source_valid;
+assign main_tx_converter_source_ready = main_tx_last_be_sink_ready;
+assign main_tx_last_be_sink_first = main_tx_converter_source_first;
+assign main_tx_last_be_sink_last = main_tx_converter_source_last;
+assign main_tx_last_be_sink_payload_data = main_tx_converter_source_payload_data;
+assign main_tx_last_be_sink_payload_last_be = main_tx_converter_source_payload_last_be;
+assign main_tx_last_be_sink_payload_error = main_tx_converter_source_payload_error;
+assign main_padding_inserter_sink_valid = main_tx_last_be_source_valid;
+assign main_tx_last_be_source_ready = main_padding_inserter_sink_ready;
+assign main_padding_inserter_sink_first = main_tx_last_be_source_first;
+assign main_padding_inserter_sink_last = main_tx_last_be_source_last;
+assign main_padding_inserter_sink_payload_data = main_tx_last_be_source_payload_data;
+assign main_padding_inserter_sink_payload_last_be = main_tx_last_be_source_payload_last_be;
+assign main_padding_inserter_sink_payload_error = main_tx_last_be_source_payload_error;
+assign main_crc32_inserter_sink_valid = main_padding_inserter_source_valid;
+assign main_padding_inserter_source_ready = main_crc32_inserter_sink_ready;
+assign main_crc32_inserter_sink_first = main_padding_inserter_source_first;
+assign main_crc32_inserter_sink_last = main_padding_inserter_source_last;
+assign main_crc32_inserter_sink_payload_data = main_padding_inserter_source_payload_data;
+assign main_crc32_inserter_sink_payload_last_be = main_padding_inserter_source_payload_last_be;
+assign main_crc32_inserter_sink_payload_error = main_padding_inserter_source_payload_error;
+assign main_preamble_inserter_sink_valid = main_liteethmaccrc32inserter_source_valid;
+assign main_liteethmaccrc32inserter_source_ready = main_preamble_inserter_sink_ready;
+assign main_preamble_inserter_sink_first = main_liteethmaccrc32inserter_source_first;
+assign main_preamble_inserter_sink_last = main_liteethmaccrc32inserter_source_last;
+assign main_preamble_inserter_sink_payload_data = main_liteethmaccrc32inserter_source_payload_data;
+assign main_preamble_inserter_sink_payload_last_be = main_liteethmaccrc32inserter_source_payload_last_be;
+assign main_preamble_inserter_sink_payload_error = main_liteethmaccrc32inserter_source_payload_error;
+assign main_tx_gap_inserter_sink_valid = main_preamble_inserter_source_valid;
+assign main_preamble_inserter_source_ready = main_tx_gap_inserter_sink_ready;
+assign main_tx_gap_inserter_sink_first = main_preamble_inserter_source_first;
+assign main_tx_gap_inserter_sink_last = main_preamble_inserter_source_last;
+assign main_tx_gap_inserter_sink_payload_data = main_preamble_inserter_source_payload_data;
+assign main_tx_gap_inserter_sink_payload_last_be = main_preamble_inserter_source_payload_last_be;
+assign main_tx_gap_inserter_sink_payload_error = main_preamble_inserter_source_payload_error;
+assign main_maccore_ethphy_sink_valid = main_tx_gap_inserter_source_valid;
+assign main_tx_gap_inserter_source_ready = main_maccore_ethphy_sink_ready;
+assign main_maccore_ethphy_sink_first = main_tx_gap_inserter_source_first;
+assign main_maccore_ethphy_sink_last = main_tx_gap_inserter_source_last;
+assign main_maccore_ethphy_sink_payload_data = main_tx_gap_inserter_source_payload_data;
+assign main_maccore_ethphy_sink_payload_last_be = main_tx_gap_inserter_source_payload_last_be;
+assign main_maccore_ethphy_sink_payload_error = main_tx_gap_inserter_source_payload_error;
+assign main_preamble_checker_sink_valid = main_maccore_ethphy_source_valid;
+assign main_maccore_ethphy_source_ready = main_preamble_checker_sink_ready;
+assign main_preamble_checker_sink_first = main_maccore_ethphy_source_first;
+assign main_preamble_checker_sink_last = main_maccore_ethphy_source_last;
+assign main_preamble_checker_sink_payload_data = main_maccore_ethphy_source_payload_data;
+assign main_preamble_checker_sink_payload_last_be = main_maccore_ethphy_source_payload_last_be;
+assign main_preamble_checker_sink_payload_error = main_maccore_ethphy_source_payload_error;
+assign main_crc32_checker_sink_valid = main_preamble_checker_source_valid;
+assign main_preamble_checker_source_ready = main_crc32_checker_sink_ready;
+assign main_crc32_checker_sink_first = main_preamble_checker_source_first;
+assign main_crc32_checker_sink_last = main_preamble_checker_source_last;
+assign main_crc32_checker_sink_payload_data = main_preamble_checker_source_payload_data;
+assign main_crc32_checker_sink_payload_last_be = main_preamble_checker_source_payload_last_be;
+assign main_crc32_checker_sink_payload_error = main_preamble_checker_source_payload_error;
+assign main_padding_checker_sink_valid = main_liteethmaccrc32checker_source_source_valid;
+assign main_liteethmaccrc32checker_source_source_ready = main_padding_checker_sink_ready;
+assign main_padding_checker_sink_first = main_liteethmaccrc32checker_source_source_first;
+assign main_padding_checker_sink_last = main_liteethmaccrc32checker_source_source_last;
+assign main_padding_checker_sink_payload_data = main_liteethmaccrc32checker_source_source_payload_data;
+assign main_padding_checker_sink_payload_last_be = main_liteethmaccrc32checker_source_source_payload_last_be;
+assign main_padding_checker_sink_payload_error = main_liteethmaccrc32checker_source_source_payload_error;
+assign main_rx_last_be_sink_valid = main_padding_checker_source_valid;
+assign main_padding_checker_source_ready = main_rx_last_be_sink_ready;
+assign main_rx_last_be_sink_first = main_padding_checker_source_first;
+assign main_rx_last_be_sink_last = main_padding_checker_source_last;
+assign main_rx_last_be_sink_payload_data = main_padding_checker_source_payload_data;
+assign main_rx_last_be_sink_payload_last_be = main_padding_checker_source_payload_last_be;
+assign main_rx_last_be_sink_payload_error = main_padding_checker_source_payload_error;
+assign main_rx_converter_sink_valid = main_rx_last_be_source_valid;
+assign main_rx_last_be_source_ready = main_rx_converter_sink_ready;
+assign main_rx_converter_sink_first = main_rx_last_be_source_first;
+assign main_rx_converter_sink_last = main_rx_last_be_source_last;
+assign main_rx_converter_sink_payload_data = main_rx_last_be_source_payload_data;
+assign main_rx_converter_sink_payload_last_be = main_rx_last_be_source_payload_last_be;
+assign main_rx_converter_sink_payload_error = main_rx_last_be_source_payload_error;
+assign main_rx_cdc_sink_sink_valid = main_rx_converter_source_valid;
+assign main_rx_converter_source_ready = main_rx_cdc_sink_sink_ready;
+assign main_rx_cdc_sink_sink_first = main_rx_converter_source_first;
+assign main_rx_cdc_sink_sink_last = main_rx_converter_source_last;
+assign main_rx_cdc_sink_sink_payload_data = main_rx_converter_source_payload_data;
+assign main_rx_cdc_sink_sink_payload_last_be = main_rx_converter_source_payload_last_be;
+assign main_rx_cdc_sink_sink_payload_error = main_rx_converter_source_payload_error;
+assign main_writer_sink_sink_valid = main_sink_valid;
+assign main_sink_ready = main_writer_sink_sink_ready;
+assign main_writer_sink_sink_first = main_sink_first;
+assign main_writer_sink_sink_last = main_sink_last;
+assign main_writer_sink_sink_payload_data = main_sink_payload_data;
+assign main_writer_sink_sink_payload_last_be = main_sink_payload_last_be;
+assign main_writer_sink_sink_payload_error = main_sink_payload_error;
+assign main_source_valid = main_reader_source_source_valid;
+assign main_reader_source_source_ready = main_source_ready;
+assign main_source_first = main_reader_source_source_first;
+assign main_source_last = main_reader_source_source_last;
+assign main_source_payload_data = main_reader_source_source_payload_data;
+assign main_source_payload_last_be = main_reader_source_source_payload_last_be;
+assign main_source_payload_error = main_reader_source_source_payload_error;
+assign main_writer_stat_fifo_sink_payload_slot = main_writer_slot;
+assign main_writer_stat_fifo_sink_payload_length = main_writer_counter;
+assign main_writer_stat_fifo_source_ready = main_writer_available_clear;
+assign main_writer_available_trigger = main_writer_stat_fifo_source_valid;
+assign main_writer_slot_status = main_writer_stat_fifo_source_payload_slot;
+assign main_writer_length_status = main_writer_stat_fifo_source_payload_length;
+always @(*) begin
+ main_writer_memory1_we <= 1'd0;
+ main_writer_memory0_adr <= 9'd0;
+ main_writer_memory1_dat_w <= 32'd0;
+ main_writer_memory0_we <= 1'd0;
+ main_writer_memory0_dat_w <= 32'd0;
+ main_writer_memory1_adr <= 9'd0;
+ case (main_writer_slot)
+ 1'd0: begin
+ main_writer_memory0_adr <= main_writer_counter[31:2];
+ main_writer_memory0_dat_w <= main_writer_sink_sink_payload_data;
+ if ((main_writer_sink_sink_valid & main_writer_ongoing)) begin
+ main_writer_memory0_we <= 4'd15;
+ end
+ end
+ 1'd1: begin
+ main_writer_memory1_adr <= main_writer_counter[31:2];
+ main_writer_memory1_dat_w <= main_writer_sink_sink_payload_data;
+ if ((main_writer_sink_sink_valid & main_writer_ongoing)) begin
+ main_writer_memory1_we <= 4'd15;
+ end
+ end
+ endcase
+end
+assign main_writer_available0 = main_writer_available_status;
+assign main_writer_available1 = main_writer_available_pending;
+always @(*) begin
+ main_writer_available_clear <= 1'd0;
+ if ((main_writer_pending_re & main_writer_pending_r)) begin
+ main_writer_available_clear <= 1'd1;
+ end
+end
+assign main_writer_irq = (main_writer_pending_status & main_writer_enable_storage);
+assign main_writer_available_status = main_writer_available_trigger;
+assign main_writer_available_pending = main_writer_available_trigger;
+always @(*) begin
+ main_writer_decoded <= 3'd0;
+ case (main_writer_sink_sink_payload_last_be)
+ 1'd1: begin
+ main_writer_decoded <= 1'd1;
+ end
+ 2'd2: begin
+ main_writer_decoded <= 2'd2;
+ end
+ 3'd4: begin
+ main_writer_decoded <= 2'd3;
+ end
+ default: begin
+ main_writer_decoded <= 3'd4;
+ end
+ endcase
+end
+assign main_writer_stat_fifo_syncfifo_din = {main_writer_stat_fifo_fifo_in_last, main_writer_stat_fifo_fifo_in_first, main_writer_stat_fifo_fifo_in_payload_length, main_writer_stat_fifo_fifo_in_payload_slot};
+assign {main_writer_stat_fifo_fifo_out_last, main_writer_stat_fifo_fifo_out_first, main_writer_stat_fifo_fifo_out_payload_length, main_writer_stat_fifo_fifo_out_payload_slot} = main_writer_stat_fifo_syncfifo_dout;
+assign main_writer_stat_fifo_sink_ready = main_writer_stat_fifo_syncfifo_writable;
+assign main_writer_stat_fifo_syncfifo_we = main_writer_stat_fifo_sink_valid;
+assign main_writer_stat_fifo_fifo_in_first = main_writer_stat_fifo_sink_first;
+assign main_writer_stat_fifo_fifo_in_last = main_writer_stat_fifo_sink_last;
+assign main_writer_stat_fifo_fifo_in_payload_slot = main_writer_stat_fifo_sink_payload_slot;
+assign main_writer_stat_fifo_fifo_in_payload_length = main_writer_stat_fifo_sink_payload_length;
+assign main_writer_stat_fifo_source_valid = main_writer_stat_fifo_syncfifo_readable;
+assign main_writer_stat_fifo_source_first = main_writer_stat_fifo_fifo_out_first;
+assign main_writer_stat_fifo_source_last = main_writer_stat_fifo_fifo_out_last;
+assign main_writer_stat_fifo_source_payload_slot = main_writer_stat_fifo_fifo_out_payload_slot;
+assign main_writer_stat_fifo_source_payload_length = main_writer_stat_fifo_fifo_out_payload_length;
+assign main_writer_stat_fifo_syncfifo_re = main_writer_stat_fifo_source_ready;
+always @(*) begin
+ main_writer_stat_fifo_wrport_adr <= 1'd0;
+ if (main_writer_stat_fifo_replace) begin
+ main_writer_stat_fifo_wrport_adr <= (main_writer_stat_fifo_produce - 1'd1);
+ end else begin
+ main_writer_stat_fifo_wrport_adr <= main_writer_stat_fifo_produce;
+ end
+end
+assign main_writer_stat_fifo_wrport_dat_w = main_writer_stat_fifo_syncfifo_din;
+assign main_writer_stat_fifo_wrport_we = (main_writer_stat_fifo_syncfifo_we & (main_writer_stat_fifo_syncfifo_writable | main_writer_stat_fifo_replace));
+assign main_writer_stat_fifo_do_read = (main_writer_stat_fifo_syncfifo_readable & main_writer_stat_fifo_syncfifo_re);
+assign main_writer_stat_fifo_rdport_adr = main_writer_stat_fifo_consume;
+assign main_writer_stat_fifo_syncfifo_dout = main_writer_stat_fifo_rdport_dat_r;
+assign main_writer_stat_fifo_syncfifo_writable = (main_writer_stat_fifo_level != 2'd2);
+assign main_writer_stat_fifo_syncfifo_readable = (main_writer_stat_fifo_level != 1'd0);
+always @(*) begin
+ main_writer_slot_ce <= 1'd0;
+ main_writer_errors_status_f_next_value <= 32'd0;
+ main_writer_start <= 1'd0;
+ main_writer_errors_status_f_next_value_ce <= 1'd0;
+ main_writer_ongoing <= 1'd0;
+ main_writer_stat_fifo_sink_valid <= 1'd0;
+ builder_liteethmacsramwriter_next_state <= 3'd0;
+ main_writer_counter_t_next_value <= 32'd0;
+ main_writer_counter_t_next_value_ce <= 1'd0;
+ builder_liteethmacsramwriter_next_state <= builder_liteethmacsramwriter_state;
+ case (builder_liteethmacsramwriter_state)
+ 1'd1: begin
+ if (main_writer_sink_sink_valid) begin
+ if ((main_writer_counter == 11'd1530)) begin
+ builder_liteethmacsramwriter_next_state <= 2'd3;
+ end else begin
+ main_writer_counter_t_next_value <= (main_writer_counter + main_writer_decoded);
+ main_writer_counter_t_next_value_ce <= 1'd1;
+ main_writer_ongoing <= 1'd1;
+ end
+ if (main_writer_sink_sink_last) begin
+ if (((main_writer_sink_sink_payload_error & main_writer_sink_sink_payload_last_be) != 1'd0)) begin
+ builder_liteethmacsramwriter_next_state <= 2'd2;
+ end else begin
+ builder_liteethmacsramwriter_next_state <= 3'd4;
+ end
+ end
+ end
+ end
+ 2'd2: begin
+ main_writer_counter_t_next_value <= 1'd0;
+ main_writer_counter_t_next_value_ce <= 1'd1;
+ builder_liteethmacsramwriter_next_state <= 1'd0;
+ end
+ 2'd3: begin
+ if ((main_writer_sink_sink_valid & main_writer_sink_sink_last)) begin
+ builder_liteethmacsramwriter_next_state <= 3'd4;
+ end
+ end
+ 3'd4: begin
+ main_writer_counter_t_next_value <= 1'd0;
+ main_writer_counter_t_next_value_ce <= 1'd1;
+ main_writer_slot_ce <= 1'd1;
+ main_writer_stat_fifo_sink_valid <= 1'd1;
+ builder_liteethmacsramwriter_next_state <= 1'd0;
+ end
+ default: begin
+ if (main_writer_sink_sink_valid) begin
+ if (main_writer_stat_fifo_sink_ready) begin
+ main_writer_start <= 1'd1;
+ main_writer_ongoing <= 1'd1;
+ main_writer_counter_t_next_value <= (main_writer_counter + main_writer_decoded);
+ main_writer_counter_t_next_value_ce <= 1'd1;
+ builder_liteethmacsramwriter_next_state <= 1'd1;
+ end else begin
+ main_writer_errors_status_f_next_value <= (main_writer_errors_status + 1'd1);
+ main_writer_errors_status_f_next_value_ce <= 1'd1;
+ builder_liteethmacsramwriter_next_state <= 2'd3;
+ end
+ end
+ end
+ endcase
+end
+assign main_reader_cmd_fifo_sink_valid = main_reader_start_start_re;
+assign main_reader_cmd_fifo_sink_payload_slot = main_reader_slot_storage;
+assign main_reader_cmd_fifo_sink_payload_length = main_reader_length_storage;
+assign main_reader_ready_status = main_reader_cmd_fifo_sink_ready;
+assign main_reader_level_status = main_reader_cmd_fifo_level;
+always @(*) begin
+ main_reader_source_source_payload_last_be <= 4'd0;
+ if (main_reader_source_source_last) begin
+ main_reader_source_source_payload_last_be <= main_reader_encoded;
+ end
+end
+assign main_reader_memory0_adr = main_reader_read_address[10:2];
+assign main_reader_memory1_adr = main_reader_read_address[10:2];
+always @(*) begin
+ main_reader_source_source_payload_data <= 32'd0;
+ case (main_reader_cmd_fifo_source_payload_slot)
+ 1'd0: begin
+ main_reader_source_source_payload_data <= main_reader_memory0_dat_r;
+ end
+ 1'd1: begin
+ main_reader_source_source_payload_data <= main_reader_memory1_dat_r;
+ end
+ endcase
+end
+assign main_reader_event00 = main_reader_eventsourcepulse_status;
+assign main_reader_event01 = main_reader_eventsourcepulse_pending;
+always @(*) begin
+ main_reader_eventsourcepulse_clear <= 1'd0;
+ if ((main_reader_pending_re & main_reader_pending_r)) begin
+ main_reader_eventsourcepulse_clear <= 1'd1;
+ end
+end
+assign main_reader_irq = (main_reader_pending_status & main_reader_enable_storage);
+assign main_reader_eventsourcepulse_status = 1'd0;
+assign main_reader_cmd_fifo_syncfifo_din = {main_reader_cmd_fifo_fifo_in_last, main_reader_cmd_fifo_fifo_in_first, main_reader_cmd_fifo_fifo_in_payload_length, main_reader_cmd_fifo_fifo_in_payload_slot};
+assign {main_reader_cmd_fifo_fifo_out_last, main_reader_cmd_fifo_fifo_out_first, main_reader_cmd_fifo_fifo_out_payload_length, main_reader_cmd_fifo_fifo_out_payload_slot} = main_reader_cmd_fifo_syncfifo_dout;
+assign main_reader_cmd_fifo_sink_ready = main_reader_cmd_fifo_syncfifo_writable;
+assign main_reader_cmd_fifo_syncfifo_we = main_reader_cmd_fifo_sink_valid;
+assign main_reader_cmd_fifo_fifo_in_first = main_reader_cmd_fifo_sink_first;
+assign main_reader_cmd_fifo_fifo_in_last = main_reader_cmd_fifo_sink_last;
+assign main_reader_cmd_fifo_fifo_in_payload_slot = main_reader_cmd_fifo_sink_payload_slot;
+assign main_reader_cmd_fifo_fifo_in_payload_length = main_reader_cmd_fifo_sink_payload_length;
+assign main_reader_cmd_fifo_source_valid = main_reader_cmd_fifo_syncfifo_readable;
+assign main_reader_cmd_fifo_source_first = main_reader_cmd_fifo_fifo_out_first;
+assign main_reader_cmd_fifo_source_last = main_reader_cmd_fifo_fifo_out_last;
+assign main_reader_cmd_fifo_source_payload_slot = main_reader_cmd_fifo_fifo_out_payload_slot;
+assign main_reader_cmd_fifo_source_payload_length = main_reader_cmd_fifo_fifo_out_payload_length;
+assign main_reader_cmd_fifo_syncfifo_re = main_reader_cmd_fifo_source_ready;
+always @(*) begin
+ main_reader_cmd_fifo_wrport_adr <= 1'd0;
+ if (main_reader_cmd_fifo_replace) begin
+ main_reader_cmd_fifo_wrport_adr <= (main_reader_cmd_fifo_produce - 1'd1);
+ end else begin
+ main_reader_cmd_fifo_wrport_adr <= main_reader_cmd_fifo_produce;
+ end
+end
+assign main_reader_cmd_fifo_wrport_dat_w = main_reader_cmd_fifo_syncfifo_din;
+assign main_reader_cmd_fifo_wrport_we = (main_reader_cmd_fifo_syncfifo_we & (main_reader_cmd_fifo_syncfifo_writable | main_reader_cmd_fifo_replace));
+assign main_reader_cmd_fifo_do_read = (main_reader_cmd_fifo_syncfifo_readable & main_reader_cmd_fifo_syncfifo_re);
+assign main_reader_cmd_fifo_rdport_adr = main_reader_cmd_fifo_consume;
+assign main_reader_cmd_fifo_syncfifo_dout = main_reader_cmd_fifo_rdport_dat_r;
+assign main_reader_cmd_fifo_syncfifo_writable = (main_reader_cmd_fifo_level != 2'd2);
+assign main_reader_cmd_fifo_syncfifo_readable = (main_reader_cmd_fifo_level != 1'd0);
+always @(*) begin
+ main_reader_start <= 1'd0;
+ builder_liteethmacsramreader_next_state <= 2'd0;
+ main_reader_counter_next_value <= 11'd0;
+ main_reader_source_source_last <= 1'd0;
+ main_reader_counter_next_value_ce <= 1'd0;
+ main_reader_read_address <= 11'd0;
+ main_reader_cmd_fifo_source_ready <= 1'd0;
+ main_reader_eventsourcepulse_trigger <= 1'd0;
+ main_reader_source_source_valid <= 1'd0;
+ builder_liteethmacsramreader_next_state <= builder_liteethmacsramreader_state;
+ case (builder_liteethmacsramreader_state)
+ 1'd1: begin
+ main_reader_source_source_valid <= 1'd1;
+ main_reader_source_source_last <= (main_reader_counter >= (main_reader_cmd_fifo_source_payload_length - 3'd4));
+ main_reader_read_address <= main_reader_counter;
+ if (main_reader_source_source_ready) begin
+ main_reader_read_address <= (main_reader_counter + 3'd4);
+ main_reader_counter_next_value <= (main_reader_counter + 3'd4);
+ main_reader_counter_next_value_ce <= 1'd1;
+ if (main_reader_source_source_last) begin
+ builder_liteethmacsramreader_next_state <= 2'd2;
+ end
+ end
+ end
+ 2'd2: begin
+ main_reader_eventsourcepulse_trigger <= 1'd1;
+ main_reader_cmd_fifo_source_ready <= 1'd1;
+ builder_liteethmacsramreader_next_state <= 1'd0;
+ end
+ default: begin
+ main_reader_counter_next_value <= 1'd0;
+ main_reader_counter_next_value_ce <= 1'd1;
+ if (main_reader_cmd_fifo_source_valid) begin
+ main_reader_start <= 1'd1;
+ builder_liteethmacsramreader_next_state <= 1'd1;
+ end
+ end
+ endcase
+end
+always @(*) begin
+ main_reader_encoded <= 4'd0;
+ case (main_reader_cmd_fifo_source_payload_length[1:0])
+ 1'd0: begin
+ main_reader_encoded <= 4'd8;
+ end
+ 1'd1: begin
+ main_reader_encoded <= 1'd1;
+ end
+ 2'd2: begin
+ main_reader_encoded <= 2'd2;
+ end
+ 2'd3: begin
+ main_reader_encoded <= 3'd4;
+ end
+ endcase
+end
+assign main_ev_irq = (main_writer_irq | main_reader_irq);
+assign main_sram0_adr0 = main_interface0_adr[8:0];
+assign main_interface0_dat_r = main_sram0_dat_r0;
+assign main_interface0_adr = main_interface0_writer_sram_converted_width_adr;
+assign main_interface0_dat_w = main_interface0_writer_sram_converted_width_dat_w;
+assign main_interface0_writer_sram_converted_width_dat_r = main_interface0_dat_r;
+assign main_interface0_sel = main_interface0_writer_sram_converted_width_sel;
+assign main_interface0_cyc = main_interface0_writer_sram_converted_width_cyc;
+assign main_interface0_stb = main_interface0_writer_sram_converted_width_stb;
+assign main_interface0_writer_sram_converted_width_ack = main_interface0_ack;
+assign main_interface0_we = main_interface0_writer_sram_converted_width_we;
+assign main_interface0_cti = main_interface0_writer_sram_converted_width_cti;
+assign main_interface0_bte = main_interface0_writer_sram_converted_width_bte;
+assign main_interface0_writer_sram_converted_width_err = main_interface0_err;
+assign main_sram1_adr0 = main_interface1_adr[8:0];
+assign main_interface1_dat_r = main_sram1_dat_r0;
+assign main_interface1_adr = main_interface1_writer_sram_converted_width_adr;
+assign main_interface1_dat_w = main_interface1_writer_sram_converted_width_dat_w;
+assign main_interface1_writer_sram_converted_width_dat_r = main_interface1_dat_r;
+assign main_interface1_sel = main_interface1_writer_sram_converted_width_sel;
+assign main_interface1_cyc = main_interface1_writer_sram_converted_width_cyc;
+assign main_interface1_stb = main_interface1_writer_sram_converted_width_stb;
+assign main_interface1_writer_sram_converted_width_ack = main_interface1_ack;
+assign main_interface1_we = main_interface1_writer_sram_converted_width_we;
+assign main_interface1_cti = main_interface1_writer_sram_converted_width_cti;
+assign main_interface1_bte = main_interface1_writer_sram_converted_width_bte;
+assign main_interface1_writer_sram_converted_width_err = main_interface1_err;
+always @(*) begin
+ main_sram0_we <= 4'd0;
+ main_sram0_we[0] <= (((main_interface2_cyc & main_interface2_stb) & main_interface2_we) & main_interface2_sel[0]);
+ main_sram0_we[1] <= (((main_interface2_cyc & main_interface2_stb) & main_interface2_we) & main_interface2_sel[1]);
+ main_sram0_we[2] <= (((main_interface2_cyc & main_interface2_stb) & main_interface2_we) & main_interface2_sel[2]);
+ main_sram0_we[3] <= (((main_interface2_cyc & main_interface2_stb) & main_interface2_we) & main_interface2_sel[3]);
+end
+assign main_sram0_adr1 = main_interface2_adr[8:0];
+assign main_interface2_dat_r = main_sram0_dat_r1;
+assign main_sram0_dat_w = main_interface2_dat_w;
+assign main_interface2_adr = main_interface0_reader_sram_converted_width_adr;
+assign main_interface2_dat_w = main_interface0_reader_sram_converted_width_dat_w;
+assign main_interface0_reader_sram_converted_width_dat_r = main_interface2_dat_r;
+assign main_interface2_sel = main_interface0_reader_sram_converted_width_sel;
+assign main_interface2_cyc = main_interface0_reader_sram_converted_width_cyc;
+assign main_interface2_stb = main_interface0_reader_sram_converted_width_stb;
+assign main_interface0_reader_sram_converted_width_ack = main_interface2_ack;
+assign main_interface2_we = main_interface0_reader_sram_converted_width_we;
+assign main_interface2_cti = main_interface0_reader_sram_converted_width_cti;
+assign main_interface2_bte = main_interface0_reader_sram_converted_width_bte;
+assign main_interface0_reader_sram_converted_width_err = main_interface2_err;
+always @(*) begin
+ main_sram1_we <= 4'd0;
+ main_sram1_we[0] <= (((main_interface3_cyc & main_interface3_stb) & main_interface3_we) & main_interface3_sel[0]);
+ main_sram1_we[1] <= (((main_interface3_cyc & main_interface3_stb) & main_interface3_we) & main_interface3_sel[1]);
+ main_sram1_we[2] <= (((main_interface3_cyc & main_interface3_stb) & main_interface3_we) & main_interface3_sel[2]);
+ main_sram1_we[3] <= (((main_interface3_cyc & main_interface3_stb) & main_interface3_we) & main_interface3_sel[3]);
+end
+assign main_sram1_adr1 = main_interface3_adr[8:0];
+assign main_interface3_dat_r = main_sram1_dat_r1;
+assign main_sram1_dat_w = main_interface3_dat_w;
+assign main_interface3_adr = main_interface1_reader_sram_converted_width_adr;
+assign main_interface3_dat_w = main_interface1_reader_sram_converted_width_dat_w;
+assign main_interface1_reader_sram_converted_width_dat_r = main_interface3_dat_r;
+assign main_interface3_sel = main_interface1_reader_sram_converted_width_sel;
+assign main_interface3_cyc = main_interface1_reader_sram_converted_width_cyc;
+assign main_interface3_stb = main_interface1_reader_sram_converted_width_stb;
+assign main_interface1_reader_sram_converted_width_ack = main_interface3_ack;
+assign main_interface3_we = main_interface1_reader_sram_converted_width_we;
+assign main_interface3_cti = main_interface1_reader_sram_converted_width_cti;
+assign main_interface3_bte = main_interface1_reader_sram_converted_width_bte;
+assign main_interface1_reader_sram_converted_width_err = main_interface3_err;
+always @(*) begin
+ main_slave_sel <= 4'd0;
+ main_slave_sel[0] <= (main_bus_adr[10:9] == 1'd0);
+ main_slave_sel[1] <= (main_bus_adr[10:9] == 1'd1);
+ main_slave_sel[2] <= (main_bus_adr[10:9] == 2'd2);
+ main_slave_sel[3] <= (main_bus_adr[10:9] == 2'd3);
+end
+assign main_interface0_writer_sram_converted_width_adr = main_bus_adr;
+assign main_interface0_writer_sram_converted_width_dat_w = main_bus_dat_w;
+assign main_interface0_writer_sram_converted_width_sel = main_bus_sel;
+assign main_interface0_writer_sram_converted_width_stb = main_bus_stb;
+assign main_interface0_writer_sram_converted_width_we = main_bus_we;
+assign main_interface0_writer_sram_converted_width_cti = main_bus_cti;
+assign main_interface0_writer_sram_converted_width_bte = main_bus_bte;
+assign main_interface1_writer_sram_converted_width_adr = main_bus_adr;
+assign main_interface1_writer_sram_converted_width_dat_w = main_bus_dat_w;
+assign main_interface1_writer_sram_converted_width_sel = main_bus_sel;
+assign main_interface1_writer_sram_converted_width_stb = main_bus_stb;
+assign main_interface1_writer_sram_converted_width_we = main_bus_we;
+assign main_interface1_writer_sram_converted_width_cti = main_bus_cti;
+assign main_interface1_writer_sram_converted_width_bte = main_bus_bte;
+assign main_interface0_reader_sram_converted_width_adr = main_bus_adr;
+assign main_interface0_reader_sram_converted_width_dat_w = main_bus_dat_w;
+assign main_interface0_reader_sram_converted_width_sel = main_bus_sel;
+assign main_interface0_reader_sram_converted_width_stb = main_bus_stb;
+assign main_interface0_reader_sram_converted_width_we = main_bus_we;
+assign main_interface0_reader_sram_converted_width_cti = main_bus_cti;
+assign main_interface0_reader_sram_converted_width_bte = main_bus_bte;
+assign main_interface1_reader_sram_converted_width_adr = main_bus_adr;
+assign main_interface1_reader_sram_converted_width_dat_w = main_bus_dat_w;
+assign main_interface1_reader_sram_converted_width_sel = main_bus_sel;
+assign main_interface1_reader_sram_converted_width_stb = main_bus_stb;
+assign main_interface1_reader_sram_converted_width_we = main_bus_we;
+assign main_interface1_reader_sram_converted_width_cti = main_bus_cti;
+assign main_interface1_reader_sram_converted_width_bte = main_bus_bte;
+assign main_interface0_writer_sram_converted_width_cyc = (main_bus_cyc & main_slave_sel[0]);
+assign main_interface1_writer_sram_converted_width_cyc = (main_bus_cyc & main_slave_sel[1]);
+assign main_interface0_reader_sram_converted_width_cyc = (main_bus_cyc & main_slave_sel[2]);
+assign main_interface1_reader_sram_converted_width_cyc = (main_bus_cyc & main_slave_sel[3]);
+assign main_bus_ack = (((main_interface0_writer_sram_converted_width_ack | main_interface1_writer_sram_converted_width_ack) | main_interface0_reader_sram_converted_width_ack) | main_interface1_reader_sram_converted_width_ack);
+assign main_bus_err = (((main_interface0_writer_sram_converted_width_err | main_interface1_writer_sram_converted_width_err) | main_interface0_reader_sram_converted_width_err) | main_interface1_reader_sram_converted_width_err);
+assign main_bus_dat_r = (((({32{main_slave_sel_r[0]}} & main_interface0_writer_sram_converted_width_dat_r) | ({32{main_slave_sel_r[1]}} & main_interface1_writer_sram_converted_width_dat_r)) | ({32{main_slave_sel_r[2]}} & main_interface0_reader_sram_converted_width_dat_r)) | ({32{main_slave_sel_r[3]}} & main_interface1_reader_sram_converted_width_dat_r));
+always @(*) begin
+ builder_maccore_wishbone_ack <= 1'd0;
+ builder_next_state <= 1'd0;
+ builder_maccore_wishbone_dat_r <= 32'd0;
+ builder_maccore_adr <= 14'd0;
+ builder_maccore_we <= 1'd0;
+ builder_maccore_dat_w <= 32'd0;
+ builder_next_state <= builder_state;
+ case (builder_state)
+ 1'd1: begin
+ builder_maccore_wishbone_ack <= 1'd1;
+ builder_maccore_wishbone_dat_r <= builder_maccore_dat_r;
+ builder_next_state <= 1'd0;
+ end
+ default: begin
+ builder_maccore_dat_w <= builder_maccore_wishbone_dat_w;
+ if ((builder_maccore_wishbone_cyc & builder_maccore_wishbone_stb)) begin
+ builder_maccore_adr <= builder_maccore_wishbone_adr;
+ builder_maccore_we <= (builder_maccore_wishbone_we & (builder_maccore_wishbone_sel != 1'd0));
+ builder_next_state <= 1'd1;
+ end
+ end
+ endcase
+end
+assign builder_shared_adr = builder_array_muxed0;
+assign builder_shared_dat_w = builder_array_muxed1;
+assign builder_shared_sel = builder_array_muxed2;
+assign builder_shared_cyc = builder_array_muxed3;
+assign builder_shared_stb = builder_array_muxed4;
+assign builder_shared_we = builder_array_muxed5;
+assign builder_shared_cti = builder_array_muxed6;
+assign builder_shared_bte = builder_array_muxed7;
+assign main_wb_bus_dat_r = builder_shared_dat_r;
+assign main_wb_bus_ack = (builder_shared_ack & (builder_grant == 1'd0));
+assign main_wb_bus_err = (builder_shared_err & (builder_grant == 1'd0));
+assign builder_request = {main_wb_bus_cyc};
+assign builder_grant = 1'd0;
+always @(*) begin
+ builder_slave_sel <= 2'd0;
+ builder_slave_sel[0] <= (builder_shared_adr[29:11] == 4'd8);
+ builder_slave_sel[1] <= (builder_shared_adr[29:14] == 1'd0);
+end
+assign main_bus_adr = builder_shared_adr;
+assign main_bus_dat_w = builder_shared_dat_w;
+assign main_bus_sel = builder_shared_sel;
+assign main_bus_stb = builder_shared_stb;
+assign main_bus_we = builder_shared_we;
+assign main_bus_cti = builder_shared_cti;
+assign main_bus_bte = builder_shared_bte;
+assign builder_maccore_wishbone_adr = builder_shared_adr;
+assign builder_maccore_wishbone_dat_w = builder_shared_dat_w;
+assign builder_maccore_wishbone_sel = builder_shared_sel;
+assign builder_maccore_wishbone_stb = builder_shared_stb;
+assign builder_maccore_wishbone_we = builder_shared_we;
+assign builder_maccore_wishbone_cti = builder_shared_cti;
+assign builder_maccore_wishbone_bte = builder_shared_bte;
+assign main_bus_cyc = (builder_shared_cyc & builder_slave_sel[0]);
+assign builder_maccore_wishbone_cyc = (builder_shared_cyc & builder_slave_sel[1]);
+assign builder_shared_err = (main_bus_err | builder_maccore_wishbone_err);
+assign builder_wait = ((builder_shared_stb & builder_shared_cyc) & (~builder_shared_ack));
+always @(*) begin
+ builder_shared_ack <= 1'd0;
+ builder_error <= 1'd0;
+ builder_shared_dat_r <= 32'd0;
+ builder_shared_ack <= (main_bus_ack | builder_maccore_wishbone_ack);
+ builder_shared_dat_r <= (({32{builder_slave_sel_r[0]}} & main_bus_dat_r) | ({32{builder_slave_sel_r[1]}} & builder_maccore_wishbone_dat_r));
+ if (builder_done) begin
+ builder_shared_dat_r <= 32'd4294967295;
+ builder_shared_ack <= 1'd1;
+ builder_error <= 1'd1;
+ end
+end
+assign builder_done = (builder_count == 1'd0);
+assign builder_csrbank0_sel = (builder_interface0_bank_bus_adr[13:9] == 2'd2);
+assign builder_csrbank0_reset0_r = builder_interface0_bank_bus_dat_w[1:0];
+always @(*) begin
+ builder_csrbank0_reset0_re <= 1'd0;
+ builder_csrbank0_reset0_we <= 1'd0;
+ if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd0))) begin
+ builder_csrbank0_reset0_re <= builder_interface0_bank_bus_we;
+ builder_csrbank0_reset0_we <= (~builder_interface0_bank_bus_we);
+ end
+end
+assign builder_csrbank0_scratch0_r = builder_interface0_bank_bus_dat_w[31:0];
+always @(*) begin
+ builder_csrbank0_scratch0_we <= 1'd0;
+ builder_csrbank0_scratch0_re <= 1'd0;
+ if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd1))) begin
+ builder_csrbank0_scratch0_re <= builder_interface0_bank_bus_we;
+ builder_csrbank0_scratch0_we <= (~builder_interface0_bank_bus_we);
+ end
+end
+assign builder_csrbank0_bus_errors_r = builder_interface0_bank_bus_dat_w[31:0];
+always @(*) begin
+ builder_csrbank0_bus_errors_we <= 1'd0;
+ builder_csrbank0_bus_errors_re <= 1'd0;
+ if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 2'd2))) begin
+ builder_csrbank0_bus_errors_re <= builder_interface0_bank_bus_we;
+ builder_csrbank0_bus_errors_we <= (~builder_interface0_bank_bus_we);
+ end
+end
+always @(*) begin
+ main_maccore_maccore_soc_rst <= 1'd0;
+ if (main_maccore_maccore_reset_re) begin
+ main_maccore_maccore_soc_rst <= main_maccore_maccore_reset_storage[0];
+ end
+end
+assign main_maccore_maccore_cpu_rst = main_maccore_maccore_reset_storage[1];
+assign builder_csrbank0_reset0_w = main_maccore_maccore_reset_storage[1:0];
+assign builder_csrbank0_scratch0_w = main_maccore_maccore_scratch_storage[31:0];
+assign builder_csrbank0_bus_errors_w = main_maccore_maccore_bus_errors_status[31:0];
+assign main_maccore_maccore_bus_errors_we = builder_csrbank0_bus_errors_we;
+assign builder_csrbank1_sel = (builder_interface1_bank_bus_adr[13:9] == 1'd1);
+assign builder_csrbank1_sram_writer_slot_r = builder_interface1_bank_bus_dat_w[0];
+always @(*) begin
+ builder_csrbank1_sram_writer_slot_we <= 1'd0;
+ builder_csrbank1_sram_writer_slot_re <= 1'd0;
+ if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd0))) begin
+ builder_csrbank1_sram_writer_slot_re <= builder_interface1_bank_bus_we;
+ builder_csrbank1_sram_writer_slot_we <= (~builder_interface1_bank_bus_we);
+ end
+end
+assign builder_csrbank1_sram_writer_length_r = builder_interface1_bank_bus_dat_w[31:0];
+always @(*) begin
+ builder_csrbank1_sram_writer_length_we <= 1'd0;
+ builder_csrbank1_sram_writer_length_re <= 1'd0;
+ if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd1))) begin
+ builder_csrbank1_sram_writer_length_re <= builder_interface1_bank_bus_we;
+ builder_csrbank1_sram_writer_length_we <= (~builder_interface1_bank_bus_we);
+ end
+end
+assign builder_csrbank1_sram_writer_errors_r = builder_interface1_bank_bus_dat_w[31:0];
+always @(*) begin
+ builder_csrbank1_sram_writer_errors_re <= 1'd0;
+ builder_csrbank1_sram_writer_errors_we <= 1'd0;
+ if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd2))) begin
+ builder_csrbank1_sram_writer_errors_re <= builder_interface1_bank_bus_we;
+ builder_csrbank1_sram_writer_errors_we <= (~builder_interface1_bank_bus_we);
+ end
+end
+assign builder_csrbank1_sram_writer_ev_status_r = builder_interface1_bank_bus_dat_w[0];
+always @(*) begin
+ builder_csrbank1_sram_writer_ev_status_re <= 1'd0;
+ builder_csrbank1_sram_writer_ev_status_we <= 1'd0;
+ if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd3))) begin
+ builder_csrbank1_sram_writer_ev_status_re <= builder_interface1_bank_bus_we;
+ builder_csrbank1_sram_writer_ev_status_we <= (~builder_interface1_bank_bus_we);
+ end
+end
+assign builder_csrbank1_sram_writer_ev_pending_r = builder_interface1_bank_bus_dat_w[0];
+always @(*) begin
+ builder_csrbank1_sram_writer_ev_pending_we <= 1'd0;
+ builder_csrbank1_sram_writer_ev_pending_re <= 1'd0;
+ if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd4))) begin
+ builder_csrbank1_sram_writer_ev_pending_re <= builder_interface1_bank_bus_we;
+ builder_csrbank1_sram_writer_ev_pending_we <= (~builder_interface1_bank_bus_we);
+ end
+end
+assign builder_csrbank1_sram_writer_ev_enable0_r = builder_interface1_bank_bus_dat_w[0];
+always @(*) begin
+ builder_csrbank1_sram_writer_ev_enable0_re <= 1'd0;
+ builder_csrbank1_sram_writer_ev_enable0_we <= 1'd0;
+ if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd5))) begin
+ builder_csrbank1_sram_writer_ev_enable0_re <= builder_interface1_bank_bus_we;
+ builder_csrbank1_sram_writer_ev_enable0_we <= (~builder_interface1_bank_bus_we);
+ end
+end
+assign main_reader_start_start_r = builder_interface1_bank_bus_dat_w[0];
+always @(*) begin
+ main_reader_start_start_we <= 1'd0;
+ main_reader_start_start_re <= 1'd0;
+ if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd6))) begin
+ main_reader_start_start_re <= builder_interface1_bank_bus_we;
+ main_reader_start_start_we <= (~builder_interface1_bank_bus_we);
+ end
+end
+assign builder_csrbank1_sram_reader_ready_r = builder_interface1_bank_bus_dat_w[0];
+always @(*) begin
+ builder_csrbank1_sram_reader_ready_re <= 1'd0;
+ builder_csrbank1_sram_reader_ready_we <= 1'd0;
+ if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd7))) begin
+ builder_csrbank1_sram_reader_ready_re <= builder_interface1_bank_bus_we;
+ builder_csrbank1_sram_reader_ready_we <= (~builder_interface1_bank_bus_we);
+ end
+end
+assign builder_csrbank1_sram_reader_level_r = builder_interface1_bank_bus_dat_w[1:0];
+always @(*) begin
+ builder_csrbank1_sram_reader_level_we <= 1'd0;
+ builder_csrbank1_sram_reader_level_re <= 1'd0;
+ if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd8))) begin
+ builder_csrbank1_sram_reader_level_re <= builder_interface1_bank_bus_we;
+ builder_csrbank1_sram_reader_level_we <= (~builder_interface1_bank_bus_we);
+ end
+end
+assign builder_csrbank1_sram_reader_slot0_r = builder_interface1_bank_bus_dat_w[0];
+always @(*) begin
+ builder_csrbank1_sram_reader_slot0_we <= 1'd0;
+ builder_csrbank1_sram_reader_slot0_re <= 1'd0;
+ if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd9))) begin
+ builder_csrbank1_sram_reader_slot0_re <= builder_interface1_bank_bus_we;
+ builder_csrbank1_sram_reader_slot0_we <= (~builder_interface1_bank_bus_we);
+ end
+end
+assign builder_csrbank1_sram_reader_length0_r = builder_interface1_bank_bus_dat_w[10:0];
+always @(*) begin
+ builder_csrbank1_sram_reader_length0_re <= 1'd0;
+ builder_csrbank1_sram_reader_length0_we <= 1'd0;
+ if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd10))) begin
+ builder_csrbank1_sram_reader_length0_re <= builder_interface1_bank_bus_we;
+ builder_csrbank1_sram_reader_length0_we <= (~builder_interface1_bank_bus_we);
+ end
+end
+assign builder_csrbank1_sram_reader_ev_status_r = builder_interface1_bank_bus_dat_w[0];
+always @(*) begin
+ builder_csrbank1_sram_reader_ev_status_we <= 1'd0;
+ builder_csrbank1_sram_reader_ev_status_re <= 1'd0;
+ if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd11))) begin
+ builder_csrbank1_sram_reader_ev_status_re <= builder_interface1_bank_bus_we;
+ builder_csrbank1_sram_reader_ev_status_we <= (~builder_interface1_bank_bus_we);
+ end
+end
+assign builder_csrbank1_sram_reader_ev_pending_r = builder_interface1_bank_bus_dat_w[0];
+always @(*) begin
+ builder_csrbank1_sram_reader_ev_pending_we <= 1'd0;
+ builder_csrbank1_sram_reader_ev_pending_re <= 1'd0;
+ if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd12))) begin
+ builder_csrbank1_sram_reader_ev_pending_re <= builder_interface1_bank_bus_we;
+ builder_csrbank1_sram_reader_ev_pending_we <= (~builder_interface1_bank_bus_we);
+ end
+end
+assign builder_csrbank1_sram_reader_ev_enable0_r = builder_interface1_bank_bus_dat_w[0];
+always @(*) begin
+ builder_csrbank1_sram_reader_ev_enable0_re <= 1'd0;
+ builder_csrbank1_sram_reader_ev_enable0_we <= 1'd0;
+ if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd13))) begin
+ builder_csrbank1_sram_reader_ev_enable0_re <= builder_interface1_bank_bus_we;
+ builder_csrbank1_sram_reader_ev_enable0_we <= (~builder_interface1_bank_bus_we);
+ end
+end
+assign builder_csrbank1_preamble_crc_r = builder_interface1_bank_bus_dat_w[0];
+always @(*) begin
+ builder_csrbank1_preamble_crc_we <= 1'd0;
+ builder_csrbank1_preamble_crc_re <= 1'd0;
+ if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd14))) begin
+ builder_csrbank1_preamble_crc_re <= builder_interface1_bank_bus_we;
+ builder_csrbank1_preamble_crc_we <= (~builder_interface1_bank_bus_we);
+ end
+end
+assign builder_csrbank1_preamble_errors_r = builder_interface1_bank_bus_dat_w[31:0];
+always @(*) begin
+ builder_csrbank1_preamble_errors_we <= 1'd0;
+ builder_csrbank1_preamble_errors_re <= 1'd0;
+ if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd15))) begin
+ builder_csrbank1_preamble_errors_re <= builder_interface1_bank_bus_we;
+ builder_csrbank1_preamble_errors_we <= (~builder_interface1_bank_bus_we);
+ end
+end
+assign builder_csrbank1_crc_errors_r = builder_interface1_bank_bus_dat_w[31:0];
+always @(*) begin
+ builder_csrbank1_crc_errors_re <= 1'd0;
+ builder_csrbank1_crc_errors_we <= 1'd0;
+ if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 5'd16))) begin
+ builder_csrbank1_crc_errors_re <= builder_interface1_bank_bus_we;
+ builder_csrbank1_crc_errors_we <= (~builder_interface1_bank_bus_we);
+ end
+end
+assign builder_csrbank1_sram_writer_slot_w = main_writer_slot_status;
+assign main_writer_slot_we = builder_csrbank1_sram_writer_slot_we;
+assign builder_csrbank1_sram_writer_length_w = main_writer_length_status[31:0];
+assign main_writer_length_we = builder_csrbank1_sram_writer_length_we;
+assign builder_csrbank1_sram_writer_errors_w = main_writer_errors_status[31:0];
+assign main_writer_errors_we = builder_csrbank1_sram_writer_errors_we;
+assign main_writer_status_status = main_writer_available0;
+assign builder_csrbank1_sram_writer_ev_status_w = main_writer_status_status;
+assign main_writer_status_we = builder_csrbank1_sram_writer_ev_status_we;
+assign main_writer_pending_status = main_writer_available1;
+assign builder_csrbank1_sram_writer_ev_pending_w = main_writer_pending_status;
+assign main_writer_pending_we = builder_csrbank1_sram_writer_ev_pending_we;
+assign main_writer_available2 = main_writer_enable_storage;
+assign builder_csrbank1_sram_writer_ev_enable0_w = main_writer_enable_storage;
+assign builder_csrbank1_sram_reader_ready_w = main_reader_ready_status;
+assign main_reader_ready_we = builder_csrbank1_sram_reader_ready_we;
+assign builder_csrbank1_sram_reader_level_w = main_reader_level_status[1:0];
+assign main_reader_level_we = builder_csrbank1_sram_reader_level_we;
+assign builder_csrbank1_sram_reader_slot0_w = main_reader_slot_storage;
+assign builder_csrbank1_sram_reader_length0_w = main_reader_length_storage[10:0];
+assign main_reader_status_status = main_reader_event00;
+assign builder_csrbank1_sram_reader_ev_status_w = main_reader_status_status;
+assign main_reader_status_we = builder_csrbank1_sram_reader_ev_status_we;
+assign main_reader_pending_status = main_reader_event01;
+assign builder_csrbank1_sram_reader_ev_pending_w = main_reader_pending_status;
+assign main_reader_pending_we = builder_csrbank1_sram_reader_ev_pending_we;
+assign main_reader_event02 = main_reader_enable_storage;
+assign builder_csrbank1_sram_reader_ev_enable0_w = main_reader_enable_storage;
+assign builder_csrbank1_preamble_crc_w = main_preamble_crc_status;
+assign main_preamble_crc_we = builder_csrbank1_preamble_crc_we;
+assign builder_csrbank1_preamble_errors_w = main_preamble_errors_status[31:0];
+assign main_preamble_errors_we = builder_csrbank1_preamble_errors_we;
+assign builder_csrbank1_crc_errors_w = main_crc_errors_status[31:0];
+assign main_crc_errors_we = builder_csrbank1_crc_errors_we;
+assign builder_csrbank2_sel = (builder_interface2_bank_bus_adr[13:9] == 1'd0);
+assign builder_csrbank2_crg_reset0_r = builder_interface2_bank_bus_dat_w[0];
+always @(*) begin
+ builder_csrbank2_crg_reset0_re <= 1'd0;
+ builder_csrbank2_crg_reset0_we <= 1'd0;
+ if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd0))) begin
+ builder_csrbank2_crg_reset0_re <= builder_interface2_bank_bus_we;
+ builder_csrbank2_crg_reset0_we <= (~builder_interface2_bank_bus_we);
+ end
+end
+assign builder_csrbank2_rx_inband_status_r = builder_interface2_bank_bus_dat_w[2:0];
+always @(*) begin
+ builder_csrbank2_rx_inband_status_we <= 1'd0;
+ builder_csrbank2_rx_inband_status_re <= 1'd0;
+ if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd1))) begin
+ builder_csrbank2_rx_inband_status_re <= builder_interface2_bank_bus_we;
+ builder_csrbank2_rx_inband_status_we <= (~builder_interface2_bank_bus_we);
+ end
+end
+assign builder_csrbank2_mdio_w0_r = builder_interface2_bank_bus_dat_w[2:0];
+always @(*) begin
+ builder_csrbank2_mdio_w0_we <= 1'd0;
+ builder_csrbank2_mdio_w0_re <= 1'd0;
+ if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd2))) begin
+ builder_csrbank2_mdio_w0_re <= builder_interface2_bank_bus_we;
+ builder_csrbank2_mdio_w0_we <= (~builder_interface2_bank_bus_we);
+ end
+end
+assign builder_csrbank2_mdio_r_r = builder_interface2_bank_bus_dat_w[0];
+always @(*) begin
+ builder_csrbank2_mdio_r_re <= 1'd0;
+ builder_csrbank2_mdio_r_we <= 1'd0;
+ if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd3))) begin
+ builder_csrbank2_mdio_r_re <= builder_interface2_bank_bus_we;
+ builder_csrbank2_mdio_r_we <= (~builder_interface2_bank_bus_we);
+ end
+end
+assign builder_csrbank2_crg_reset0_w = main_maccore_ethphy_reset_storage;
+always @(*) begin
+ main_maccore_ethphy_status <= 3'd0;
+ main_maccore_ethphy_status[0] <= main_maccore_ethphy_link_status;
+ main_maccore_ethphy_status[1] <= main_maccore_ethphy_clock_speed;
+ main_maccore_ethphy_status[2] <= main_maccore_ethphy_duplex_status;
+end
+assign builder_csrbank2_rx_inband_status_w = main_maccore_ethphy_status[2:0];
+assign main_maccore_ethphy_we = builder_csrbank2_rx_inband_status_we;
+assign main_maccore_ethphy_mdc = main_maccore_ethphy__w_storage[0];
+assign main_maccore_ethphy_oe = main_maccore_ethphy__w_storage[1];
+assign main_maccore_ethphy_w = main_maccore_ethphy__w_storage[2];
+assign builder_csrbank2_mdio_w0_w = main_maccore_ethphy__w_storage[2:0];
+assign builder_csrbank2_mdio_r_w = main_maccore_ethphy__r_status;
+assign main_maccore_ethphy__r_we = builder_csrbank2_mdio_r_we;
+assign builder_csr_interconnect_adr = builder_maccore_adr;
+assign builder_csr_interconnect_we = builder_maccore_we;
+assign builder_csr_interconnect_dat_w = builder_maccore_dat_w;
+assign builder_maccore_dat_r = builder_csr_interconnect_dat_r;
+assign builder_interface0_bank_bus_adr = builder_csr_interconnect_adr;
+assign builder_interface1_bank_bus_adr = builder_csr_interconnect_adr;
+assign builder_interface2_bank_bus_adr = builder_csr_interconnect_adr;
+assign builder_interface0_bank_bus_we = builder_csr_interconnect_we;
+assign builder_interface1_bank_bus_we = builder_csr_interconnect_we;
+assign builder_interface2_bank_bus_we = builder_csr_interconnect_we;
+assign builder_interface0_bank_bus_dat_w = builder_csr_interconnect_dat_w;
+assign builder_interface1_bank_bus_dat_w = builder_csr_interconnect_dat_w;
+assign builder_interface2_bank_bus_dat_w = builder_csr_interconnect_dat_w;
+assign builder_csr_interconnect_dat_r = ((builder_interface0_bank_bus_dat_r | builder_interface1_bank_bus_dat_r) | builder_interface2_bank_bus_dat_r);
+always @(*) begin
+ builder_array_muxed0 <= 30'd0;
+ case (builder_grant)
+ default: begin
+ builder_array_muxed0 <= main_wb_bus_adr;
+ end
+ endcase
+end
+always @(*) begin
+ builder_array_muxed1 <= 32'd0;
+ case (builder_grant)
+ default: begin
+ builder_array_muxed1 <= main_wb_bus_dat_w;
+ end
+ endcase
+end
+always @(*) begin
+ builder_array_muxed2 <= 4'd0;
+ case (builder_grant)
+ default: begin
+ builder_array_muxed2 <= main_wb_bus_sel;
+ end
+ endcase
+end
+always @(*) begin
+ builder_array_muxed3 <= 1'd0;
+ case (builder_grant)
+ default: begin
+ builder_array_muxed3 <= main_wb_bus_cyc;
+ end
+ endcase
+end
+always @(*) begin
+ builder_array_muxed4 <= 1'd0;
+ case (builder_grant)
+ default: begin
+ builder_array_muxed4 <= main_wb_bus_stb;
+ end
+ endcase
+end
+always @(*) begin
+ builder_array_muxed5 <= 1'd0;
+ case (builder_grant)
+ default: begin
+ builder_array_muxed5 <= main_wb_bus_we;
+ end
+ endcase
+end
+always @(*) begin
+ builder_array_muxed6 <= 3'd0;
+ case (builder_grant)
+ default: begin
+ builder_array_muxed6 <= main_wb_bus_cti;
+ end
+ endcase
+end
+always @(*) begin
+ builder_array_muxed7 <= 2'd0;
+ case (builder_grant)
+ default: begin
+ builder_array_muxed7 <= main_wb_bus_bte;
+ end
+ endcase
+end
+always @(*) begin
+ main_maccore_ethphy__r_status <= 1'd0;
+ main_maccore_ethphy__r_status <= main_maccore_ethphy_r;
+ main_maccore_ethphy__r_status <= builder_multiregimpl0_regs1;
+end
+assign main_ps_preamble_error_toggle_o = builder_multiregimpl1_regs1;
+assign main_ps_crc_error_toggle_o = builder_multiregimpl2_regs1;
+assign main_tx_cdc_cdc_produce_rdomain = builder_multiregimpl3_regs1;
+assign main_tx_cdc_cdc_consume_wdomain = builder_multiregimpl4_regs1;
+assign main_rx_cdc_cdc_produce_rdomain = builder_multiregimpl5_regs1;
+assign main_rx_cdc_cdc_consume_wdomain = builder_multiregimpl6_regs1;
+
+
+//------------------------------------------------------------------------------
+// Synchronous Logic
+//------------------------------------------------------------------------------
+
+always @(posedge eth_rx_clk) begin
+ main_maccore_ethphy_rx_ctl_reg <= main_maccore_ethphy_rx_ctl;
+ main_maccore_ethphy_rx_data_reg <= main_maccore_ethphy_rx_data;
+ main_maccore_ethphy_rx_ctl_reg_d <= main_maccore_ethphy_rx_ctl_reg;
+ main_maccore_ethphy_source_valid <= main_maccore_ethphy_rx_ctl_reg[0];
+ main_maccore_ethphy_source_payload_data <= main_maccore_ethphy_rx_data_reg;
+ if ((main_maccore_ethphy_rx_ctl == 1'd0)) begin
+ main_maccore_ethphy_link_status <= main_maccore_ethphy_rx_data[0];
+ main_maccore_ethphy_clock_speed <= main_maccore_ethphy_rx_data[2:1];
+ main_maccore_ethphy_duplex_status <= main_maccore_ethphy_rx_data[3];
+ end
+ builder_liteethmacpreamblechecker_state <= builder_liteethmacpreamblechecker_next_state;
+ if (main_liteethmaccrc32checker_crc_ce) begin
+ main_liteethmaccrc32checker_crc_reg <= main_liteethmaccrc32checker_crc_next;
+ end
+ if (main_liteethmaccrc32checker_crc_reset) begin
+ main_liteethmaccrc32checker_crc_reg <= 32'd4294967295;
+ end
+ if (((main_liteethmaccrc32checker_syncfifo_syncfifo_we & main_liteethmaccrc32checker_syncfifo_syncfifo_writable) & (~main_liteethmaccrc32checker_syncfifo_replace))) begin
+ if ((main_liteethmaccrc32checker_syncfifo_produce == 3'd4)) begin
+ main_liteethmaccrc32checker_syncfifo_produce <= 1'd0;
+ end else begin
+ main_liteethmaccrc32checker_syncfifo_produce <= (main_liteethmaccrc32checker_syncfifo_produce + 1'd1);
+ end
+ end
+ if (main_liteethmaccrc32checker_syncfifo_do_read) begin
+ if ((main_liteethmaccrc32checker_syncfifo_consume == 3'd4)) begin
+ main_liteethmaccrc32checker_syncfifo_consume <= 1'd0;
+ end else begin
+ main_liteethmaccrc32checker_syncfifo_consume <= (main_liteethmaccrc32checker_syncfifo_consume + 1'd1);
+ end
+ end
+ if (((main_liteethmaccrc32checker_syncfifo_syncfifo_we & main_liteethmaccrc32checker_syncfifo_syncfifo_writable) & (~main_liteethmaccrc32checker_syncfifo_replace))) begin
+ if ((~main_liteethmaccrc32checker_syncfifo_do_read)) begin
+ main_liteethmaccrc32checker_syncfifo_level <= (main_liteethmaccrc32checker_syncfifo_level + 1'd1);
+ end
+ end else begin
+ if (main_liteethmaccrc32checker_syncfifo_do_read) begin
+ main_liteethmaccrc32checker_syncfifo_level <= (main_liteethmaccrc32checker_syncfifo_level - 1'd1);
+ end
+ end
+ if (main_liteethmaccrc32checker_fifo_reset) begin
+ main_liteethmaccrc32checker_syncfifo_level <= 3'd0;
+ main_liteethmaccrc32checker_syncfifo_produce <= 3'd0;
+ main_liteethmaccrc32checker_syncfifo_consume <= 3'd0;
+ end
+ builder_liteethmaccrc32checker_state <= builder_liteethmaccrc32checker_next_state;
+ if (((~main_crc32_checker_source_valid) | main_crc32_checker_source_ready)) begin
+ main_crc32_checker_source_valid <= main_crc32_checker_sink_valid;
+ main_crc32_checker_source_first <= main_crc32_checker_sink_first;
+ main_crc32_checker_source_last <= main_crc32_checker_sink_last;
+ main_crc32_checker_source_payload_data <= main_crc32_checker_sink_payload_data;
+ main_crc32_checker_source_payload_last_be <= main_crc32_checker_sink_payload_last_be;
+ main_crc32_checker_source_payload_error <= main_crc32_checker_sink_payload_error;
+ end
+ if (main_ps_preamble_error_i) begin
+ main_ps_preamble_error_toggle_i <= (~main_ps_preamble_error_toggle_i);
+ end
+ if (main_ps_crc_error_i) begin
+ main_ps_crc_error_toggle_i <= (~main_ps_crc_error_toggle_i);
+ end
+ if (main_rx_converter_converter_source_ready) begin
+ main_rx_converter_converter_strobe_all <= 1'd0;
+ end
+ if (main_rx_converter_converter_load_part) begin
+ if (((main_rx_converter_converter_demux == 2'd3) | main_rx_converter_converter_sink_last)) begin
+ main_rx_converter_converter_demux <= 1'd0;
+ main_rx_converter_converter_strobe_all <= 1'd1;
+ end else begin
+ main_rx_converter_converter_demux <= (main_rx_converter_converter_demux + 1'd1);
+ end
+ end
+ if ((main_rx_converter_converter_source_valid & main_rx_converter_converter_source_ready)) begin
+ if ((main_rx_converter_converter_sink_valid & main_rx_converter_converter_sink_ready)) begin
+ main_rx_converter_converter_source_first <= main_rx_converter_converter_sink_first;
+ main_rx_converter_converter_source_last <= main_rx_converter_converter_sink_last;
+ end else begin
+ main_rx_converter_converter_source_first <= 1'd0;
+ main_rx_converter_converter_source_last <= 1'd0;
+ end
+ end else begin
+ if ((main_rx_converter_converter_sink_valid & main_rx_converter_converter_sink_ready)) begin
+ main_rx_converter_converter_source_first <= (main_rx_converter_converter_sink_first | main_rx_converter_converter_source_first);
+ main_rx_converter_converter_source_last <= (main_rx_converter_converter_sink_last | main_rx_converter_converter_source_last);
+ end
+ end
+ if (main_rx_converter_converter_load_part) begin
+ case (main_rx_converter_converter_demux)
+ 1'd0: begin
+ main_rx_converter_converter_source_payload_data[9:0] <= main_rx_converter_converter_sink_payload_data;
+ end
+ 1'd1: begin
+ main_rx_converter_converter_source_payload_data[19:10] <= main_rx_converter_converter_sink_payload_data;
+ end
+ 2'd2: begin
+ main_rx_converter_converter_source_payload_data[29:20] <= main_rx_converter_converter_sink_payload_data;
+ end
+ 2'd3: begin
+ main_rx_converter_converter_source_payload_data[39:30] <= main_rx_converter_converter_sink_payload_data;
+ end
+ endcase
+ end
+ if (main_rx_converter_converter_load_part) begin
+ main_rx_converter_converter_source_payload_valid_token_count <= (main_rx_converter_converter_demux + 1'd1);
+ end
+ main_rx_cdc_cdc_graycounter0_q_binary <= main_rx_cdc_cdc_graycounter0_q_next_binary;
+ main_rx_cdc_cdc_graycounter0_q <= main_rx_cdc_cdc_graycounter0_q_next;
+ if (eth_rx_rst) begin
+ main_maccore_ethphy_source_valid <= 1'd0;
+ main_maccore_ethphy_source_payload_data <= 8'd0;
+ main_maccore_ethphy_link_status <= 1'd0;
+ main_maccore_ethphy_clock_speed <= 1'd0;
+ main_maccore_ethphy_duplex_status <= 1'd0;
+ main_maccore_ethphy_rx_ctl_reg <= 2'd0;
+ main_maccore_ethphy_rx_data_reg <= 8'd0;
+ main_maccore_ethphy_rx_ctl_reg_d <= 2'd0;
+ main_liteethmaccrc32checker_crc_reg <= 32'd4294967295;
+ main_liteethmaccrc32checker_syncfifo_level <= 3'd0;
+ main_liteethmaccrc32checker_syncfifo_produce <= 3'd0;
+ main_liteethmaccrc32checker_syncfifo_consume <= 3'd0;
+ main_crc32_checker_source_valid <= 1'd0;
+ main_crc32_checker_source_payload_data <= 8'd0;
+ main_crc32_checker_source_payload_last_be <= 1'd0;
+ main_crc32_checker_source_payload_error <= 1'd0;
+ main_rx_converter_converter_source_payload_data <= 40'd0;
+ main_rx_converter_converter_source_payload_valid_token_count <= 3'd0;
+ main_rx_converter_converter_demux <= 2'd0;
+ main_rx_converter_converter_strobe_all <= 1'd0;
+ main_rx_cdc_cdc_graycounter0_q <= 6'd0;
+ main_rx_cdc_cdc_graycounter0_q_binary <= 6'd0;
+ builder_liteethmacpreamblechecker_state <= 1'd0;
+ builder_liteethmaccrc32checker_state <= 2'd0;
+ end
+ builder_multiregimpl6_regs0 <= main_rx_cdc_cdc_graycounter1_q;
+ builder_multiregimpl6_regs1 <= builder_multiregimpl6_regs0;
+end
+
+always @(posedge eth_tx_clk) begin
+ builder_liteethmacgap_state <= builder_liteethmacgap_next_state;
+ if (main_tx_gap_inserter_counter_liteethmacgap_next_value_ce) begin
+ main_tx_gap_inserter_counter <= main_tx_gap_inserter_counter_liteethmacgap_next_value;
+ end
+ builder_liteethmacpreambleinserter_state <= builder_liteethmacpreambleinserter_next_state;
+ if (main_preamble_inserter_count_liteethmacpreambleinserter_next_value_ce) begin
+ main_preamble_inserter_count <= main_preamble_inserter_count_liteethmacpreambleinserter_next_value;
+ end
+ if (main_liteethmaccrc32inserter_is_ongoing0) begin
+ main_liteethmaccrc32inserter_cnt <= 2'd3;
+ end else begin
+ if ((main_liteethmaccrc32inserter_is_ongoing1 & (~main_liteethmaccrc32inserter_cnt_done))) begin
+ main_liteethmaccrc32inserter_cnt <= (main_liteethmaccrc32inserter_cnt - main_liteethmaccrc32inserter_source_ready);
+ end
+ end
+ if (main_liteethmaccrc32inserter_ce) begin
+ main_liteethmaccrc32inserter_reg <= main_liteethmaccrc32inserter_next;
+ end
+ if (main_liteethmaccrc32inserter_reset) begin
+ main_liteethmaccrc32inserter_reg <= 32'd4294967295;
+ end
+ builder_liteethmaccrc32inserter_state <= builder_liteethmaccrc32inserter_next_state;
+ if (((~main_crc32_inserter_source_valid) | main_crc32_inserter_source_ready)) begin
+ main_crc32_inserter_source_valid <= main_crc32_inserter_sink_valid;
+ main_crc32_inserter_source_first <= main_crc32_inserter_sink_first;
+ main_crc32_inserter_source_last <= main_crc32_inserter_sink_last;
+ main_crc32_inserter_source_payload_data <= main_crc32_inserter_sink_payload_data;
+ main_crc32_inserter_source_payload_last_be <= main_crc32_inserter_sink_payload_last_be;
+ main_crc32_inserter_source_payload_error <= main_crc32_inserter_sink_payload_error;
+ end
+ builder_liteethmacpaddinginserter_state <= builder_liteethmacpaddinginserter_next_state;
+ if (main_padding_inserter_counter_liteethmacpaddinginserter_next_value_ce) begin
+ main_padding_inserter_counter <= main_padding_inserter_counter_liteethmacpaddinginserter_next_value;
+ end
+ builder_liteethmactxlastbe_state <= builder_liteethmactxlastbe_next_state;
+ if ((main_tx_converter_converter_source_valid & main_tx_converter_converter_source_ready)) begin
+ if (main_tx_converter_converter_last) begin
+ main_tx_converter_converter_mux <= 1'd0;
+ end else begin
+ main_tx_converter_converter_mux <= (main_tx_converter_converter_mux + 1'd1);
+ end
+ end
+ main_tx_cdc_cdc_graycounter1_q_binary <= main_tx_cdc_cdc_graycounter1_q_next_binary;
+ main_tx_cdc_cdc_graycounter1_q <= main_tx_cdc_cdc_graycounter1_q_next;
+ if (eth_tx_rst) begin
+ main_liteethmaccrc32inserter_reg <= 32'd4294967295;
+ main_liteethmaccrc32inserter_cnt <= 2'd3;
+ main_crc32_inserter_source_valid <= 1'd0;
+ main_crc32_inserter_source_payload_data <= 8'd0;
+ main_crc32_inserter_source_payload_last_be <= 1'd0;
+ main_crc32_inserter_source_payload_error <= 1'd0;
+ main_padding_inserter_counter <= 16'd0;
+ main_tx_converter_converter_mux <= 2'd0;
+ main_tx_cdc_cdc_graycounter1_q <= 6'd0;
+ main_tx_cdc_cdc_graycounter1_q_binary <= 6'd0;
+ builder_liteethmacgap_state <= 1'd0;
+ builder_liteethmacpreambleinserter_state <= 2'd0;
+ builder_liteethmaccrc32inserter_state <= 2'd0;
+ builder_liteethmacpaddinginserter_state <= 1'd0;
+ builder_liteethmactxlastbe_state <= 1'd0;
+ end
+ builder_multiregimpl3_regs0 <= main_tx_cdc_cdc_graycounter0_q;
+ builder_multiregimpl3_regs1 <= builder_multiregimpl3_regs0;
+end
+
+always @(posedge por_clk) begin
+ main_maccore_int_rst <= sys_reset;
+end
+
+always @(posedge sys_clk) begin
+ if ((main_maccore_maccore_bus_errors != 32'd4294967295)) begin
+ if (main_maccore_maccore_bus_error) begin
+ main_maccore_maccore_bus_errors <= (main_maccore_maccore_bus_errors + 1'd1);
+ end
+ end
+ if (main_ps_preamble_error_o) begin
+ main_preamble_errors_status <= (main_preamble_errors_status + 1'd1);
+ end
+ if (main_ps_crc_error_o) begin
+ main_crc_errors_status <= (main_crc_errors_status + 1'd1);
+ end
+ main_ps_preamble_error_toggle_o_r <= main_ps_preamble_error_toggle_o;
+ main_ps_crc_error_toggle_o_r <= main_ps_crc_error_toggle_o;
+ main_tx_cdc_cdc_graycounter0_q_binary <= main_tx_cdc_cdc_graycounter0_q_next_binary;
+ main_tx_cdc_cdc_graycounter0_q <= main_tx_cdc_cdc_graycounter0_q_next;
+ main_rx_cdc_cdc_graycounter1_q_binary <= main_rx_cdc_cdc_graycounter1_q_next_binary;
+ main_rx_cdc_cdc_graycounter1_q <= main_rx_cdc_cdc_graycounter1_q_next;
+ if (main_writer_slot_ce) begin
+ main_writer_slot <= (main_writer_slot + 1'd1);
+ end
+ if (((main_writer_stat_fifo_syncfifo_we & main_writer_stat_fifo_syncfifo_writable) & (~main_writer_stat_fifo_replace))) begin
+ main_writer_stat_fifo_produce <= (main_writer_stat_fifo_produce + 1'd1);
+ end
+ if (main_writer_stat_fifo_do_read) begin
+ main_writer_stat_fifo_consume <= (main_writer_stat_fifo_consume + 1'd1);
+ end
+ if (((main_writer_stat_fifo_syncfifo_we & main_writer_stat_fifo_syncfifo_writable) & (~main_writer_stat_fifo_replace))) begin
+ if ((~main_writer_stat_fifo_do_read)) begin
+ main_writer_stat_fifo_level <= (main_writer_stat_fifo_level + 1'd1);
+ end
+ end else begin
+ if (main_writer_stat_fifo_do_read) begin
+ main_writer_stat_fifo_level <= (main_writer_stat_fifo_level - 1'd1);
+ end
+ end
+ builder_liteethmacsramwriter_state <= builder_liteethmacsramwriter_next_state;
+ if (main_writer_counter_t_next_value_ce) begin
+ main_writer_counter <= main_writer_counter_t_next_value;
+ end
+ if (main_writer_errors_status_f_next_value_ce) begin
+ main_writer_errors_status <= main_writer_errors_status_f_next_value;
+ end
+ if (main_reader_eventsourcepulse_clear) begin
+ main_reader_eventsourcepulse_pending <= 1'd0;
+ end
+ if (main_reader_eventsourcepulse_trigger) begin
+ main_reader_eventsourcepulse_pending <= 1'd1;
+ end
+ if (((main_reader_cmd_fifo_syncfifo_we & main_reader_cmd_fifo_syncfifo_writable) & (~main_reader_cmd_fifo_replace))) begin
+ main_reader_cmd_fifo_produce <= (main_reader_cmd_fifo_produce + 1'd1);
+ end
+ if (main_reader_cmd_fifo_do_read) begin
+ main_reader_cmd_fifo_consume <= (main_reader_cmd_fifo_consume + 1'd1);
+ end
+ if (((main_reader_cmd_fifo_syncfifo_we & main_reader_cmd_fifo_syncfifo_writable) & (~main_reader_cmd_fifo_replace))) begin
+ if ((~main_reader_cmd_fifo_do_read)) begin
+ main_reader_cmd_fifo_level <= (main_reader_cmd_fifo_level + 1'd1);
+ end
+ end else begin
+ if (main_reader_cmd_fifo_do_read) begin
+ main_reader_cmd_fifo_level <= (main_reader_cmd_fifo_level - 1'd1);
+ end
+ end
+ builder_liteethmacsramreader_state <= builder_liteethmacsramreader_next_state;
+ if (main_reader_counter_next_value_ce) begin
+ main_reader_counter <= main_reader_counter_next_value;
+ end
+ main_interface0_ack <= 1'd0;
+ if (((main_interface0_cyc & main_interface0_stb) & (~main_interface0_ack))) begin
+ main_interface0_ack <= 1'd1;
+ end
+ main_interface1_ack <= 1'd0;
+ if (((main_interface1_cyc & main_interface1_stb) & (~main_interface1_ack))) begin
+ main_interface1_ack <= 1'd1;
+ end
+ main_interface2_ack <= 1'd0;
+ if (((main_interface2_cyc & main_interface2_stb) & (~main_interface2_ack))) begin
+ main_interface2_ack <= 1'd1;
+ end
+ main_interface3_ack <= 1'd0;
+ if (((main_interface3_cyc & main_interface3_stb) & (~main_interface3_ack))) begin
+ main_interface3_ack <= 1'd1;
+ end
+ main_slave_sel_r <= main_slave_sel;
+ builder_state <= builder_next_state;
+ builder_slave_sel_r <= builder_slave_sel;
+ if (builder_wait) begin
+ if ((~builder_done)) begin
+ builder_count <= (builder_count - 1'd1);
+ end
+ end else begin
+ builder_count <= 20'd1000000;
+ end
+ builder_interface0_bank_bus_dat_r <= 1'd0;
+ if (builder_csrbank0_sel) begin
+ case (builder_interface0_bank_bus_adr[8:0])
+ 1'd0: begin
+ builder_interface0_bank_bus_dat_r <= builder_csrbank0_reset0_w;
+ end
+ 1'd1: begin
+ builder_interface0_bank_bus_dat_r <= builder_csrbank0_scratch0_w;
+ end
+ 2'd2: begin
+ builder_interface0_bank_bus_dat_r <= builder_csrbank0_bus_errors_w;
+ end
+ endcase
+ end
+ if (builder_csrbank0_reset0_re) begin
+ main_maccore_maccore_reset_storage[1:0] <= builder_csrbank0_reset0_r;
+ end
+ main_maccore_maccore_reset_re <= builder_csrbank0_reset0_re;
+ if (builder_csrbank0_scratch0_re) begin
+ main_maccore_maccore_scratch_storage[31:0] <= builder_csrbank0_scratch0_r;
+ end
+ main_maccore_maccore_scratch_re <= builder_csrbank0_scratch0_re;
+ main_maccore_maccore_bus_errors_re <= builder_csrbank0_bus_errors_re;
+ builder_interface1_bank_bus_dat_r <= 1'd0;
+ if (builder_csrbank1_sel) begin
+ case (builder_interface1_bank_bus_adr[8:0])
+ 1'd0: begin
+ builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_writer_slot_w;
+ end
+ 1'd1: begin
+ builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_writer_length_w;
+ end
+ 2'd2: begin
+ builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_writer_errors_w;
+ end
+ 2'd3: begin
+ builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_writer_ev_status_w;
+ end
+ 3'd4: begin
+ builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_writer_ev_pending_w;
+ end
+ 3'd5: begin
+ builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_writer_ev_enable0_w;
+ end
+ 3'd6: begin
+ builder_interface1_bank_bus_dat_r <= main_reader_start_start_w;
+ end
+ 3'd7: begin
+ builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_reader_ready_w;
+ end
+ 4'd8: begin
+ builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_reader_level_w;
+ end
+ 4'd9: begin
+ builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_reader_slot0_w;
+ end
+ 4'd10: begin
+ builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_reader_length0_w;
+ end
+ 4'd11: begin
+ builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_reader_ev_status_w;
+ end
+ 4'd12: begin
+ builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_reader_ev_pending_w;
+ end
+ 4'd13: begin
+ builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_reader_ev_enable0_w;
+ end
+ 4'd14: begin
+ builder_interface1_bank_bus_dat_r <= builder_csrbank1_preamble_crc_w;
+ end
+ 4'd15: begin
+ builder_interface1_bank_bus_dat_r <= builder_csrbank1_preamble_errors_w;
+ end
+ 5'd16: begin
+ builder_interface1_bank_bus_dat_r <= builder_csrbank1_crc_errors_w;
+ end
+ endcase
+ end
+ main_writer_slot_re <= builder_csrbank1_sram_writer_slot_re;
+ main_writer_length_re <= builder_csrbank1_sram_writer_length_re;
+ main_writer_errors_re <= builder_csrbank1_sram_writer_errors_re;
+ main_writer_status_re <= builder_csrbank1_sram_writer_ev_status_re;
+ if (builder_csrbank1_sram_writer_ev_pending_re) begin
+ main_writer_pending_r <= builder_csrbank1_sram_writer_ev_pending_r;
+ end
+ main_writer_pending_re <= builder_csrbank1_sram_writer_ev_pending_re;
+ if (builder_csrbank1_sram_writer_ev_enable0_re) begin
+ main_writer_enable_storage <= builder_csrbank1_sram_writer_ev_enable0_r;
+ end
+ main_writer_enable_re <= builder_csrbank1_sram_writer_ev_enable0_re;
+ main_reader_ready_re <= builder_csrbank1_sram_reader_ready_re;
+ main_reader_level_re <= builder_csrbank1_sram_reader_level_re;
+ if (builder_csrbank1_sram_reader_slot0_re) begin
+ main_reader_slot_storage <= builder_csrbank1_sram_reader_slot0_r;
+ end
+ main_reader_slot_re <= builder_csrbank1_sram_reader_slot0_re;
+ if (builder_csrbank1_sram_reader_length0_re) begin
+ main_reader_length_storage[10:0] <= builder_csrbank1_sram_reader_length0_r;
+ end
+ main_reader_length_re <= builder_csrbank1_sram_reader_length0_re;
+ main_reader_status_re <= builder_csrbank1_sram_reader_ev_status_re;
+ if (builder_csrbank1_sram_reader_ev_pending_re) begin
+ main_reader_pending_r <= builder_csrbank1_sram_reader_ev_pending_r;
+ end
+ main_reader_pending_re <= builder_csrbank1_sram_reader_ev_pending_re;
+ if (builder_csrbank1_sram_reader_ev_enable0_re) begin
+ main_reader_enable_storage <= builder_csrbank1_sram_reader_ev_enable0_r;
+ end
+ main_reader_enable_re <= builder_csrbank1_sram_reader_ev_enable0_re;
+ main_preamble_crc_re <= builder_csrbank1_preamble_crc_re;
+ main_preamble_errors_re <= builder_csrbank1_preamble_errors_re;
+ main_crc_errors_re <= builder_csrbank1_crc_errors_re;
+ builder_interface2_bank_bus_dat_r <= 1'd0;
+ if (builder_csrbank2_sel) begin
+ case (builder_interface2_bank_bus_adr[8:0])
+ 1'd0: begin
+ builder_interface2_bank_bus_dat_r <= builder_csrbank2_crg_reset0_w;
+ end
+ 1'd1: begin
+ builder_interface2_bank_bus_dat_r <= builder_csrbank2_rx_inband_status_w;
+ end
+ 2'd2: begin
+ builder_interface2_bank_bus_dat_r <= builder_csrbank2_mdio_w0_w;
+ end
+ 2'd3: begin
+ builder_interface2_bank_bus_dat_r <= builder_csrbank2_mdio_r_w;
+ end
+ endcase
+ end
+ if (builder_csrbank2_crg_reset0_re) begin
+ main_maccore_ethphy_reset_storage <= builder_csrbank2_crg_reset0_r;
+ end
+ main_maccore_ethphy_reset_re <= builder_csrbank2_crg_reset0_re;
+ main_maccore_ethphy_re <= builder_csrbank2_rx_inband_status_re;
+ if (builder_csrbank2_mdio_w0_re) begin
+ main_maccore_ethphy__w_storage[2:0] <= builder_csrbank2_mdio_w0_r;
+ end
+ main_maccore_ethphy__w_re <= builder_csrbank2_mdio_w0_re;
+ main_maccore_ethphy__r_re <= builder_csrbank2_mdio_r_re;
+ if (sys_rst) begin
+ main_maccore_maccore_reset_storage <= 2'd0;
+ main_maccore_maccore_reset_re <= 1'd0;
+ main_maccore_maccore_scratch_storage <= 32'd305419896;
+ main_maccore_maccore_scratch_re <= 1'd0;
+ main_maccore_maccore_bus_errors_re <= 1'd0;
+ main_maccore_maccore_bus_errors <= 32'd0;
+ main_maccore_ethphy_reset_storage <= 1'd0;
+ main_maccore_ethphy_reset_re <= 1'd0;
+ main_maccore_ethphy_re <= 1'd0;
+ main_maccore_ethphy__w_storage <= 3'd0;
+ main_maccore_ethphy__w_re <= 1'd0;
+ main_maccore_ethphy__r_re <= 1'd0;
+ main_preamble_crc_re <= 1'd0;
+ main_preamble_errors_status <= 32'd0;
+ main_preamble_errors_re <= 1'd0;
+ main_crc_errors_status <= 32'd0;
+ main_crc_errors_re <= 1'd0;
+ main_tx_cdc_cdc_graycounter0_q <= 6'd0;
+ main_tx_cdc_cdc_graycounter0_q_binary <= 6'd0;
+ main_rx_cdc_cdc_graycounter1_q <= 6'd0;
+ main_rx_cdc_cdc_graycounter1_q_binary <= 6'd0;
+ main_writer_slot_re <= 1'd0;
+ main_writer_length_re <= 1'd0;
+ main_writer_errors_status <= 32'd0;
+ main_writer_errors_re <= 1'd0;
+ main_writer_status_re <= 1'd0;
+ main_writer_pending_re <= 1'd0;
+ main_writer_pending_r <= 1'd0;
+ main_writer_enable_storage <= 1'd0;
+ main_writer_enable_re <= 1'd0;
+ main_writer_counter <= 32'd0;
+ main_writer_slot <= 1'd0;
+ main_writer_stat_fifo_level <= 2'd0;
+ main_writer_stat_fifo_produce <= 1'd0;
+ main_writer_stat_fifo_consume <= 1'd0;
+ main_reader_ready_re <= 1'd0;
+ main_reader_level_re <= 1'd0;
+ main_reader_slot_re <= 1'd0;
+ main_reader_length_re <= 1'd0;
+ main_reader_eventsourcepulse_pending <= 1'd0;
+ main_reader_status_re <= 1'd0;
+ main_reader_pending_re <= 1'd0;
+ main_reader_pending_r <= 1'd0;
+ main_reader_enable_storage <= 1'd0;
+ main_reader_enable_re <= 1'd0;
+ main_reader_cmd_fifo_level <= 2'd0;
+ main_reader_cmd_fifo_produce <= 1'd0;
+ main_reader_cmd_fifo_consume <= 1'd0;
+ main_reader_counter <= 11'd0;
+ main_interface0_ack <= 1'd0;
+ main_interface1_ack <= 1'd0;
+ main_interface2_ack <= 1'd0;
+ main_interface3_ack <= 1'd0;
+ main_slave_sel_r <= 4'd0;
+ builder_liteethmacsramwriter_state <= 3'd0;
+ builder_liteethmacsramreader_state <= 2'd0;
+ builder_slave_sel_r <= 2'd0;
+ builder_count <= 20'd1000000;
+ builder_state <= 1'd0;
+ end
+ builder_multiregimpl0_regs0 <= main_maccore_ethphy_data_r;
+ builder_multiregimpl0_regs1 <= builder_multiregimpl0_regs0;
+ builder_multiregimpl1_regs0 <= main_ps_preamble_error_toggle_i;
+ builder_multiregimpl1_regs1 <= builder_multiregimpl1_regs0;
+ builder_multiregimpl2_regs0 <= main_ps_crc_error_toggle_i;
+ builder_multiregimpl2_regs1 <= builder_multiregimpl2_regs0;
+ builder_multiregimpl4_regs0 <= main_tx_cdc_cdc_graycounter1_q;
+ builder_multiregimpl4_regs1 <= builder_multiregimpl4_regs0;
+ builder_multiregimpl5_regs0 <= main_rx_cdc_cdc_graycounter0_q;
+ builder_multiregimpl5_regs1 <= builder_multiregimpl5_regs0;
+end
+
+
+//------------------------------------------------------------------------------
+// Specialized Logic
+//------------------------------------------------------------------------------
+
+DELAYG #(
+ .DEL_MODE("SCLK_ALIGNED"),
+ .DEL_VALUE(7'd80)
+) DELAYG (
+ .A(main_maccore_ethphy_eth_tx_clk_o),
+ .Z(rgmii_eth_clocks_tx)
+);
+
+DELAYG #(
+ .DEL_MODE("SCLK_ALIGNED"),
+ .DEL_VALUE(1'd0)
+) DELAYG_1 (
+ .A(main_maccore_ethphy_tx_ctl_oddrx1f),
+ .Z(rgmii_eth_tx_ctl)
+);
+
+DELAYG #(
+ .DEL_MODE("SCLK_ALIGNED"),
+ .DEL_VALUE(1'd0)
+) DELAYG_2 (
+ .A(main_maccore_ethphy_tx_data_oddrx1f[0]),
+ .Z(rgmii_eth_tx_data[0])
+);
+
+DELAYG #(
+ .DEL_MODE("SCLK_ALIGNED"),
+ .DEL_VALUE(1'd0)
+) DELAYG_3 (
+ .A(main_maccore_ethphy_tx_data_oddrx1f[1]),
+ .Z(rgmii_eth_tx_data[1])
+);
+
+DELAYG #(
+ .DEL_MODE("SCLK_ALIGNED"),
+ .DEL_VALUE(1'd0)
+) DELAYG_4 (
+ .A(main_maccore_ethphy_tx_data_oddrx1f[2]),
+ .Z(rgmii_eth_tx_data[2])
+);
+
+DELAYG #(
+ .DEL_MODE("SCLK_ALIGNED"),
+ .DEL_VALUE(1'd0)
+) DELAYG_5 (
+ .A(main_maccore_ethphy_tx_data_oddrx1f[3]),
+ .Z(rgmii_eth_tx_data[3])
+);
+
+DELAYG #(
+ .DEL_MODE("SCLK_ALIGNED"),
+ .DEL_VALUE(7'd80)
+) DELAYG_6 (
+ .A(rgmii_eth_rx_ctl),
+ .Z(main_maccore_ethphy_rx_ctl_delayf)
+);
+
+DELAYG #(
+ .DEL_MODE("SCLK_ALIGNED"),
+ .DEL_VALUE(7'd80)
+) DELAYG_7 (
+ .A(rgmii_eth_rx_data[0]),
+ .Z(main_maccore_ethphy_rx_data_delayf[0])
+);
+
+DELAYG #(
+ .DEL_MODE("SCLK_ALIGNED"),
+ .DEL_VALUE(7'd80)
+) DELAYG_8 (
+ .A(rgmii_eth_rx_data[1]),
+ .Z(main_maccore_ethphy_rx_data_delayf[1])
+);
+
+DELAYG #(
+ .DEL_MODE("SCLK_ALIGNED"),
+ .DEL_VALUE(7'd80)
+) DELAYG_9 (
+ .A(rgmii_eth_rx_data[2]),
+ .Z(main_maccore_ethphy_rx_data_delayf[2])
+);
+
+DELAYG #(
+ .DEL_MODE("SCLK_ALIGNED"),
+ .DEL_VALUE(7'd80)
+) DELAYG_10 (
+ .A(rgmii_eth_rx_data[3]),
+ .Z(main_maccore_ethphy_rx_data_delayf[3])
+);
+
+assign rgmii_eth_mdio = main_maccore_ethphy_data_oe ? main_maccore_ethphy_data_w : 1'bz;
+assign main_maccore_ethphy_data_r = rgmii_eth_mdio;
+
+//------------------------------------------------------------------------------
+// Memory storage: 5-words x 12-bit
+//------------------------------------------------------------------------------
+// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 12
+// Port 1 | Read: Async | Write: ---- |
+reg [11:0] storage[0:4];
+reg [11:0] storage_dat0;
+always @(posedge eth_rx_clk) begin
+ if (main_liteethmaccrc32checker_syncfifo_wrport_we)
+ storage[main_liteethmaccrc32checker_syncfifo_wrport_adr] <= main_liteethmaccrc32checker_syncfifo_wrport_dat_w;
+ storage_dat0 <= storage[main_liteethmaccrc32checker_syncfifo_wrport_adr];
+end
+always @(posedge eth_rx_clk) begin
+end
+assign main_liteethmaccrc32checker_syncfifo_wrport_dat_r = storage_dat0;
+assign main_liteethmaccrc32checker_syncfifo_rdport_dat_r = storage[main_liteethmaccrc32checker_syncfifo_rdport_adr];
+
+
+//------------------------------------------------------------------------------
+// Memory storage_1: 32-words x 42-bit
+//------------------------------------------------------------------------------
+// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 42
+// Port 1 | Read: Sync | Write: ---- |
+reg [41:0] storage_1[0:31];
+reg [41:0] storage_1_dat0;
+reg [41:0] storage_1_dat1;
+always @(posedge sys_clk) begin
+ if (main_tx_cdc_cdc_wrport_we)
+ storage_1[main_tx_cdc_cdc_wrport_adr] <= main_tx_cdc_cdc_wrport_dat_w;
+ storage_1_dat0 <= storage_1[main_tx_cdc_cdc_wrport_adr];
+end
+always @(posedge eth_tx_clk) begin
+ storage_1_dat1 <= storage_1[main_tx_cdc_cdc_rdport_adr];
+end
+assign main_tx_cdc_cdc_wrport_dat_r = storage_1_dat0;
+assign main_tx_cdc_cdc_rdport_dat_r = storage_1_dat1;
+
+
+//------------------------------------------------------------------------------
+// Memory storage_2: 32-words x 42-bit
+//------------------------------------------------------------------------------
+// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 42
+// Port 1 | Read: Sync | Write: ---- |
+reg [41:0] storage_2[0:31];
+reg [41:0] storage_2_dat0;
+reg [41:0] storage_2_dat1;
+always @(posedge eth_rx_clk) begin
+ if (main_rx_cdc_cdc_wrport_we)
+ storage_2[main_rx_cdc_cdc_wrport_adr] <= main_rx_cdc_cdc_wrport_dat_w;
+ storage_2_dat0 <= storage_2[main_rx_cdc_cdc_wrport_adr];
+end
+always @(posedge sys_clk) begin
+ storage_2_dat1 <= storage_2[main_rx_cdc_cdc_rdport_adr];
+end
+assign main_rx_cdc_cdc_wrport_dat_r = storage_2_dat0;
+assign main_rx_cdc_cdc_rdport_dat_r = storage_2_dat1;
+
+
+//------------------------------------------------------------------------------
+// Memory storage_3: 2-words x 35-bit
+//------------------------------------------------------------------------------
+// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 35
+// Port 1 | Read: Async | Write: ---- |
+reg [34:0] storage_3[0:1];
+reg [34:0] storage_3_dat0;
+always @(posedge sys_clk) begin
+ if (main_writer_stat_fifo_wrport_we)
+ storage_3[main_writer_stat_fifo_wrport_adr] <= main_writer_stat_fifo_wrport_dat_w;
+ storage_3_dat0 <= storage_3[main_writer_stat_fifo_wrport_adr];
+end
+always @(posedge sys_clk) begin
+end
+assign main_writer_stat_fifo_wrport_dat_r = storage_3_dat0;
+assign main_writer_stat_fifo_rdport_dat_r = storage_3[main_writer_stat_fifo_rdport_adr];
+
+
+//------------------------------------------------------------------------------
+// Memory storage_4: 2-words x 14-bit
+//------------------------------------------------------------------------------
+// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 14
+// Port 1 | Read: Async | Write: ---- |
+reg [13:0] storage_4[0:1];
+reg [13:0] storage_4_dat0;
+always @(posedge sys_clk) begin
+ if (main_reader_cmd_fifo_wrport_we)
+ storage_4[main_reader_cmd_fifo_wrport_adr] <= main_reader_cmd_fifo_wrport_dat_w;
+ storage_4_dat0 <= storage_4[main_reader_cmd_fifo_wrport_adr];
+end
+always @(posedge sys_clk) begin
+end
+assign main_reader_cmd_fifo_wrport_dat_r = storage_4_dat0;
+assign main_reader_cmd_fifo_rdport_dat_r = storage_4[main_reader_cmd_fifo_rdport_adr];
+
+
+//------------------------------------------------------------------------------
+// Memory mem_grain0: 383-words x 8-bit
+//------------------------------------------------------------------------------
+// Port 0 | Read: Sync | Write: Sync | Mode: Write-First | Write-Granularity: 8
+// Port 1 | Read: Sync | Write: ---- |
+reg [7:0] mem_grain0[0:382];
+reg [8:0] mem_grain0_adr0;
+reg [7:0] mem_grain0_dat1;
+always @(posedge sys_clk) begin
+ if (main_writer_memory0_we)
+ mem_grain0[main_writer_memory0_adr] <= main_writer_memory0_dat_w[7:0];
+ mem_grain0_adr0 <= main_writer_memory0_adr;
+end
+always @(posedge sys_clk) begin
+ mem_grain0_dat1 <= mem_grain0[main_sram0_adr0];
+end
+assign main_writer_memory0_dat_r[7:0] = mem_grain0[mem_grain0_adr0];
+assign main_sram0_dat_r0[7:0] = mem_grain0_dat1;
+
+
+//------------------------------------------------------------------------------
+// Memory mem_grain1: 383-words x 8-bit
+//------------------------------------------------------------------------------
+// Port 0 | Read: Sync | Write: Sync | Mode: Write-First | Write-Granularity: 8
+// Port 1 | Read: Sync | Write: ---- |
+reg [7:0] mem_grain1[0:382];
+reg [8:0] mem_grain1_adr0;
+reg [7:0] mem_grain1_dat1;
+always @(posedge sys_clk) begin
+ if (main_writer_memory0_we)
+ mem_grain1[main_writer_memory0_adr] <= main_writer_memory0_dat_w[15:8];
+ mem_grain1_adr0 <= main_writer_memory0_adr;
+end
+always @(posedge sys_clk) begin
+ mem_grain1_dat1 <= mem_grain1[main_sram0_adr0];
+end
+assign main_writer_memory0_dat_r[15:8] = mem_grain1[mem_grain1_adr0];
+assign main_sram0_dat_r0[15:8] = mem_grain1_dat1;
+
+
+//------------------------------------------------------------------------------
+// Memory mem_grain2: 383-words x 8-bit
+//------------------------------------------------------------------------------
+// Port 0 | Read: Sync | Write: Sync | Mode: Write-First | Write-Granularity: 8
+// Port 1 | Read: Sync | Write: ---- |
+reg [7:0] mem_grain2[0:382];
+reg [8:0] mem_grain2_adr0;
+reg [7:0] mem_grain2_dat1;
+always @(posedge sys_clk) begin
+ if (main_writer_memory0_we)
+ mem_grain2[main_writer_memory0_adr] <= main_writer_memory0_dat_w[23:16];
+ mem_grain2_adr0 <= main_writer_memory0_adr;
+end
+always @(posedge sys_clk) begin
+ mem_grain2_dat1 <= mem_grain2[main_sram0_adr0];
+end
+assign main_writer_memory0_dat_r[23:16] = mem_grain2[mem_grain2_adr0];
+assign main_sram0_dat_r0[23:16] = mem_grain2_dat1;
+
+
+//------------------------------------------------------------------------------
+// Memory mem_grain3: 383-words x 8-bit
+//------------------------------------------------------------------------------
+// Port 0 | Read: Sync | Write: Sync | Mode: Write-First | Write-Granularity: 8
+// Port 1 | Read: Sync | Write: ---- |
+reg [7:0] mem_grain3[0:382];
+reg [8:0] mem_grain3_adr0;
+reg [7:0] mem_grain3_dat1;
+always @(posedge sys_clk) begin
+ if (main_writer_memory0_we)
+ mem_grain3[main_writer_memory0_adr] <= main_writer_memory0_dat_w[31:24];
+ mem_grain3_adr0 <= main_writer_memory0_adr;
+end
+always @(posedge sys_clk) begin
+ mem_grain3_dat1 <= mem_grain3[main_sram0_adr0];
+end
+assign main_writer_memory0_dat_r[31:24] = mem_grain3[mem_grain3_adr0];
+assign main_sram0_dat_r0[31:24] = mem_grain3_dat1;
+
+
+//------------------------------------------------------------------------------
+// Memory mem_grain0_1: 383-words x 8-bit
+//------------------------------------------------------------------------------
+// Port 0 | Read: Sync | Write: Sync | Mode: Write-First | Write-Granularity: 8
+// Port 1 | Read: Sync | Write: ---- |
+reg [7:0] mem_grain0_1[0:382];
+reg [8:0] mem_grain0_1_adr0;
+reg [7:0] mem_grain0_1_dat1;
+always @(posedge sys_clk) begin
+ if (main_writer_memory1_we)
+ mem_grain0_1[main_writer_memory1_adr] <= main_writer_memory1_dat_w[7:0];
+ mem_grain0_1_adr0 <= main_writer_memory1_adr;
+end
+always @(posedge sys_clk) begin
+ mem_grain0_1_dat1 <= mem_grain0_1[main_sram1_adr0];
+end
+assign main_writer_memory1_dat_r[7:0] = mem_grain0_1[mem_grain0_1_adr0];
+assign main_sram1_dat_r0[7:0] = mem_grain0_1_dat1;
+
+
+//------------------------------------------------------------------------------
+// Memory mem_grain1_1: 383-words x 8-bit
+//------------------------------------------------------------------------------
+// Port 0 | Read: Sync | Write: Sync | Mode: Write-First | Write-Granularity: 8
+// Port 1 | Read: Sync | Write: ---- |
+reg [7:0] mem_grain1_1[0:382];
+reg [8:0] mem_grain1_1_adr0;
+reg [7:0] mem_grain1_1_dat1;
+always @(posedge sys_clk) begin
+ if (main_writer_memory1_we)
+ mem_grain1_1[main_writer_memory1_adr] <= main_writer_memory1_dat_w[15:8];
+ mem_grain1_1_adr0 <= main_writer_memory1_adr;
+end
+always @(posedge sys_clk) begin
+ mem_grain1_1_dat1 <= mem_grain1_1[main_sram1_adr0];
+end
+assign main_writer_memory1_dat_r[15:8] = mem_grain1_1[mem_grain1_1_adr0];
+assign main_sram1_dat_r0[15:8] = mem_grain1_1_dat1;
+
+
+//------------------------------------------------------------------------------
+// Memory mem_grain2_1: 383-words x 8-bit
+//------------------------------------------------------------------------------
+// Port 0 | Read: Sync | Write: Sync | Mode: Write-First | Write-Granularity: 8
+// Port 1 | Read: Sync | Write: ---- |
+reg [7:0] mem_grain2_1[0:382];
+reg [8:0] mem_grain2_1_adr0;
+reg [7:0] mem_grain2_1_dat1;
+always @(posedge sys_clk) begin
+ if (main_writer_memory1_we)
+ mem_grain2_1[main_writer_memory1_adr] <= main_writer_memory1_dat_w[23:16];
+ mem_grain2_1_adr0 <= main_writer_memory1_adr;
+end
+always @(posedge sys_clk) begin
+ mem_grain2_1_dat1 <= mem_grain2_1[main_sram1_adr0];
+end
+assign main_writer_memory1_dat_r[23:16] = mem_grain2_1[mem_grain2_1_adr0];
+assign main_sram1_dat_r0[23:16] = mem_grain2_1_dat1;
+
+
+//------------------------------------------------------------------------------
+// Memory mem_grain3_1: 383-words x 8-bit
+//------------------------------------------------------------------------------
+// Port 0 | Read: Sync | Write: Sync | Mode: Write-First | Write-Granularity: 8
+// Port 1 | Read: Sync | Write: ---- |
+reg [7:0] mem_grain3_1[0:382];
+reg [8:0] mem_grain3_1_adr0;
+reg [7:0] mem_grain3_1_dat1;
+always @(posedge sys_clk) begin
+ if (main_writer_memory1_we)
+ mem_grain3_1[main_writer_memory1_adr] <= main_writer_memory1_dat_w[31:24];
+ mem_grain3_1_adr0 <= main_writer_memory1_adr;
+end
+always @(posedge sys_clk) begin
+ mem_grain3_1_dat1 <= mem_grain3_1[main_sram1_adr0];
+end
+assign main_writer_memory1_dat_r[31:24] = mem_grain3_1[mem_grain3_1_adr0];
+assign main_sram1_dat_r0[31:24] = mem_grain3_1_dat1;
+
+
+//------------------------------------------------------------------------------
+// Memory mem_grain0_2: 383-words x 8-bit
+//------------------------------------------------------------------------------
+// Port 0 | Read: Sync | Write: ---- |
+// Port 1 | Read: Sync | Write: Sync | Mode: Write-First | Write-Granularity: 8
+reg [7:0] mem_grain0_2[0:382];
+reg [8:0] mem_grain0_2_adr0;
+reg [8:0] mem_grain0_2_adr1;
+always @(posedge sys_clk) begin
+ mem_grain0_2_adr0 <= main_reader_memory0_adr;
+end
+always @(posedge sys_clk) begin
+ if (main_sram0_we[0])
+ mem_grain0_2[main_sram0_adr1] <= main_sram0_dat_w[7:0];
+ mem_grain0_2_adr1 <= main_sram0_adr1;
+end
+assign main_reader_memory0_dat_r[7:0] = mem_grain0_2[mem_grain0_2_adr0];
+assign main_sram0_dat_r1[7:0] = mem_grain0_2[mem_grain0_2_adr1];
+
+
+//------------------------------------------------------------------------------
+// Memory mem_grain1_2: 383-words x 8-bit
+//------------------------------------------------------------------------------
+// Port 0 | Read: Sync | Write: ---- |
+// Port 1 | Read: Sync | Write: Sync | Mode: Write-First | Write-Granularity: 8
+reg [7:0] mem_grain1_2[0:382];
+reg [8:0] mem_grain1_2_adr0;
+reg [8:0] mem_grain1_2_adr1;
+always @(posedge sys_clk) begin
+ mem_grain1_2_adr0 <= main_reader_memory0_adr;
+end
+always @(posedge sys_clk) begin
+ if (main_sram0_we[1])
+ mem_grain1_2[main_sram0_adr1] <= main_sram0_dat_w[15:8];
+ mem_grain1_2_adr1 <= main_sram0_adr1;
+end
+assign main_reader_memory0_dat_r[15:8] = mem_grain1_2[mem_grain1_2_adr0];
+assign main_sram0_dat_r1[15:8] = mem_grain1_2[mem_grain1_2_adr1];
+
+
+//------------------------------------------------------------------------------
+// Memory mem_grain2_2: 383-words x 8-bit
+//------------------------------------------------------------------------------
+// Port 0 | Read: Sync | Write: ---- |
+// Port 1 | Read: Sync | Write: Sync | Mode: Write-First | Write-Granularity: 8
+reg [7:0] mem_grain2_2[0:382];
+reg [8:0] mem_grain2_2_adr0;
+reg [8:0] mem_grain2_2_adr1;
+always @(posedge sys_clk) begin
+ mem_grain2_2_adr0 <= main_reader_memory0_adr;
+end
+always @(posedge sys_clk) begin
+ if (main_sram0_we[2])
+ mem_grain2_2[main_sram0_adr1] <= main_sram0_dat_w[23:16];
+ mem_grain2_2_adr1 <= main_sram0_adr1;
+end
+assign main_reader_memory0_dat_r[23:16] = mem_grain2_2[mem_grain2_2_adr0];
+assign main_sram0_dat_r1[23:16] = mem_grain2_2[mem_grain2_2_adr1];
+
+
+//------------------------------------------------------------------------------
+// Memory mem_grain3_2: 383-words x 8-bit
+//------------------------------------------------------------------------------
+// Port 0 | Read: Sync | Write: ---- |
+// Port 1 | Read: Sync | Write: Sync | Mode: Write-First | Write-Granularity: 8
+reg [7:0] mem_grain3_2[0:382];
+reg [8:0] mem_grain3_2_adr0;
+reg [8:0] mem_grain3_2_adr1;
+always @(posedge sys_clk) begin
+ mem_grain3_2_adr0 <= main_reader_memory0_adr;
+end
+always @(posedge sys_clk) begin
+ if (main_sram0_we[3])
+ mem_grain3_2[main_sram0_adr1] <= main_sram0_dat_w[31:24];
+ mem_grain3_2_adr1 <= main_sram0_adr1;
+end
+assign main_reader_memory0_dat_r[31:24] = mem_grain3_2[mem_grain3_2_adr0];
+assign main_sram0_dat_r1[31:24] = mem_grain3_2[mem_grain3_2_adr1];
+
+
+//------------------------------------------------------------------------------
+// Memory mem_grain0_3: 383-words x 8-bit
+//------------------------------------------------------------------------------
+// Port 0 | Read: Sync | Write: ---- |
+// Port 1 | Read: Sync | Write: Sync | Mode: Write-First | Write-Granularity: 8
+reg [7:0] mem_grain0_3[0:382];
+reg [8:0] mem_grain0_3_adr0;
+reg [8:0] mem_grain0_3_adr1;
+always @(posedge sys_clk) begin
+ mem_grain0_3_adr0 <= main_reader_memory1_adr;
+end
+always @(posedge sys_clk) begin
+ if (main_sram1_we[0])
+ mem_grain0_3[main_sram1_adr1] <= main_sram1_dat_w[7:0];
+ mem_grain0_3_adr1 <= main_sram1_adr1;
+end
+assign main_reader_memory1_dat_r[7:0] = mem_grain0_3[mem_grain0_3_adr0];
+assign main_sram1_dat_r1[7:0] = mem_grain0_3[mem_grain0_3_adr1];
+
+
+//------------------------------------------------------------------------------
+// Memory mem_grain1_3: 383-words x 8-bit
+//------------------------------------------------------------------------------
+// Port 0 | Read: Sync | Write: ---- |
+// Port 1 | Read: Sync | Write: Sync | Mode: Write-First | Write-Granularity: 8
+reg [7:0] mem_grain1_3[0:382];
+reg [8:0] mem_grain1_3_adr0;
+reg [8:0] mem_grain1_3_adr1;
+always @(posedge sys_clk) begin
+ mem_grain1_3_adr0 <= main_reader_memory1_adr;
+end
+always @(posedge sys_clk) begin
+ if (main_sram1_we[1])
+ mem_grain1_3[main_sram1_adr1] <= main_sram1_dat_w[15:8];
+ mem_grain1_3_adr1 <= main_sram1_adr1;
+end
+assign main_reader_memory1_dat_r[15:8] = mem_grain1_3[mem_grain1_3_adr0];
+assign main_sram1_dat_r1[15:8] = mem_grain1_3[mem_grain1_3_adr1];
+
+
+//------------------------------------------------------------------------------
+// Memory mem_grain2_3: 383-words x 8-bit
+//------------------------------------------------------------------------------
+// Port 0 | Read: Sync | Write: ---- |
+// Port 1 | Read: Sync | Write: Sync | Mode: Write-First | Write-Granularity: 8
+reg [7:0] mem_grain2_3[0:382];
+reg [8:0] mem_grain2_3_adr0;
+reg [8:0] mem_grain2_3_adr1;
+always @(posedge sys_clk) begin
+ mem_grain2_3_adr0 <= main_reader_memory1_adr;
+end
+always @(posedge sys_clk) begin
+ if (main_sram1_we[2])
+ mem_grain2_3[main_sram1_adr1] <= main_sram1_dat_w[23:16];
+ mem_grain2_3_adr1 <= main_sram1_adr1;
+end
+assign main_reader_memory1_dat_r[23:16] = mem_grain2_3[mem_grain2_3_adr0];
+assign main_sram1_dat_r1[23:16] = mem_grain2_3[mem_grain2_3_adr1];
+
+
+//------------------------------------------------------------------------------
+// Memory mem_grain3_3: 383-words x 8-bit
+//------------------------------------------------------------------------------
+// Port 0 | Read: Sync | Write: ---- |
+// Port 1 | Read: Sync | Write: Sync | Mode: Write-First | Write-Granularity: 8
+reg [7:0] mem_grain3_3[0:382];
+reg [8:0] mem_grain3_3_adr0;
+reg [8:0] mem_grain3_3_adr1;
+always @(posedge sys_clk) begin
+ mem_grain3_3_adr0 <= main_reader_memory1_adr;
+end
+always @(posedge sys_clk) begin
+ if (main_sram1_we[3])
+ mem_grain3_3[main_sram1_adr1] <= main_sram1_dat_w[31:24];
+ mem_grain3_3_adr1 <= main_sram1_adr1;
+end
+assign main_reader_memory1_dat_r[31:24] = mem_grain3_3[mem_grain3_3_adr0];
+assign main_sram1_dat_r1[31:24] = mem_grain3_3[mem_grain3_3_adr1];
+
+
+ODDRX1F ODDRX1F(
+ .D0(1'd1),
+ .D1(1'd0),
+ .SCLK(eth_tx_clk),
+ .Q(main_maccore_ethphy_eth_tx_clk_o)
+);
+
+FD1S3BX FD1S3BX(
+ .CK(eth_tx_clk),
+ .D(1'd0),
+ .PD(main_maccore_ethphy_reset),
+ .Q(builder_rst10)
+);
+
+FD1S3BX FD1S3BX_1(
+ .CK(eth_tx_clk),
+ .D(builder_rst10),
+ .PD(main_maccore_ethphy_reset),
+ .Q(eth_tx_rst)
+);
+
+FD1S3BX FD1S3BX_2(
+ .CK(eth_rx_clk),
+ .D(1'd0),
+ .PD(main_maccore_ethphy_reset),
+ .Q(builder_rst11)
+);
+
+FD1S3BX FD1S3BX_3(
+ .CK(eth_rx_clk),
+ .D(builder_rst11),
+ .PD(main_maccore_ethphy_reset),
+ .Q(eth_rx_rst)
+);
+
+ODDRX1F ODDRX1F_1(
+ .D0(main_maccore_ethphy_sink_valid),
+ .D1(main_maccore_ethphy_sink_valid),
+ .SCLK(eth_tx_clk),
+ .Q(main_maccore_ethphy_tx_ctl_oddrx1f)
+);
+
+ODDRX1F ODDRX1F_2(
+ .D0(main_maccore_ethphy_sink_payload_data[0]),
+ .D1(main_maccore_ethphy_sink_payload_data[4]),
+ .SCLK(eth_tx_clk),
+ .Q(main_maccore_ethphy_tx_data_oddrx1f[0])
+);
+
+ODDRX1F ODDRX1F_3(
+ .D0(main_maccore_ethphy_sink_payload_data[1]),
+ .D1(main_maccore_ethphy_sink_payload_data[5]),
+ .SCLK(eth_tx_clk),
+ .Q(main_maccore_ethphy_tx_data_oddrx1f[1])
+);
+
+ODDRX1F ODDRX1F_4(
+ .D0(main_maccore_ethphy_sink_payload_data[2]),
+ .D1(main_maccore_ethphy_sink_payload_data[6]),
+ .SCLK(eth_tx_clk),
+ .Q(main_maccore_ethphy_tx_data_oddrx1f[2])
+);
+
+ODDRX1F ODDRX1F_5(
+ .D0(main_maccore_ethphy_sink_payload_data[3]),
+ .D1(main_maccore_ethphy_sink_payload_data[7]),
+ .SCLK(eth_tx_clk),
+ .Q(main_maccore_ethphy_tx_data_oddrx1f[3])
+);
+
+IDDRX1F IDDRX1F(
+ .D(main_maccore_ethphy_rx_ctl_delayf),
+ .SCLK(eth_rx_clk),
+ .Q0(main_maccore_ethphy_rx_ctl[0]),
+ .Q1(main_maccore_ethphy_rx_ctl[1])
+);
+
+IDDRX1F IDDRX1F_1(
+ .D(main_maccore_ethphy_rx_data_delayf[0]),
+ .SCLK(eth_rx_clk),
+ .Q0(main_maccore_ethphy_rx_data[0]),
+ .Q1(main_maccore_ethphy_rx_data[4])
+);
+
+IDDRX1F IDDRX1F_2(
+ .D(main_maccore_ethphy_rx_data_delayf[1]),
+ .SCLK(eth_rx_clk),
+ .Q0(main_maccore_ethphy_rx_data[1]),
+ .Q1(main_maccore_ethphy_rx_data[5])
+);
+
+IDDRX1F IDDRX1F_3(
+ .D(main_maccore_ethphy_rx_data_delayf[2]),
+ .SCLK(eth_rx_clk),
+ .Q0(main_maccore_ethphy_rx_data[2]),
+ .Q1(main_maccore_ethphy_rx_data[6])
+);
+
+IDDRX1F IDDRX1F_4(
+ .D(main_maccore_ethphy_rx_data_delayf[3]),
+ .SCLK(eth_rx_clk),
+ .Q0(main_maccore_ethphy_rx_data[3]),
+ .Q1(main_maccore_ethphy_rx_data[7])
+);
+
+endmodule
+
+// -----------------------------------------------------------------------------
+// Auto-Generated by LiteX on 2022-02-22 13:54:55.
+//------------------------------------------------------------------------------
projects / microwatt.git / commitdiff