Update Tercel README with actual core state on reset

diff --git a/README.tercel.md b/README.tercel.md
index 874f352c2f4a85b54cd363e618e4bdde58549902..96a16d14d9d307b95bb9437f67499587247fe4cb 100644 (file)
--- a/README.tercel.md
+++ b/README.tercel.md
@@ -10,7 +10,7 @@ Tercel provides two interfaces to the host CPU:
 
 ## General Usage
 
-On reset, the Tercel core provides read-only access in single SPI, 3BA mode to any attached Flash device.  It uses the generic well-known single byte access instructions to provide full XIP support.  Host software is responsible for reading the Flash ID of the attached Flash device and reconfiguring the Tercel core for faster and more advanced operating modes.  This reconfiguration can take place online, with no interruption to the concurrent read operations in progress on the main MMIO Flash window.
+On reset, the Tercel core provides basic read/write access in single SPI, 3BA mode to any attached Flash device.  It uses the generic well-known single byte access instructions to provide full XIP support.  Host software is responsible for reading the Flash ID of the attached Flash device and reconfiguring the Tercel core for faster and more advanced operating modes.  This reconfiguration can take place online, with no interruption to the concurrent read operations in progress on the main MMIO Flash window.
 
 By default, with Microwatt, the two bus regions are available at:
 Flash MMIO (XIP base): 0xf0000000