sim._pyrtl: fix miscompilation of -(Const(0b11, 2).as_signed()).

Fixes #473.

diff --git a/nmigen/sim/_pyrtl.py b/nmigen/sim/_pyrtl.py
index 9c7225a765c568d24e39db064329867033a3d353..c2e9367bcb1d0c36cc3ac8efd7bacb8c4ca00710 100644 (file)
--- a/nmigen/sim/_pyrtl.py
+++ b/nmigen/sim/_pyrtl.py
@@ -116,7 +116,7 @@ class _RHSValueCompiler(_ValueCompiler):
             if value.operator == "~":
                 return f"(~{self(arg)})"
             if value.operator == "-":
-                return f"(-{self(arg)})"
+                return f"(-{sign(arg)})"
             if value.operator == "b":
                 return f"bool({mask(arg)})"
             if value.operator == "r|":

diff --git a/nmigen/test/test_sim.py b/nmigen/test/test_sim.py
index 8626e71eab9832090d5081ff330707bc6ff92cf7..94424f71042e6123d2f029759377c43f6d499abb 100644 (file)
--- a/nmigen/test/test_sim.py
+++ b/nmigen/test/test_sim.py
@@ -365,6 +365,7 @@ class SimulatorUnitTestCase(FHDLTestCase):
         self.assertStatement(stmt, [C(0b1000000)], C(0b0000010))
         self.assertStatement(stmt, [C(0b1000001)], C(0b0000110))
 
+
 class SimulatorIntegrationTestCase(FHDLTestCase):
     @contextmanager
     def assertSimulation(self, module, deadline=None):
@@ -788,3 +789,10 @@ class SimulatorRegressionTestCase(FHDLTestCase):
         dut = Module()
         dut.d.comb += Signal().eq(Repl(Const(1), 0))
         Simulator(dut).run()
+
+    def test_bug_473(self):
+        sim = Simulator(Module())
+        def process():
+            self.assertEqual((yield -(Const(0b11, 2).as_signed())), 1)
+        sim.add_process(process)
+        sim.run()