src/test_run_simulation_bug.py

   1 from nmigen import Signal, Module, Elaboratable
   2 from nmigen.compat.sim import run_simulation
   3
   4 # test for https://github.com/nmigen/nmigen/issues/344
   5
   6
   7 class MyModule(Elaboratable):
   8     def __init__(self):
   9         self.a = Signal()
  10
  11     def elaborate(self, platform):
  12         m = Module()
  13         m.d.sync += self.a.eq(~self.a)
  14         return m
  15
  16
  17 def test1():
  18     dut = MyModule()
  19
  20     def generator():
  21         for _i in range(10):
  22             print((yield dut.a))
  23             yield
  24
  25     run_simulation(dut, generator(),
  26                    vcd_name="test_run_simulation_bug.vcd")
  27
  28
  29 if __name__ == '__main__':
  30     test1()