src/bsv/bsv_lib/Makefile.gpio.templates

   1 ### Makefile for the srio
   2
   3 TOP_MODULE:=mkgpio_real
   4 TOP_FILE:=gpio.bsv
   5 HOMEDIR:=./
   6 TOP_DIR:=./
   7 BSVBUILDDIR:=./build/
   8 VERILOGDIR:=./verilog/
   9 BSVINCDIR:= .:%/Prelude:%/Libraries:%/Libraries/BlueNoC
  10 FPGA=xc7a100tcsg324-1
  11 export HOMEDIR=./
  12 export TOP=$(TOP_MODULE)
  13
  14 default: full_clean compile link simulate
  15
  16 timing_area: full_clean generate_verilog vivado_build
  17
  18 .PHONY: compile
  19 compile:
  20         @echo Compiling $(TOP_MODULE)....
  21         @mkdir -p $(BSVBUILDDIR)
  22         @bsc -u -sim -simdir $(BSVBUILDDIR) -bdir $(BSVBUILDDIR) -info-dir $(BSVBUILDDIR) -keep-fires -p  $(BSVINCDIR) -D NAME=neel -g $(TOP_MODULE)  $(TOP_DIR)/$(TOP_FILE)
  23         @echo Compilation finished
  24
  25 .PHONY: link
  26 link:
  27         @echo Linking $(TOP_MODULE)...
  28         @mkdir -p bin
  29         @bsc -e $(TOP_MODULE) -sim -o ./bin/out -simdir $(BSVBUILDDIR) -p .:%/Prelude:%/Libraries:%/Libraries/BlueNoC:./c_files -keep-fires -bdir $(BSVBUILDDIR) -keep-fires ./c_files/checker.c
  30         @echo Linking finished
  31
  32 .PHONY: generate_verilog
  33 generate_verilog:
  34         @echo Compiling $(TOP_MODULE) in verilog ...
  35         @mkdir -p $(BSVBUILDDIR);
  36         @mkdir -p $(VERILOGDIR);
  37         @bsc -u -verilog -elab -vdir $(VERILOGDIR) -bdir $(BSVBUILDDIR) -info-dir $(BSVBUILDDIR)\
  38   $(define_macros) -D verilog=True $(BSVCOMPILEOPTS) -verilog-filter ${BLUESPECDIR}/bin/basicinout\
  39   -p $(BSVINCDIR) -g $(TOP_MODULE) $(TOP_DIR)/$(TOP_FILE)  || (echo "BSC COMPILE ERROR"; exit 1)
  40
  41 .PHONY: simulate
  42 simulate:
  43         @echo Simulation...
  44         ./bin/out
  45         @echo Simulation finished.
  46
  47 .PHONY: clean
  48 clean:
  49         rm -rf build bin *.jou *.log
  50
  51 .PHONY: full_clean
  52 full_clean: clean
  53         rm -rf verilog fpga