src/bsv/bsv_lib/slow_peripherals.bsv

   1 package slow_peripherals;
   2         /*===== Project imports =====*/
   3         import defined_types::*;
   4         import AXI4_Lite_Fabric::*;
   5         import AXI4_Lite_Types::*;
   6         import AXI4_Fabric::*;
   7         import AXI4_Types::*;
   8         import Semi_FIFOF::*;
   9         import AXI4Lite_AXI4_Bridge::*;
  10         `include "instance_defines.bsv"
  11         /*===========================*/
  12         /*=== package imports ===*/
  13         import Clocks::*;
  14         import GetPut::*;
  15         import ClientServer::*;
  16         import Connectable::*;
  17         import Vector::*;
  18         import FIFO::*;
  19         /*=======================*/
  20         /*===== Import the slow peripherals ====*/
  21         `ifdef UART0
  22                 import Uart16550                 :: *;
  23         `endif
  24         `ifdef UART1
  25                 import Uart_bs::*;
  26                 import RS232_modified::*;
  27         `endif
  28         `ifdef CLINT
  29                 import clint::*;
  30         `endif
  31         `ifdef PLIC
  32                 import plic                             ::*;
  33         `endif
  34         `ifdef I2C0
  35                 import I2C_top                   :: *;
  36         `endif
  37         `ifdef QSPI0
  38                 import qspi                              :: *;
  39         `endif
  40         `ifdef AXIEXP
  41                 import axiexpansion     ::*;
  42         `endif
  43   `ifdef PWM_AXI4Lite
  44     import pwm::*;
  45   `endif
  46   // NEEL EDIT
  47   import pinmux::*;
  48   import mux::*;
  49   import gpio::*;
  50         /*=====================================*/
  51
  52         /*===== interface declaration =====*/
  53         interface SP_ios;
  54                 `ifdef UART0
  55                         interface RS232_PHY_Ifc uart0_coe;
  56                 `endif
  57                 `ifdef UART1
  58                         interface RS232 uart1_coe;
  59                 `endif
  60                 `ifdef I2C0
  61                         interface I2C_out i2c0_out;
  62                 `endif
  63                 `ifdef I2C1
  64                         interface I2C_out i2c1_out;
  65                 `endif
  66                 `ifdef QSPI0
  67                         interface QSPI_out qspi0_out;
  68                 `endif
  69       `ifdef QSPI1
  70                         interface QSPI_out qspi1_out;
  71                 `endif
  72                 `ifdef AXIEXP
  73                         interface Get#(Bit#(67)) axiexp1_out;
  74                         interface Put#(Bit#(67)) axiexp1_in;
  75                 `endif
  76     `ifdef PWM_AXI4Lite
  77       interface PWMIO pwm_o;
  78     `endif
  79         endinterface
  80         interface Ifc_slow_peripherals;
  81                 interface AXI4_Slave_IFC#(`PADDR,`Reg_width,`USERSPACE) axi_slave;
  82                 interface SP_ios slow_ios;
  83     method Action external_int(Bit#(32) in);
  84                 `ifdef CLINT
  85                         method Bit#(1) msip_int;
  86                         method Bit#(1) mtip_int;
  87                         method Bit#(`Reg_width) mtime;
  88                 `endif
  89                 `ifdef PLIC method ActionValue#(Tuple2#(Bool,Bool)) intrpt_note; `endif
  90                 `ifdef I2C0     method Bit#(1) i2c0_isint; `endif
  91                 `ifdef I2C1     method Bit#(1) i2c1_isint; `endif
  92                 `ifdef QSPI0 method Bit#(1) qspi0_isint; `endif
  93                 `ifdef QSPI1 method Bit#(1) qspi1_isint; `endif
  94                 `ifdef UART0 method Bit#(1) uart0_intr; `endif
  95     // NEEL EDIT
  96     interface IOCellSide iocell_side; // mandatory interface
  97     interface GPIO_config#(3) pad_configa; // depends on the number of banks
  98     // NEEL EDIT OVER
  99         endinterface
 100         /*================================*/
 101
 102         function Tuple2#(Bool, Bit#(TLog#(Num_Slow_Slaves))) fn_address_mapping (Bit#(`PADDR) addr);
 103                 `ifdef UART0
 104                         if(addr>=`UART0Base && addr<=`UART0End)
 105                                 return tuple2(True,fromInteger(valueOf(Uart0_slave_num)));
 106                         else
 107                 `endif
 108                 `ifdef UART1
 109                         if(addr>=`UART1Base && addr<=`UART1End)
 110                                 return tuple2(True,fromInteger(valueOf(Uart1_slave_num)));
 111                         else
 112                 `endif
 113                 `ifdef CLINT
 114                         if(addr>=`ClintBase && addr<=`ClintEnd)
 115                                 return tuple2(True,fromInteger(valueOf(CLINT_slave_num)));
 116                         else
 117                 `endif
 118                 `ifdef PLIC
 119                         if(addr>=`PLICBase && addr<=`PLICEnd)
 120                                 return tuple2(True,fromInteger(valueOf(Plic_slave_num)));
 121                         else
 122                 `endif
 123                 `ifdef I2C0
 124                         if(addr>=`I2C0Base && addr<=`I2C0End)
 125                                 return tuple2(True,fromInteger(valueOf(I2c0_slave_num)));
 126                         else
 127                 `endif
 128                 `ifdef I2C1
 129                         if(addr>=`I2C1Base && addr<=`I2C1End)
 130                                 return tuple2(True,fromInteger(valueOf(I2c1_slave_num)));
 131                         else
 132                 `endif
 133                 `ifdef QSPI0
 134                         if(addr>=`QSPI0CfgBase && addr<=`QSPI0CfgEnd)
 135                                 return tuple2(True,fromInteger(valueOf(Qspi0_slave_num)));
 136                         else if(addr>=`QSPI0MemBase && addr<=`QSPI0MemEnd)
 137                                 return tuple2(True,fromInteger(valueOf(Qspi0_slave_num)));
 138                         else
 139                 `endif
 140                 `ifdef QSPI1
 141                         if(addr>=`QSPI1CfgBase && addr<=`QSPI1CfgEnd)
 142                                 return tuple2(True,fromInteger(valueOf(Qspi1_slave_num)));
 143                         else if(addr>=`QSPI1MemBase && addr<=`QSPI1MemEnd)
 144                                 return tuple2(True,fromInteger(valueOf(Qspi1_slave_num)));
 145                         else
 146                 `endif
 147                 `ifdef AXIEXP
 148                         if(addr>=`AxiExp1Base && addr<=`AxiExp1End)
 149                                 return tuple2(True,fromInteger(valueOf(AxiExp1_slave_num)));
 150                         else
 151                 `endif
 152     `ifdef PWM_AXI4Lite
 153       if(addr>=`PWMBase && addr<=`PWMEnd)
 154         return tuple2(True,fromInteger(valueOf(Pwm_slave_num)));
 155       else
 156     `endif
 157
 158     // NEEL EDIT
 159       // give slave number and adress map to whatever peripherals you instantiate on the AXI4_Lite
 160       // slave.
 161     // NEEL EDIT OVER
 162                 return tuple2(False,?);
 163         endfunction
 164
 165         (*synthesize*)
 166         module mkslow_peripherals#(Clock fast_clock, Reset fast_reset, Clock uart_clock, Reset uart_reset
 167   `ifdef PWM_AXI4Lite ,Clock ext_pwm_clock `endif )(Ifc_slow_peripherals);
 168                 Clock sp_clock <-exposeCurrentClock; // slow peripheral clock
 169                 Reset sp_reset <-exposeCurrentReset; // slow peripheral reset
 170
 171                 /*======= Module declarations for each peripheral =======*/
 172                 `ifdef UART0
 173                         Uart16550_AXI4_Lite_Ifc uart0 <- mkUart16550(clocked_by uart_clock, reset_by uart_reset, sp_clock, sp_reset);
 174                 `endif
 175                 `ifdef UART1
 176                         //Ifc_Uart_bs uart1 <- mkUart_bs(clocked_by uart_clock, reset_by uart_reset,sp_clock, sp_reset);
 177                         Ifc_Uart_bs uart1 <- mkUart_bs(clocked_by sp_clock, reset_by sp_reset,sp_clock, sp_reset);
 178                 `endif
 179                 `ifdef CLINT
 180                         Ifc_clint                               clint                           <- mkclint();
 181                 `endif
 182                 `ifdef PLIC
 183                         Ifc_PLIC_AXI    plic <- mkplicperipheral();
 184          Wire#(Bit#(TLog#(`INTERRUPT_PINS))) interrupt_id <- mkWire();
 185                           Vector#(32, FIFO#(bit)) ff_gateway_queue <- replicateM(mkFIFO);
 186                 `endif
 187                 `ifdef I2C0
 188                         I2C_IFC                                 i2c0                            <- mkI2CController();
 189                 `endif
 190                 `ifdef I2C1
 191                         I2C_IFC                                 i2c1                            <- mkI2CController();
 192                 `endif
 193                 `ifdef QSPI0
 194                         Ifc_qspi                        qspi0                           <-      mkqspi();
 195                 `endif
 196                 `ifdef QSPI1
 197                         Ifc_qspi                        qspi1                           <-      mkqspi();
 198                 `endif
 199                 `ifdef AXIEXP
 200                         Ifc_AxiExpansion                axiexp1                 <- mkAxiExpansion();
 201                 `endif
 202     `ifdef PWM_AXI4Lite
 203       Ifc_PWM_bus pwm_bus <- mkPWM_bus(ext_pwm_clock);
 204     `endif
 205     // NEEL EDIT
 206     Ifc_pinmux pinmux <- mkpinmux; // mandatory
 207     MUX#(3) muxa <- mkmux(); // mandatory. number depends on the number of instances required.
 208     GPIO#(3) gpioa <- mkgpio(); // optional. depends the number of IO pins declared before.
 209     Wire#(Bit#(32)) wr_interrupt <- mkWire();
 210     // NEEL EDIT OVER
 211                 /*=======================================================*/
 212
 213         AXI4_Lite_Fabric_IFC #(1, Num_Slow_Slaves, `PADDR, `Reg_width,`USERSPACE)       slow_fabric <-
 214                                                             mkAXI4_Lite_Fabric(fn_address_mapping);
 215                 Ifc_AXI4Lite_AXI4_Bridge bridge <-mkAXI4Lite_AXI4_Bridge(fast_clock,fast_reset);
 216
 217                 mkConnection (bridge.axi4_lite_master,  slow_fabric.v_from_masters [0]);
 218                 /*======= Slave connections to AXI4Lite fabric =========*/
 219                 `ifdef UART0
 220                         mkConnection (slow_fabric.v_to_slaves [fromInteger(valueOf(Uart0_slave_num))],
 221                     uart0.slave_axi_uart);
 222                 `endif
 223                 `ifdef UART1
 224                 mkConnection (slow_fabric.v_to_slaves [fromInteger(valueOf(Uart1_slave_num))],
 225                     uart1.slave_axi_uart);
 226                 `endif
 227                 `ifdef CLINT
 228                         mkConnection (slow_fabric.v_to_slaves [fromInteger(valueOf(CLINT_slave_num))],
 229                     clint.axi4_slave);
 230                 `endif
 231                 `ifdef PLIC
 232                         mkConnection (slow_fabric.v_to_slaves [fromInteger(valueOf(Plic_slave_num))],
 233                     plic.axi4_slave_plic); //
 234                 `endif
 235                 `ifdef I2C0
 236                 mkConnection (slow_fabric.v_to_slaves [fromInteger(valueOf(I2c0_slave_num))],
 237                     i2c0.slave_i2c_axi);
 238                 `endif
 239                 `ifdef I2C1
 240                 mkConnection (slow_fabric.v_to_slaves [fromInteger(valueOf(I2c1_slave_num))],
 241                     i2c1.slave_i2c_axi); //
 242                 `endif
 243                 `ifdef QSPI0
 244                         mkConnection (slow_fabric.v_to_slaves [fromInteger(valueOf(Qspi0_slave_num))],
 245                     qspi0.slave);
 246                 `endif
 247                 `ifdef QSPI1
 248                         mkConnection (slow_fabric.v_to_slaves [fromInteger(valueOf(Qspi1_slave_num))],
 249                     qspi1.slave);
 250                 `endif
 251                 `ifdef AXIEXP
 252                 mkConnection (slow_fabric.v_to_slaves [fromInteger(valueOf(AxiExp1_slave_num))],
 253                     axiexp1.axi_slave); //
 254                 `endif
 255     `ifdef PWM_AXI4Lite
 256       mkConnection (slow_fabric.v_to_slaves [fromInteger(valueOf(Pwm_slave_num))],
 257                     pwm_bus.axi4_slave);
 258     `endif
 259
 260     // NEEL EDIT
 261     mkConnection (slow_fabric.
 262                   v_to_slaves[fromInteger(valueOf(Muxa_slave_num))],
 263                   muxa.axi_slave);
 264     mkConnection (slow_fabric.
 265                   v_to_slaves[fromInteger(valueOf(Gpioa_slave_num))],
 266                   gpioa.axi_slave);
 267     rule connect_select_lines_pinmux;// mandatory
 268       pinmux.mux_lines.cell0_mux(muxa.mux_config.mux[0]);
 269       pinmux.mux_lines.cell1_mux(muxa.mux_config.mux[1]);
 270       pinmux.mux_lines.cell2_mux(muxa.mux_config.mux[2]);
 271     endrule
 272     rule connect_i2c0_scl;
 273       pinmux.peripheral_side.twi_scl_out(i2c0.out.scl_out);
 274       pinmux.peripheral_side.twi_scl_outen(pack(i2c0.out.scl_out_en));
 275     endrule
 276     rule connect_i2c0_scl_in;
 277       i2c0.out.scl_in(pinmux.peripheral_side.twi_scl_in);
 278     endrule
 279     rule connect_i2c0_sda;
 280       pinmux.peripheral_side.twi_sda_out(i2c0.out.sda_out);
 281       pinmux.peripheral_side.twi_sda_outen(pack(i2c0.out.sda_out_en));
 282     endrule
 283     rule connect_i2c0_sda_in;
 284       i2c0.out.sda_in(pinmux.peripheral_side.twi_sda_in);
 285     endrule
 286     rule connect_uart1tx;
 287       pinmux.peripheral_side.uart_tx(uart1.coe_rs232.sout);
 288     endrule
 289     rule connect_uart1rx;
 290       uart1.coe_rs232.sin(pinmux.peripheral_side.uart_rx);
 291     endrule
 292     rule connect_gpioa;
 293       pinmux.peripheral_side.gpioa_a0_out(gpioa.func.gpio_out[0]);
 294       pinmux.peripheral_side.gpioa_a0_outen(gpioa.func.gpio_out_en[0]);
 295       pinmux.peripheral_side.gpioa_a1_out(gpioa.func.gpio_out[1]);
 296       pinmux.peripheral_side.gpioa_a1_outen(gpioa.func.gpio_out_en[1]);
 297       pinmux.peripheral_side.gpioa_a2_out(gpioa.func.gpio_out[2]);
 298       pinmux.peripheral_side.gpioa_a2_outen(gpioa.func.gpio_out_en[2]);
 299                 Vector#(3,Bit#(1)) temp;
 300                 temp[0]=pinmux.peripheral_side.gpioa_a0_in;
 301                 temp[1]=pinmux.peripheral_side.gpioa_a1_in;
 302                 temp[2]=pinmux.peripheral_side.gpioa_a2_in;
 303       gpioa.func.gpio_in(temp);
 304     endrule
 305     for(Integer i=0;i<32;i=i+ 1)begin
 306       rule connect_int_to_plic(wr_interrupt[i]==1);
 307                                 ff_gateway_queue[i].enq(1);
 308                                 plic.ifc_external_irq[i].irq_frm_gateway(True);
 309       endrule
 310     end
 311     rule rl_completion_msg_from_plic;
 312                   let id <- plic.intrpt_completion;
 313       interrupt_id <= id;
 314       `ifdef verbose $display("Dequeing the FIFO -- PLIC Interrupt Serviced id: %d",id); `endif
 315                 endrule
 316
 317     for(Integer i=0; i <32; i=i+1) begin
 318             rule deq_gateway_queue;
 319                     if(interrupt_id==fromInteger(i)) begin
 320                             ff_gateway_queue[i].deq;
 321           `ifdef $display($time,"Dequeing the Interrupt request for ID: %d",i); `endif
 322         end
 323       endrule
 324     end
 325     // NEEL EDIT OVER
 326                 /*=======================================================*/
 327                 /*=================== PLIC Connections ==================== */
 328                 `ifdef PLIC_main
 329                         /*TODO DMA interrupt need to be connected to the plic
 330                         for(Integer i=1; i<8; i=i+1) begin
 331          `ifdef DMA
 332              rule rl_connect_dma_interrupts_to_plic;
 333                                         if(dma.interrupt_to_processor[i-1]==1'b1) begin
 334                                                 ff_gateway_queue[i].enq(1);
 335                                                 plic.ifc_external_irq[i].irq_frm_gateway(True);
 336                                         end
 337              endrule
 338           `else
 339              rule rl_connect_dma_interrupts_to_plic;
 340                  ff_gateway_queue[i].enq(0);
 341              endrule
 342           `endif
 343          end
 344                         */
 345          rule rl_connect_i2c0_to_plic;
 346                                 `ifdef I2C0
 347                                         if(i2c0.isint()==1'b1) begin
 348                                                 ff_gateway_queue[8].enq(1);
 349                                                 plic.ifc_external_irq[8].irq_frm_gateway(True);
 350                                         end
 351                                 `else
 352                                         ff_gateway_queue[8].enq(0);
 353             `endif
 354          endrule
 355
 356                         rule rl_connect_i2c1_to_plic;
 357                                 `ifdef I2C1
 358                                         if(i2c1.isint()==1'b1) begin
 359                                                 ff_gateway_queue[9].enq(1);
 360                                                 plic.ifc_external_irq[9].irq_frm_gateway(True);
 361                                         end
 362             `else
 363                                         ff_gateway_queue[9].enq(0);
 364             `endif
 365                         endrule
 366
 367          rule rl_connect_i2c0_timerint_to_plic;
 368                                 `ifdef I2C0
 369                                         if(i2c0.timerint()==1'b1) begin
 370                                                 ff_gateway_queue[10].enq(1);
 371                                                 plic.ifc_external_irq[10].irq_frm_gateway(True);
 372                                         end
 373             `else
 374                                         ff_gateway_queue[10].enq(0);
 375             `endif
 376                         endrule
 377
 378          rule rl_connect_i2c1_timerint_to_plic;
 379                                 `ifdef I2C1
 380                                         if(i2c1.timerint()==1'b1) begin
 381                                                 ff_gateway_queue[11].enq(1);
 382                                                 plic.ifc_external_irq[11].irq_frm_gateway(True);
 383                                         end
 384             `else
 385                                         ff_gateway_queue[11].enq(0);
 386             `endif
 387          endrule
 388
 389          rule rl_connect_i2c0_isber_to_plic;
 390                                 `ifdef I2C0
 391                                         if(i2c0.isber()==1'b1) begin
 392                                                 ff_gateway_queue[12].enq(1);
 393                                                 plic.ifc_external_irq[12].irq_frm_gateway(True);
 394                                         end
 395             `else
 396                                         ff_gateway_queue[12].enq(0);
 397             `endif
 398          endrule
 399
 400          rule rl_connect_i2c1_isber_to_plic;
 401                                 `ifdef I2C1
 402                                         if(i2c1.isber()==1'b1) begin
 403                                                 ff_gateway_queue[13].enq(1);
 404                                                 plic.ifc_external_irq[13].irq_frm_gateway(True);
 405                end
 406             `else
 407                                         ff_gateway_queue[13].enq(0);
 408             `endif
 409          endrule
 410
 411          for(Integer i = 14; i < 20; i=i+1) begin
 412                                 rule rl_connect_qspi0_to_plic;
 413                                         `ifdef QSPI0
 414                                                 if(qspi0.interrupts()[i-14]==1'b1) begin
 415                                                         ff_gateway_queue[i].enq(1);
 416                                                         plic.ifc_external_irq[i].irq_frm_gateway(True);
 417                                                 end
 418                `else
 419                                                 ff_gateway_queue[i].enq(0);
 420                `endif
 421             endrule
 422          end
 423
 424          for(Integer i = 20; i<26; i=i+1) begin
 425                                 rule rl_connect_qspi1_to_plic;
 426                                         `ifdef QSPI1
 427                                                 if(qspi1.interrupts()[i-20]==1'b1) begin
 428                                                         ff_gateway_queue[i].enq(1);
 429                                                         plic.ifc_external_irq[i].irq_frm_gateway(True);
 430                                                 end
 431                `else
 432                                                 ff_gateway_queue[i].enq(0);
 433                `endif
 434             endrule
 435                         end
 436
 437                         `ifdef UART0
 438                                 SyncBitIfc#(Bit#(1)) uart0_interrupt <-mkSyncBitToCC(uart_clock,uart_reset);
 439                                 rule synchronize_the_uart0_interrupt;
 440                                         uart0_interrupt.send(uart0.irq);
 441                                 endrule
 442                         `endif
 443                         rule rl_connect_uart_to_plic;
 444                                 `ifdef UART0
 445                                         if(uart0_interrupt.read==1'b1) begin
 446                                                 ff_gateway_queue[27].enq(1);
 447                                                 plic.ifc_external_irq[27].irq_frm_gateway(True);
 448                end
 449
 450             `else
 451                                         ff_gateway_queue[27].enq(0);
 452             `endif
 453          endrule
 454
 455                         for(Integer i = 28; i<`INTERRUPT_PINS; i=i+1) begin
 456                                 rule rl_raise_interrupts;
 457                                         if((i-28)<`IONum) begin //Peripheral interrupts
 458                                                 if(gpio.to_plic[i-28]==1'b1) begin
 459                                                         plic.ifc_external_irq[i].irq_frm_gateway(True);
 460                                                                 ff_gateway_queue[i].enq(1);
 461                   end
 462                                         end
 463                                 endrule
 464                         end
 465
 466          rule rl_completion_msg_from_plic;
 467                                 let id <- plic.intrpt_completion;
 468             interrupt_id <= id;
 469             `ifdef verbose $display("Dequeing the FIFO -- PLIC Interrupt Serviced id: %d",id); `endif
 470                         endrule
 471
 472          for(Integer i=0; i <`INTERRUPT_PINS; i=i+1) begin
 473                                 rule deq_gateway_queue;
 474                                         if(interrupt_id==fromInteger(i)) begin
 475                                                 ff_gateway_queue[i].deq;
 476                   `ifdef $display($time,"Dequeing the Interrupt request for ID: %d",i); `endif
 477                end
 478             endrule
 479          end
 480
 481
 482                 `endif
 483                         /*======================================================= */
 484
 485                 /* ===== interface definition =======*/
 486                 interface axi_slave=bridge.axi_slave;
 487                 `ifdef PLIC method intrpt_note = plic.intrpt_note; `endif
 488                 `ifdef CLINT
 489                         method msip_int=clint.msip_int;
 490                         method mtip_int=clint.mtip_int;
 491                         method mtime=clint.mtime;
 492                 `endif
 493                 `ifdef I2C0
 494                         method i2c0_isint=i2c0.isint;
 495                 `endif
 496                 `ifdef I2C1
 497                         method i2c1_isint=i2c1.isint;
 498                 `endif
 499                 `ifdef QSPI0 method     qspi0_isint=qspi0.interrupts[5]; `endif
 500                 `ifdef QSPI1 method     qspi1_isint=qspi1.interrupts[5]; `endif
 501                 `ifdef UART0 method uart0_intr=uart0.irq; `endif
 502                 interface SP_ios slow_ios;
 503                         `ifdef UART0
 504                                 interface uart0_coe=uart0.coe_rs232;
 505                         `endif
 506                         `ifdef UART1
 507                                 interface uart1_coe=uart1.coe_rs232;
 508                         `endif
 509                         `ifdef I2C0
 510                                 interface i2c0_out=i2c0.out;
 511                         `endif
 512                         `ifdef I2C1
 513                                 interface i2c1_out=i2c1.out;
 514                         `endif
 515                         `ifdef QSPI0
 516                                 interface qspi0_out = qspi0.out;
 517                         `endif
 518                         `ifdef QSPI1
 519                                 interface qspi1_out = qspi1.out;
 520                         `endif
 521                         `ifdef AXIEXP
 522                                 interface axiexp1_out=axiexp1.slave_out;
 523                                 interface axiexp1_in=axiexp1.slave_in;
 524                         `endif
 525       `ifdef PWM_AXI4Lite
 526         interface pwm_o = pwm_bus.pwm_io;
 527       `endif
 528                 endinterface
 529     // NEEL EDIT
 530     interface iocell_side=pinmux.iocell_side;
 531     interface pad_configa= gpioa.pad_config;
 532     method Action external_int(Bit#(32) in);
 533       wr_interrupt<= in;
 534     endmethod
 535     // NEEL EDIT OVER
 536                 /*===================================*/
 537         endmodule
 538 endpackage