src/bsv/bsv_lib/slow_peripherals.bsv

   1 package slow_peripherals;
   2         /*===== Project imports =====*/
   3         import defined_types::*;
   4         import AXI4_Lite_Fabric::*;
   5         import AXI4_Lite_Types::*;
   6         import AXI4_Fabric::*;
   7         import AXI4_Types::*;
   8         import Semi_FIFOF::*;
   9         import AXI4Lite_AXI4_Bridge::*;
  10         `include "instance_defines.bsv"
  11         /*===========================*/
  12         /*=== package imports ===*/
  13         import Clocks::*;
  14         import GetPut::*;
  15         import ClientServer::*;
  16         import Connectable::*;
  17         import Vector::*;
  18         import FIFO::*;
  19         /*=======================*/
  20         /*===== Import the slow peripherals ====*/
  21         `ifdef UART0
  22                 import Uart16550                 :: *;
  23         `endif
  24         `ifdef UART1
  25                 import Uart_bs::*;
  26                 import RS232_modified::*;
  27         `endif
  28         `ifdef CLINT
  29                 import clint::*;
  30         `endif
  31         `ifdef PLIC
  32                 import plic                             ::*;
  33         `endif
  34         `ifdef I2C0
  35                 import I2C_top                   :: *;
  36         `endif
  37         `ifdef QSPI0
  38                 import qspi                              :: *;
  39         `endif
  40         `ifdef AXIEXP
  41                 import axiexpansion     ::*;
  42         `endif
  43   `ifdef PWM_AXI4Lite
  44     import pwm::*;
  45   `endif
  46   // NEEL EDIT
  47   import pinmux::*;
  48   import mux::*;
  49   import gpio::*;
  50         /*=====================================*/
  51
  52         /*===== interface declaration =====*/
  53         interface SP_ios;
  54                 `ifdef UART0
  55                         interface RS232_PHY_Ifc uart0_coe;
  56                 `endif
  57                 `ifdef UART1
  58                         interface RS232 uart1_coe;
  59                 `endif
  60                 `ifdef PLIC
  61                         (*always_ready,always_enabled*)
  62                         method Action gpio_in (Vector#(`IONum,Bit#(1)) inp);
  63                         (*always_ready,always_enabled*)
  64                         method Vector#(`IONum,Bit#(1))   gpio_out;
  65                         (*always_ready,always_enabled*)
  66                         method Vector#(`IONum,Bit#(1))   gpio_out_en;
  67                 `endif
  68                 `ifdef I2C0
  69                         interface I2C_out i2c0_out;
  70                 `endif
  71                 `ifdef I2C1
  72                         interface I2C_out i2c1_out;
  73                 `endif
  74                 `ifdef QSPI0
  75                         interface QSPI_out qspi0_out;
  76                 `endif
  77       `ifdef QSPI1
  78                         interface QSPI_out qspi1_out;
  79                 `endif
  80                 `ifdef AXIEXP
  81                         interface Get#(Bit#(67)) axiexp1_out;
  82                         interface Put#(Bit#(67)) axiexp1_in;
  83                 `endif
  84     `ifdef PWM_AXI4Lite
  85       interface PWMIO pwm_o;
  86     `endif
  87         endinterface
  88         interface Ifc_slow_peripherals;
  89                 interface AXI4_Slave_IFC#(`PADDR,`Reg_width,`USERSPACE) axi_slave;
  90                 interface SP_ios slow_ios;
  91                 `ifdef CLINT
  92                         method Bit#(1) msip_int;
  93                         method Bit#(1) mtip_int;
  94                         method Bit#(`Reg_width) mtime;
  95                 `endif
  96                 `ifdef PLIC method ActionValue#(Tuple2#(Bool,Bool)) intrpt_note; `endif
  97                 `ifdef I2C0     method Bit#(1) i2c0_isint; `endif
  98                 `ifdef I2C1     method Bit#(1) i2c1_isint; `endif
  99                 `ifdef QSPI0 method Bit#(1) qspi0_isint; `endif
 100                 `ifdef QSPI1 method Bit#(1) qspi1_isint; `endif
 101                 `ifdef UART0 method Bit#(1) uart0_intr; `endif
 102     // NEEL EDIT
 103     interface IOCellSide iocell_side; // mandatory interface
 104     interface GPIO_config#(3) pad_configa; // depends on the number of banks
 105     // NEEL EDIT OVER
 106         endinterface
 107         /*================================*/
 108
 109         function Tuple2#(Bool, Bit#(TLog#(Num_Slow_Slaves))) fn_address_mapping (Bit#(`PADDR) addr);
 110                 `ifdef UART0
 111                         if(addr>=`UART0Base && addr<=`UART0End)
 112                                 return tuple2(True,fromInteger(valueOf(Uart0_slave_num)));
 113                         else
 114                 `endif
 115                 `ifdef UART1
 116                         if(addr>=`UART1Base && addr<=`UART1End)
 117                                 return tuple2(True,fromInteger(valueOf(Uart1_slave_num)));
 118                         else
 119                 `endif
 120                 `ifdef CLINT
 121                         if(addr>=`ClintBase && addr<=`ClintEnd)
 122                                 return tuple2(True,fromInteger(valueOf(CLINT_slave_num)));
 123                         else
 124                 `endif
 125                 `ifdef PLIC
 126                         if(addr>=`PLICBase && addr<=`PLICEnd)
 127                                 return tuple2(True,fromInteger(valueOf(Plic_slave_num)));
 128                         else if(addr>=`GPIOBase && addr<=`GPIOEnd)
 129                                 return tuple2(True,fromInteger(valueOf(GPIO_slave_num)));
 130                         else
 131                 `endif
 132                 `ifdef I2C0
 133                         if(addr>=`I2C0Base && addr<=`I2C0End)
 134                                 return tuple2(True,fromInteger(valueOf(I2c0_slave_num)));
 135                         else
 136                 `endif
 137                 `ifdef I2C1
 138                         if(addr>=`I2C1Base && addr<=`I2C1End)
 139                                 return tuple2(True,fromInteger(valueOf(I2c1_slave_num)));
 140                         else
 141                 `endif
 142                 `ifdef QSPI0
 143                         if(addr>=`QSPI0CfgBase && addr<=`QSPI0CfgEnd)
 144                                 return tuple2(True,fromInteger(valueOf(Qspi0_slave_num)));
 145                         else if(addr>=`QSPI0MemBase && addr<=`QSPI0MemEnd)
 146                                 return tuple2(True,fromInteger(valueOf(Qspi0_slave_num)));
 147                         else
 148                 `endif
 149                 `ifdef QSPI1
 150                         if(addr>=`QSPI1CfgBase && addr<=`QSPI1CfgEnd)
 151                                 return tuple2(True,fromInteger(valueOf(Qspi1_slave_num)));
 152                         else if(addr>=`QSPI1MemBase && addr<=`QSPI1MemEnd)
 153                                 return tuple2(True,fromInteger(valueOf(Qspi1_slave_num)));
 154                         else
 155                 `endif
 156                 `ifdef AXIEXP
 157                         if(addr>=`AxiExp1Base && addr<=`AxiExp1End)
 158                                 return tuple2(True,fromInteger(valueOf(AxiExp1_slave_num)));
 159                         else
 160                 `endif
 161     `ifdef PWM_AXI4Lite
 162       if(addr>=`PWMBase && addr<=`PWMEnd)
 163         return tuple2(True,fromInteger(valueOf(Pwm_slave_num)));
 164       else
 165     `endif
 166
 167     // NEEL EDIT
 168       // give slave number and adress map to whatever peripherals you instantiate on the AXI4_Lite
 169       // slave.
 170     // NEEL EDIT OVER
 171                 return tuple2(False,?);
 172         endfunction
 173
 174         (*synthesize*)
 175         module mkslow_peripherals#(Clock fast_clock, Reset fast_reset, Clock uart_clock, Reset uart_reset
 176   `ifdef PWM_AXI4Lite ,Clock ext_pwm_clock `endif )(Ifc_slow_peripherals);
 177                 Clock sp_clock <-exposeCurrentClock; // slow peripheral clock
 178                 Reset sp_reset <-exposeCurrentReset; // slow peripheral reset
 179
 180                 /*======= Module declarations for each peripheral =======*/
 181                 `ifdef UART0
 182                         Uart16550_AXI4_Lite_Ifc uart0 <- mkUart16550(clocked_by uart_clock, reset_by uart_reset, sp_clock, sp_reset);
 183                 `endif
 184                 `ifdef UART1
 185                         //Ifc_Uart_bs uart1 <- mkUart_bs(clocked_by uart_clock, reset_by uart_reset,sp_clock, sp_reset);
 186                         Ifc_Uart_bs uart1 <- mkUart_bs(clocked_by sp_clock, reset_by sp_reset,sp_clock, sp_reset);
 187                 `endif
 188                 `ifdef CLINT
 189                         Ifc_clint                               clint                           <- mkclint();
 190                 `endif
 191                 `ifdef PLIC
 192                         Ifc_PLIC_AXI    plic <- mkplicperipheral();
 193          Wire#(Bit#(TLog#(`INTERRUPT_PINS))) interrupt_id <- mkWire();
 194                         Vector#(`INTERRUPT_PINS, FIFO#(bit)) ff_gateway_queue <- replicateM(mkFIFO);
 195                         GPIO                                            gpio                            <- mkgpio;
 196                 `endif
 197                 `ifdef I2C0
 198                         I2C_IFC                                 i2c0                            <- mkI2CController();
 199                 `endif
 200                 `ifdef I2C1
 201                         I2C_IFC                                 i2c1                            <- mkI2CController();
 202                 `endif
 203                 `ifdef QSPI0
 204                         Ifc_qspi                        qspi0                           <-      mkqspi();
 205                 `endif
 206                 `ifdef QSPI1
 207                         Ifc_qspi                        qspi1                           <-      mkqspi();
 208                 `endif
 209                 `ifdef AXIEXP
 210                         Ifc_AxiExpansion                axiexp1                 <- mkAxiExpansion();
 211                 `endif
 212     `ifdef PWM_AXI4Lite
 213       Ifc_PWM_bus pwm_bus <- mkPWM_bus(ext_pwm_clock);
 214     `endif
 215     // NEEL EDIT
 216     Ifc_pinmux pinmux <- mkpinmux; // mandatory
 217     MUX#(3) muxa <- mkmux(); // mandatory. number depends on the number of instances required.
 218     GPIO#(3) gpioa <- mkgpio(); // optional. depends the number of IO pins declared before.
 219     // NEEL EDIT OVER
 220                 /*=======================================================*/
 221
 222         AXI4_Lite_Fabric_IFC #(1, Num_Slow_Slaves, `PADDR, `Reg_width,`USERSPACE)       slow_fabric <-
 223                                                             mkAXI4_Lite_Fabric(fn_address_mapping);
 224                 Ifc_AXI4Lite_AXI4_Bridge bridge <-mkAXI4Lite_AXI4_Bridge(fast_clock,fast_reset);
 225
 226                 mkConnection (bridge.axi4_lite_master,  slow_fabric.v_from_masters [0]);
 227                 /*======= Slave connections to AXI4Lite fabric =========*/
 228                 `ifdef UART0
 229                         mkConnection (slow_fabric.v_to_slaves [fromInteger(valueOf(Uart0_slave_num))],
 230                     uart0.slave_axi_uart);
 231                 `endif
 232                 `ifdef UART1
 233                 mkConnection (slow_fabric.v_to_slaves [fromInteger(valueOf(Uart1_slave_num))],
 234                     uart1.slave_axi_uart);
 235                 `endif
 236                 `ifdef CLINT
 237                         mkConnection (slow_fabric.v_to_slaves [fromInteger(valueOf(CLINT_slave_num))],
 238                     clint.axi4_slave);
 239                 `endif
 240                 `ifdef PLIC
 241                         mkConnection (slow_fabric.v_to_slaves [fromInteger(valueOf(Plic_slave_num))],
 242                     plic.axi4_slave_plic); //
 243                         mkConnection (slow_fabric.v_to_slaves [fromInteger(valueOf(GPIO_slave_num))],
 244                     gpio.axi_slave); //
 245                 `endif
 246                 `ifdef I2C0
 247                 mkConnection (slow_fabric.v_to_slaves [fromInteger(valueOf(I2c0_slave_num))],
 248                     i2c0.slave_i2c_axi);
 249                 `endif
 250                 `ifdef I2C1
 251                 mkConnection (slow_fabric.v_to_slaves [fromInteger(valueOf(I2c1_slave_num))],
 252                     i2c1.slave_i2c_axi); //
 253                 `endif
 254                 `ifdef QSPI0
 255                         mkConnection (slow_fabric.v_to_slaves [fromInteger(valueOf(Qspi0_slave_num))],
 256                     qspi0.slave);
 257                 `endif
 258                 `ifdef QSPI1
 259                         mkConnection (slow_fabric.v_to_slaves [fromInteger(valueOf(Qspi1_slave_num))],
 260                     qspi1.slave);
 261                 `endif
 262                 `ifdef AXIEXP
 263                 mkConnection (slow_fabric.v_to_slaves [fromInteger(valueOf(AxiExp1_slave_num))],
 264                     axiexp1.axi_slave); //
 265                 `endif
 266     `ifdef PWM_AXI4Lite
 267       mkConnection (slow_fabric.v_to_slaves [fromInteger(valueOf(Pwm_slave_num))],
 268                     pwm_bus.axi4_slave);
 269     `endif
 270
 271     // NEEL EDIT
 272     mkConnection (slow_fabric.
 273                   v_to_slaves[fromInteger(valueOf(Muxa_slave_num))],
 274                   muxa.axi_slave);
 275     mkConnection (slow_fabric.
 276                   v_to_slaves[fromInteger(valueOf(Gpioa_slave_num))],
 277                   gpioa.axi_slave);
 278     rule connect_select_lines_pinmux;// mandatory
 279       pinmux.mux_lines.cell0_mux(muxa.mux_config.mux[0]);
 280       pinmux.mux_lines.cell1_mux(muxa.mux_config.mux[1]);
 281       pinmux.mux_lines.cell2_mux(muxa.mux_config.mux[2]);
 282     endrule
 283     rule connect_i2c0_scl;
 284       pinmux.peripheral_side.twi_scl_out(i2c0.out.scl_out);
 285       pinmux.peripheral_side.twi_scl_outen(pack(i2c0.out.scl_out_en));
 286     endrule
 287     rule connect_i2c0_scl_in;
 288       i2c0.out.scl_in(pinmux.peripheral_side.twi_scl_in);
 289     endrule
 290     rule connect_i2c0_sda;
 291       pinmux.peripheral_side.twi_sda_out(i2c0.out.sda_out);
 292       pinmux.peripheral_side.twi_sda_outen(pack(i2c0.out.sda_out_en));
 293     endrule
 294     rule connect_i2c0_sda_in;
 295       i2c0.out.sda_in(pinmux.peripheral_side.twi_sda_in);
 296     endrule
 297     rule connect_uart1tx;
 298       pinmux.peripheral_side.uart_tx(uart1.coe_rs232.sout);
 299     endrule
 300     rule connect_uart1rx;
 301       uart1.coe_rs232.sin(pinmux.peripheral_side.uart_rx);
 302     endrule
 303     rule connect_gpioa;
 304       pinmux.peripheral_side.gpioa_a0_out(gpioa.func.gpio_out[0]);
 305       pinmux.peripheral_side.gpioa_a0_outen(gpioa.func.gpio_out_en[0]);
 306       pinmux.peripheral_side.gpioa_a1_out(gpioa.func.gpio_out[1]);
 307       pinmux.peripheral_side.gpioa_a1_outen(gpioa.func.gpio_out_en[1]);
 308       pinmux.peripheral_side.gpioa_a2_out(gpioa.func.gpio_out[2]);
 309       pinmux.peripheral_side.gpioa_a2_outen(gpioa.func.gpio_out_en[2]);
 310                 Vector#(3,Bit#(1)) temp;
 311                 temp[0]=pinmux.peripheral_side.gpioa_a0_in;
 312                 temp[1]=pinmux.peripheral_side.gpioa_a1_in;
 313                 temp[2]=pinmux.peripheral_side.gpioa_a2_in;
 314       gpioa.func.gpio_in(temp);
 315     endrule
 316     // NEEL EDIT OVER
 317                 /*=======================================================*/
 318                 /*=================== PLIC Connections ==================== */
 319                 `ifdef PLIC
 320                         /*TODO DMA interrupt need to be connected to the plic
 321                         for(Integer i=1; i<8; i=i+1) begin
 322          `ifdef DMA
 323              rule rl_connect_dma_interrupts_to_plic;
 324                                         if(dma.interrupt_to_processor[i-1]==1'b1) begin
 325                                                 ff_gateway_queue[i].enq(1);
 326                                                 plic.ifc_external_irq[i].irq_frm_gateway(True);
 327                                         end
 328              endrule
 329           `else
 330              rule rl_connect_dma_interrupts_to_plic;
 331                  ff_gateway_queue[i].enq(0);
 332              endrule
 333           `endif
 334          end
 335                         */
 336          rule rl_connect_i2c0_to_plic;
 337                                 `ifdef I2C0
 338                                         if(i2c0.isint()==1'b1) begin
 339                                                 ff_gateway_queue[8].enq(1);
 340                                                 plic.ifc_external_irq[8].irq_frm_gateway(True);
 341                                         end
 342                                 `else
 343                                         ff_gateway_queue[8].enq(0);
 344             `endif
 345          endrule
 346
 347                         rule rl_connect_i2c1_to_plic;
 348                                 `ifdef I2C1
 349                                         if(i2c1.isint()==1'b1) begin
 350                                                 ff_gateway_queue[9].enq(1);
 351                                                 plic.ifc_external_irq[9].irq_frm_gateway(True);
 352                                         end
 353             `else
 354                                         ff_gateway_queue[9].enq(0);
 355             `endif
 356                         endrule
 357
 358          rule rl_connect_i2c0_timerint_to_plic;
 359                                 `ifdef I2C0
 360                                         if(i2c0.timerint()==1'b1) begin
 361                                                 ff_gateway_queue[10].enq(1);
 362                                                 plic.ifc_external_irq[10].irq_frm_gateway(True);
 363                                         end
 364             `else
 365                                         ff_gateway_queue[10].enq(0);
 366             `endif
 367                         endrule
 368
 369          rule rl_connect_i2c1_timerint_to_plic;
 370                                 `ifdef I2C1
 371                                         if(i2c1.timerint()==1'b1) begin
 372                                                 ff_gateway_queue[11].enq(1);
 373                                                 plic.ifc_external_irq[11].irq_frm_gateway(True);
 374                                         end
 375             `else
 376                                         ff_gateway_queue[11].enq(0);
 377             `endif
 378          endrule
 379
 380          rule rl_connect_i2c0_isber_to_plic;
 381                                 `ifdef I2C0
 382                                         if(i2c0.isber()==1'b1) begin
 383                                                 ff_gateway_queue[12].enq(1);
 384                                                 plic.ifc_external_irq[12].irq_frm_gateway(True);
 385                                         end
 386             `else
 387                                         ff_gateway_queue[12].enq(0);
 388             `endif
 389          endrule
 390
 391          rule rl_connect_i2c1_isber_to_plic;
 392                                 `ifdef I2C1
 393                                         if(i2c1.isber()==1'b1) begin
 394                                                 ff_gateway_queue[13].enq(1);
 395                                                 plic.ifc_external_irq[13].irq_frm_gateway(True);
 396                end
 397             `else
 398                                         ff_gateway_queue[13].enq(0);
 399             `endif
 400          endrule
 401
 402          for(Integer i = 14; i < 20; i=i+1) begin
 403                                 rule rl_connect_qspi0_to_plic;
 404                                         `ifdef QSPI0
 405                                                 if(qspi0.interrupts()[i-14]==1'b1) begin
 406                                                         ff_gateway_queue[i].enq(1);
 407                                                         plic.ifc_external_irq[i].irq_frm_gateway(True);
 408                                                 end
 409                `else
 410                                                 ff_gateway_queue[i].enq(0);
 411                `endif
 412             endrule
 413          end
 414
 415          for(Integer i = 20; i<26; i=i+1) begin
 416                                 rule rl_connect_qspi1_to_plic;
 417                                         `ifdef QSPI1
 418                                                 if(qspi1.interrupts()[i-20]==1'b1) begin
 419                                                         ff_gateway_queue[i].enq(1);
 420                                                         plic.ifc_external_irq[i].irq_frm_gateway(True);
 421                                                 end
 422                `else
 423                                                 ff_gateway_queue[i].enq(0);
 424                `endif
 425             endrule
 426                         end
 427
 428                         `ifdef UART0
 429                                 SyncBitIfc#(Bit#(1)) uart0_interrupt <-mkSyncBitToCC(uart_clock,uart_reset);
 430                                 rule synchronize_the_uart0_interrupt;
 431                                         uart0_interrupt.send(uart0.irq);
 432                                 endrule
 433                         `endif
 434                         rule rl_connect_uart_to_plic;
 435                                 `ifdef UART0
 436                                         if(uart0_interrupt.read==1'b1) begin
 437                                                 ff_gateway_queue[27].enq(1);
 438                                                 plic.ifc_external_irq[27].irq_frm_gateway(True);
 439                end
 440
 441             `else
 442                                         ff_gateway_queue[27].enq(0);
 443             `endif
 444          endrule
 445
 446                         for(Integer i = 28; i<`INTERRUPT_PINS; i=i+1) begin
 447                                 rule rl_raise_interrupts;
 448                                         if((i-28)<`IONum) begin //Peripheral interrupts
 449                                                 if(gpio.to_plic[i-28]==1'b1) begin
 450                                                         plic.ifc_external_irq[i].irq_frm_gateway(True);
 451                                                                 ff_gateway_queue[i].enq(1);
 452                   end
 453                                         end
 454                                 endrule
 455                         end
 456
 457          rule rl_completion_msg_from_plic;
 458                                 let id <- plic.intrpt_completion;
 459             interrupt_id <= id;
 460             `ifdef verbose $display("Dequeing the FIFO -- PLIC Interrupt Serviced id: %d",id); `endif
 461                         endrule
 462
 463          for(Integer i=0; i <`INTERRUPT_PINS; i=i+1) begin
 464                                 rule deq_gateway_queue;
 465                                         if(interrupt_id==fromInteger(i)) begin
 466                                                 ff_gateway_queue[i].deq;
 467                   `ifdef $display($time,"Dequeing the Interrupt request for ID: %d",i); `endif
 468                end
 469             endrule
 470          end
 471
 472
 473                 `endif
 474                         /*======================================================= */
 475
 476                 /* ===== interface definition =======*/
 477                 interface axi_slave=bridge.axi_slave;
 478                 `ifdef PLIC method intrpt_note = plic.intrpt_note; `endif
 479                 `ifdef CLINT
 480                         method msip_int=clint.msip_int;
 481                         method mtip_int=clint.mtip_int;
 482                         method mtime=clint.mtime;
 483                 `endif
 484                 `ifdef I2C0
 485                         method i2c0_isint=i2c0.isint;
 486                 `endif
 487                 `ifdef I2C1
 488                         method i2c1_isint=i2c1.isint;
 489                 `endif
 490                 `ifdef QSPI0 method     qspi0_isint=qspi0.interrupts[5]; `endif
 491                 `ifdef QSPI1 method     qspi1_isint=qspi1.interrupts[5]; `endif
 492                 `ifdef UART0 method uart0_intr=uart0.irq; `endif
 493                 interface SP_ios slow_ios;
 494                         `ifdef UART0
 495                                 interface uart0_coe=uart0.coe_rs232;
 496                         `endif
 497                         `ifdef UART1
 498                                 interface uart1_coe=uart1.coe_rs232;
 499                         `endif
 500                         `ifdef PLIC
 501                                 method Action gpio_in (Vector#(`IONum,Bit#(1)) inp)=gpio.gpio_in(inp);
 502                                 method Vector#(`IONum,Bit#(1))   gpio_out=gpio.gpio_out;
 503                                 method Vector#(`IONum,Bit#(1))   gpio_out_en=gpio.gpio_out_en;
 504                         `endif
 505                         `ifdef I2C0
 506                                 interface i2c0_out=i2c0.out;
 507                         `endif
 508                         `ifdef I2C1
 509                                 interface i2c1_out=i2c1.out;
 510                         `endif
 511                         `ifdef QSPI0
 512                                 interface qspi0_out = qspi0.out;
 513                         `endif
 514                         `ifdef QSPI1
 515                                 interface qspi1_out = qspi1.out;
 516                         `endif
 517                         `ifdef AXIEXP
 518                                 interface axiexp1_out=axiexp1.slave_out;
 519                                 interface axiexp1_in=axiexp1.slave_in;
 520                         `endif
 521       `ifdef PWM_AXI4Lite
 522         interface pwm_o = pwm_bus.pwm_io;
 523       `endif
 524                 endinterface
 525     // NEEL EDIT
 526     interface iocell_side=pinmux.iocell_side;
 527     interface pad_configa= gpioa.pad_config;
 528     // NEEL EDIT OVER
 529                 /*===================================*/
 530         endmodule
 531 endpackage