src/bsv/bsv_lib/slow_peripherals_template.bsv

   1 package slow_peripherals;
   2         /*===== Project imports =====*/
   3         import defined_types::*;
   4         import AXI4_Lite_Fabric::*;
   5         import AXI4_Lite_Types::*;
   6         import AXI4_Fabric::*;
   7         import AXI4_Types::*;
   8         import Semi_FIFOF::*;
   9         import AXI4Lite_AXI4_Bridge::*;
  10         `include "instance_defines.bsv"
  11     /* ==== define the AXI Addresses ==== */
  12 {2}
  13     /*====== AXI4 Lite slave declarations =======*/
  14
  15 {3}
  16         /*===========================*/
  17         /*=== package imports ===*/
  18         import Clocks::*;
  19         import GetPut::*;
  20         import ClientServer::*;
  21         import Connectable::*;
  22         import Vector::*;
  23         import FIFO::*;
  24         /*=======================*/
  25         /*===== Import the slow peripherals ====*/
  26 {0}
  27     `ifdef CLINT
  28         import clint::*;
  29     `endif
  30     `ifdef PLIC
  31         import plic             ::*;
  32     `endif
  33         `ifdef AXIEXP
  34                 import axiexpansion     ::*;
  35         `endif
  36         `ifdef QSPI
  37                 import qspi                              :: *;
  38         `endif
  39         /*=====================================*/
  40
  41         /*===== interface declaration =====*/
  42         interface SP_ios;
  43 {1}
  44                 `ifdef AXIEXP
  45                         interface Get#(Bit#(67)) axiexp1_out;
  46                         interface Put#(Bit#(67)) axiexp1_in;
  47                 `endif
  48         endinterface
  49         interface Ifc_slow_peripherals;
  50                 interface AXI4_Slave_IFC#(`ADDR,`DATA,`USERSPACE) axi_slave;
  51                 interface SP_ios slow_ios;
  52     method Action external_int(Bit#(32) in);
  53                 `ifdef CLINT
  54                         method Bit#(1) msip_int;
  55                         method Bit#(1) mtip_int;
  56                         method Bit#(`DATA) mtime;
  57                 `endif
  58                 `ifdef PLIC method ActionValue#(Tuple2#(Bool,Bool)) intrpt_note; `endif
  59     interface IOCellSide iocell_side; // mandatory interface
  60         endinterface
  61         /*================================*/
  62
  63         function Tuple2#(Bool, Bit#(TLog#(Num_Slow_Slaves)))
  64                      fn_address_mapping (Bit#(`ADDR) addr);
  65                 `ifdef CLINT
  66                         if(addr>=`ClintBase && addr<=`ClintEnd)
  67                                 return tuple2(True,fromInteger(valueOf(CLINT_slave_num)));
  68                         else
  69                 `endif
  70                 `ifdef PLIC
  71                         if(addr>=`PLICBase && addr<=`PLICEnd)
  72                                 return tuple2(True,fromInteger(valueOf(Plic_slave_num)));
  73                         else
  74                 `endif
  75                 `ifdef AXIEXP
  76                         if(addr>=`AxiExp1Base && addr<=`AxiExp1End)
  77                                 return tuple2(True,fromInteger(valueOf(AxiExp1_slave_num)));
  78                         else
  79                 `endif
  80 {4}
  81                         return tuple2(False,?);
  82         endfunction
  83
  84         (*synthesize*)
  85         module mkslow_peripherals#(Clock fast_clock, Reset fast_reset,
  86                                Clock uart_clock, Reset uart_reset
  87                               `ifdef PWM_AXI4Lite ,Clock ext_pwm_clock `endif
  88                               )(Ifc_slow_peripherals);
  89                 Clock sp_clock <-exposeCurrentClock; // slow peripheral clock
  90                 Reset sp_reset <-exposeCurrentReset; // slow peripheral reset
  91
  92                 /*======= Module declarations for each peripheral =======*/
  93 {5}
  94                 `ifdef CLINT
  95                         Ifc_clint                               clint                           <- mkclint();
  96                 `endif
  97                 `ifdef PLIC
  98                         Ifc_PLIC_AXI    plic <- mkplicperipheral();
  99          Wire#(Bit#(TLog#(`INTERRUPT_PINS))) interrupt_id <- mkWire();
 100                           Vector#(32, FIFO#(bit)) ff_gateway_queue <- replicateM(mkFIFO);
 101                 `endif
 102                 `ifdef AXIEXP
 103                         Ifc_AxiExpansion                axiexp1                 <- mkAxiExpansion();
 104                 `endif
 105     Ifc_pinmux pinmux <- mkpinmux; // mandatory
 106     Wire#(Bit#(32)) wr_interrupt <- mkWire();
 107                 /*=======================================================*/
 108
 109         AXI4_Lite_Fabric_IFC #(1, Num_Slow_Slaves, `ADDR, `DATA,`USERSPACE)
 110             slow_fabric <- mkAXI4_Lite_Fabric(fn_address_mapping);
 111                 Ifc_AXI4Lite_AXI4_Bridge
 112             bridge<-mkAXI4Lite_AXI4_Bridge(fast_clock,fast_reset);
 113
 114                 mkConnection (bridge.axi4_lite_master,  slow_fabric.v_from_masters [0]);
 115                 /*======= Slave connections to AXI4Lite fabric =========*/
 116 {6}
 117                 `ifdef CLINT
 118                         mkConnection (slow_fabric.v_to_slaves
 119                     [fromInteger(valueOf(CLINT_slave_num))],
 120                     clint.axi4_slave);
 121                 `endif
 122                 `ifdef PLIC
 123                         mkConnection (slow_fabric.v_to_slaves
 124                     [fromInteger(valueOf(Plic_slave_num))],
 125                     plic.axi4_slave_plic); //
 126                 `endif
 127                 `ifdef AXIEXP
 128                 mkConnection (slow_fabric.v_to_slaves
 129                     [fromInteger(valueOf(AxiExp1_slave_num))],
 130                     axiexp1.axi_slave); //
 131                 `endif
 132
 133     /*========== pinmux connections ============*/
 134 {7}
 135 {8}
 136     for(Integer i=0;i<32;i=i+ 1)begin
 137       rule connect_int_to_plic(wr_interrupt[i]==1);
 138                                 ff_gateway_queue[i].enq(1);
 139                                 plic.ifc_external_irq[i].irq_frm_gateway(True);
 140       endrule
 141     end
 142     rule rl_completion_msg_from_plic;
 143                   let id <- plic.intrpt_completion;
 144       interrupt_id <= id;
 145       `ifdef verbose $display("Dequeing the FIFO -- PLIC Interrupt Serviced id: %d",id); `endif
 146                 endrule
 147
 148     for(Integer i=0; i <32; i=i+1) begin
 149             rule deq_gateway_queue;
 150                     if(interrupt_id==fromInteger(i)) begin
 151                             ff_gateway_queue[i].deq;
 152           `ifdef $display($time,"Dequeing the Interrupt request for ID: %d",i); `endif
 153         end
 154       endrule
 155     end
 156     /* for connectin inputs from pinmux as itnerrupts
 157       rule connect_pinmux_eint;
 158         wr_interrupt<= pinmux.peripheral_side.eint_input;
 159       endrule
 160     */
 161     // NEEL EDIT OVER
 162                 /*=======================================================*/
 163                 /*=================== PLIC Connections ==================== */
 164                 `ifdef PLIC_main
 165                         /*TODO DMA interrupt need to be connected to the plic
 166                         for(Integer i=1; i<8; i=i+1) begin
 167          `ifdef DMA
 168              rule rl_connect_dma_interrupts_to_plic;
 169                                         if(dma.interrupt_to_processor[i-1]==1'b1) begin
 170                                                 ff_gateway_queue[i].enq(1);
 171                                                 plic.ifc_external_irq[i].irq_frm_gateway(True);
 172                                         end
 173              endrule
 174           `else
 175              rule rl_connect_dma_interrupts_to_plic;
 176                  ff_gateway_queue[i].enq(0);
 177              endrule
 178           `endif
 179          end
 180                         */
 181          rule rl_connect_i2c0_to_plic;
 182                                 `ifdef I2C0
 183                                         if(i2c0.isint()==1'b1) begin
 184                                                 ff_gateway_queue[8].enq(1);
 185                                                 plic.ifc_external_irq[8].irq_frm_gateway(True);
 186                                         end
 187                                 `else
 188                                         ff_gateway_queue[8].enq(0);
 189             `endif
 190          endrule
 191
 192                         rule rl_connect_i2c1_to_plic;
 193                                 `ifdef I2C1
 194                                         if(i2c1.isint()==1'b1) begin
 195                                                 ff_gateway_queue[9].enq(1);
 196                                                 plic.ifc_external_irq[9].irq_frm_gateway(True);
 197                                         end
 198             `else
 199                                         ff_gateway_queue[9].enq(0);
 200             `endif
 201                         endrule
 202
 203          rule rl_connect_i2c0_timerint_to_plic;
 204                                 `ifdef I2C0
 205                                         if(i2c0.timerint()==1'b1) begin
 206                                                 ff_gateway_queue[10].enq(1);
 207                                                 plic.ifc_external_irq[10].irq_frm_gateway(True);
 208                                         end
 209             `else
 210                                         ff_gateway_queue[10].enq(0);
 211             `endif
 212                         endrule
 213
 214          rule rl_connect_i2c1_timerint_to_plic;
 215                                 `ifdef I2C1
 216                                         if(i2c1.timerint()==1'b1) begin
 217                                                 ff_gateway_queue[11].enq(1);
 218                                                 plic.ifc_external_irq[11].irq_frm_gateway(True);
 219                                         end
 220             `else
 221                                         ff_gateway_queue[11].enq(0);
 222             `endif
 223          endrule
 224
 225          rule rl_connect_i2c0_isber_to_plic;
 226                                 `ifdef I2C0
 227                                         if(i2c0.isber()==1'b1) begin
 228                                                 ff_gateway_queue[12].enq(1);
 229                                                 plic.ifc_external_irq[12].irq_frm_gateway(True);
 230                                         end
 231             `else
 232                                         ff_gateway_queue[12].enq(0);
 233             `endif
 234          endrule
 235
 236          rule rl_connect_i2c1_isber_to_plic;
 237                                 `ifdef I2C1
 238                                         if(i2c1.isber()==1'b1) begin
 239                                                 ff_gateway_queue[13].enq(1);
 240                                                 plic.ifc_external_irq[13].irq_frm_gateway(True);
 241                end
 242             `else
 243                                         ff_gateway_queue[13].enq(0);
 244             `endif
 245          endrule
 246
 247          for(Integer i = 14; i < 20; i=i+1) begin
 248                                 rule rl_connect_qspi0_to_plic;
 249                                         `ifdef QSPI0
 250                                                 if(qspi0.interrupts()[i-14]==1'b1) begin
 251                                                         ff_gateway_queue[i].enq(1);
 252                                                         plic.ifc_external_irq[i].irq_frm_gateway(True);
 253                                                 end
 254                `else
 255                                                 ff_gateway_queue[i].enq(0);
 256                `endif
 257             endrule
 258          end
 259
 260          for(Integer i = 20; i<26; i=i+1) begin
 261                                 rule rl_connect_qspi1_to_plic;
 262                                         `ifdef QSPI1
 263                                                 if(qspi1.interrupts()[i-20]==1'b1) begin
 264                                                         ff_gateway_queue[i].enq(1);
 265                                                         plic.ifc_external_irq[i].irq_frm_gateway(True);
 266                                                 end
 267                `else
 268                                                 ff_gateway_queue[i].enq(0);
 269                `endif
 270             endrule
 271                         end
 272
 273                         `ifdef UART0
 274                                 SyncBitIfc#(Bit#(1)) uart0_interrupt <-mkSyncBitToCC(uart_clock,uart_reset);
 275                                 rule synchronize_the_uart0_interrupt;
 276                                         uart0_interrupt.send(uart0.irq);
 277                                 endrule
 278                         `endif
 279                         rule rl_connect_uart_to_plic;
 280                                 `ifdef UART0
 281                                         if(uart0_interrupt.read==1'b1) begin
 282                                                 ff_gateway_queue[27].enq(1);
 283                                                 plic.ifc_external_irq[27].irq_frm_gateway(True);
 284                end
 285
 286             `else
 287                                         ff_gateway_queue[27].enq(0);
 288             `endif
 289          endrule
 290
 291                         for(Integer i = 28; i<`INTERRUPT_PINS; i=i+1) begin
 292                                 rule rl_raise_interrupts;
 293                                         if((i-28)<`IONum) begin //Peripheral interrupts
 294                                                 if(gpio.to_plic[i-28]==1'b1) begin
 295                                                         plic.ifc_external_irq[i].irq_frm_gateway(True);
 296                                                                 ff_gateway_queue[i].enq(1);
 297                   end
 298                                         end
 299                                 endrule
 300                         end
 301
 302          rule rl_completion_msg_from_plic;
 303                                 let id <- plic.intrpt_completion;
 304             interrupt_id <= id;
 305             `ifdef verbose $display("Dequeing the FIFO -- PLIC Interrupt Serviced id: %d",id); `endif
 306                         endrule
 307
 308          for(Integer i=0; i <`INTERRUPT_PINS; i=i+1) begin
 309                                 rule deq_gateway_queue;
 310                                         if(interrupt_id==fromInteger(i)) begin
 311                                                 ff_gateway_queue[i].deq;
 312                   `ifdef $display($time,"Dequeing the Interrupt request for ID: %d",i); `endif
 313                end
 314             endrule
 315          end
 316
 317
 318                 `endif
 319                         /*======================================================= */
 320
 321                 /* ===== interface definition =======*/
 322                 interface axi_slave=bridge.axi_slave;
 323                 `ifdef PLIC method intrpt_note = plic.intrpt_note; `endif
 324                 `ifdef CLINT
 325                         method msip_int=clint.msip_int;
 326                         method mtip_int=clint.mtip_int;
 327                         method mtime=clint.mtime;
 328                 `endif
 329                 `ifdef I2C0
 330                         method i2c0_isint=i2c0.isint;
 331                 `endif
 332                 `ifdef I2C1
 333                         method i2c1_isint=i2c1.isint;
 334                 `endif
 335                 `ifdef QSPI0 method     qspi0_isint=qspi0.interrupts[5]; `endif
 336                 `ifdef QSPI1 method     qspi1_isint=qspi1.interrupts[5]; `endif
 337                 `ifdef UART0 method uart0_intr=uart0.irq; `endif
 338                 interface SP_ios slow_ios;
 339 /* template for dedicated peripherals
 340                         `ifdef UART0
 341                                 interface uart0_coe=uart0.coe_rs232;
 342                         `endif
 343                         `ifdef UART1
 344                                 interface uart1_coe=uart1.coe_rs232;
 345                         `endif
 346                         `ifdef I2C0
 347                                 interface i2c0_out=i2c0.out;
 348                         `endif
 349                         `ifdef I2C1
 350                                 interface i2c1_out=i2c1.out;
 351                         `endif
 352                         `ifdef QSPI0
 353                                 interface qspi0_out = qspi0.out;
 354                         `endif
 355                         `ifdef QSPI1
 356                                 interface qspi1_out = qspi1.out;
 357                         `endif
 358                         `ifdef AXIEXP
 359                                 interface axiexp1_out=axiexp1.slave_out;
 360                                 interface axiexp1_in=axiexp1.slave_in;
 361                         `endif
 362       `ifdef PWM_AXI4Lite
 363         interface pwm_o = pwm_bus.pwm_io;
 364       `endif
 365 */
 366                 endinterface
 367     // NEEL EDIT
 368     interface iocell_side=pinmux.iocell_side;
 369     //interface pad_config0= gpioa.pad_config;
 370     method Action external_int(Bit#(32) in);
 371       wr_interrupt<= in;
 372     endmethod
 373     // NEEL EDIT OVER
 374                 /*===================================*/
 375         endmodule
 376 endpackage