src/bsv/bsv_lib/soc_template.bsv

   1 /*
   2 Copyright (c) 2013, IIT Madras
   3 All rights reserved.
   4
   5 Redistribution and use in source and binary forms, with or without
   6 modification, are permitted provided that the following conditions
   7 are met:
   8
   9 *  Redistributions of source code must retain the above copyright notice,
  10    this list of conditions and the following disclaimer.
  11 *  Redistributions in binary form must reproduce the above copyright
  12    notice, this list of conditions and the following disclaimer in the
  13    documentation and/or other materials provided with the distribution.
  14 *  Neither the name of IIT Madras  nor the names of its contributors
  15    may be used to endorse or promote products derived from this software
  16    without specific prior written permission.
  17
  18 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  19 "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  20 LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  21 A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  22 HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  23 SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
  24 TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
  25 PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
  26 LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
  27 NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  28 SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  29 -------------------------------------------------------------------
  30 */
  31 package socgen;
  32     /*====== Package imports === */
  33     import FIFO::*;
  34     import FIFOF::*;
  35     import SpecialFIFOs::*;
  36     import GetPut::*;
  37     import ClientServer::*;
  38     import Vector::*;
  39     import Connectable::*;
  40     import Clocks::*;
  41
  42     /*=== Project imports === */
  43     import ifc_sync:: *;
  44     import ConcatReg::*;
  45     import AXI4_Types::*;
  46     import AXI4_Fabric::*;
  47     import defined_types::*;
  48     import MemoryMap             :: *;
  49     import slow_peripherals::*;
  50     import fast_memory_map::*;
  51     import slow_memory_map::*;
  52 `ifdef DEBUG
  53     `include "defines.bsv"
  54 `endif
  55     `include "instance_defines.bsv"
  56     `include "core_parameters.bsv"
  57 {8}
  58
  59     `ifdef DMA
  60         import DMA                               :: *;
  61     `endif
  62     `ifdef BOOTROM
  63         import BootRom                  ::*;
  64     `endif
  65     `ifdef BRAM
  66         import Memory_AXI4      ::*;
  67     `endif
  68     `ifdef TCMemory
  69         import TCM::*;
  70     `endif
  71     `ifdef Debug
  72         import DebugModule::*;
  73     `else
  74         import core::*;
  75     `endif
  76     `ifdef  VME
  77         import vme_top ::*;
  78     `endif
  79
  80     `ifdef VME
  81         import vme_master::*;
  82     `endif
  83 {0}
  84
  85     /*========================= */
  86     interface Ifc_Soc;
  87         interface SP_dedicated_ios slow_ios;
  88         interface IOCellSide iocell_side;
  89         (*always_ready,always_enabled*)
  90         method Action boot_sequence(Bit#(1) bootseq);
  91
  92         `ifdef DDR
  93             (*prefix="M_AXI"*) interface
  94                    AXI4_Master_IFC#(`PADDR, `DATA, `USERSPACE) master;
  95         `endif
  96         `ifdef HYPER
  97              (*always_ready,always_enabled*)
  98              interface Ifc_flash ifc_flash;
  99         `endif
 100         /*=============================================== */
 101         `ifdef VME
 102              interface Vme_out  proc_ifc;
 103              interface Data_bus_inf proc_dbus;
 104         `endif
 105 {1}
 106     endinterface
 107
 108     //============ mkSoc module =================
 109
 110     (*synthesize*)
 111     module mkSoc #(Bit#(`VADDR) reset_vector,
 112                  Clock slow_clock, Reset slow_reset, Clock uart_clock,
 113                  Reset uart_reset, Clock clk0, Clock tck, Reset trst
 114                  `ifdef PWM_AXI4Lite ,Clock ext_pwm_clock `endif )(Ifc_Soc);
 115         Clock core_clock <-exposeCurrentClock; // slow peripheral clock
 116         Reset core_reset <-exposeCurrentReset; // slow peripheral reset
 117 {2}
 118         `ifdef Debug
 119             Ifc_DebugModule core<-mkDebugModule(reset_vector);
 120         `else
 121             Ifc_core_AXI4 core <-mkcore_AXI4(reset_vector);
 122         `endif
 123         `ifdef BOOTROM
 124             BootRom_IFC bootrom <-mkBootRom;
 125         `endif
 126         `ifdef BRAM
 127             Memory_IFC#(`SDRAMMemBase,`Addr_space)main_memory <-
 128                         mkMemory("code.mem.MSB","code.mem.LSB","MainMEM");
 129         `endif
 130         `ifdef TCMemory
 131             Ifc_TCM                                     tcm                             <- mkTCM;
 132         `endif
 133         `ifdef DMA
 134             DmaC#(7,`NUM_DMACHANNELS) dma       <- mkDMA();
 135         `endif
 136             `ifdef VME
 137             Ifc_vme_top             vme             <-mkvme_top();
 138             `endif
 139         Ifc_slow_peripherals slow_peripherals <-mkslow_peripherals(
 140                           core_clock, core_reset,
 141                           uart_clock, uart_reset,
 142                           clocked_by slow_clock, reset_by slow_reset
 143                           `ifdef PWM_AXI4Lite , ext_pwm_clock `endif );
 144
 145         // clock sync mkConnections
 146 {12}
 147
 148         // Fabric
 149         AXI4_Fabric_IFC #(Num_Masters, Num_Fast_Slaves,
 150                           `PADDR, `DATA,`USERSPACE)
 151                         fabric <- mkAXI4_Fabric(fn_addr_to_slave_num);
 152
 153         // Connect traffic generators to fabric
 154         mkConnection (core.dmem_master,fabric.v_from_masters
 155                               [fromInteger(valueOf(Dmem_master_num))]);
 156         mkConnection (core.imem_master, fabric.v_from_masters
 157                               [fromInteger(valueOf(Imem_master_num))]);
 158         `ifdef Debug
 159             mkConnection (core.debug_master, fabric.v_from_masters
 160                               [fromInteger(valueOf(Debug_master_num))]);
 161         `endif
 162         `ifdef DMA
 163          mkConnection (dma.mmu, fabric.v_from_masters
 164                               [fromInteger(valueOf(DMA_master_num))]);
 165         `endif
 166 {13}
 167
 168
 169         // Connect fabric to memory slaves
 170             `ifdef Debug
 171                 mkConnection (fabric.v_to_slaves
 172                               [fromInteger(valueOf(Debug_slave_num))],
 173                               core.debug_slave);
 174             `endif
 175             `ifdef SDRAM
 176                 mkConnection (fabric.v_to_slaves
 177                               [fromInteger(valueOf(Sdram_slave_num))],
 178                               sdram.axi4_slave_sdram); //
 179             mkConnection (fabric.v_to_slaves
 180                               [fromInteger(valueOf(Sdram_cfg_slave_num))],
 181                               sdram.axi4_slave_cntrl_reg); //
 182       `endif
 183       `ifdef BRAM
 184                 mkConnection(fabric.v_to_slaves
 185                               [fromInteger(valueOf(Sdram_slave_num))],
 186                               main_memory.axi_slave);
 187             `endif
 188             `ifdef BOOTROM
 189                 mkConnection (fabric.v_to_slaves
 190                               [fromInteger(valueOf(BootRom_slave_num))],
 191                               bootrom.axi_slave);
 192             `endif
 193             `ifdef DMA
 194             mkConnection (fabric.v_to_slaves
 195                               [fromInteger(valueOf(Dma_slave_num))],
 196                               dma.cfg); //DMA slave
 197             `endif
 198             `ifdef TCMemory
 199                 mkConnection (fabric.v_to_slaves
 200                               [fromInteger(valueOf(TCM_slave_num))],
 201                               tcm.axi_slave);
 202             `endif
 203             mkConnection(fabric.v_to_slaves
 204                               [fromInteger(valueOf(SlowPeripheral_slave_num))],
 205                               slow_peripherals.axi_slave);
 206             `ifdef VME
 207                 mkConnection (fabric.v_to_slaves
 208                               [fromInteger(valueOf(VME_slave_num))],
 209                               vme.slave_axi_vme);
 210             `endif
 211
 212 //          pin connections
 213 {9}
 214
 215             // fabric connections
 216 {5}
 217
 218             `ifdef DMA
 219             // rule to connect all interrupt lines to the DMA
 220             // All the interrupt lines to DMA are active
 221             // HIGH. For peripherals that are not connected,
 222             // or those which do not
 223             // generate an interrupt (like TCM), drive a constant 1
 224             // on the corresponding interrupt line.
 225 {7}
 226             `endif
 227
 228
 229         /*==== Synchornization between the JTAG and the Debug Module ===== */
 230         `ifdef Debug
 231             SyncFIFOIfc#(Bit#(40)) sync_request_to_dm <-
 232                                         mkSyncFIFOToCC(1,tck,trst);
 233             SyncFIFOIfc#(Bit#(34)) sync_response_from_dm <-
 234                                         mkSyncFIFOFromCC(1,tck);
 235             rule connect_tap_request_to_syncfifo;
 236                 let x<-tap.request_to_dm;
 237                 sync_request_to_dm.enq(x);
 238             endrule
 239             rule read_synced_request_to_dm;
 240                 sync_request_to_dm.deq;
 241                 core.request_from_dtm(sync_request_to_dm.first);
 242             endrule
 243
 244             rule connect_debug_response_to_syncfifo;
 245                 let x<-core.response_to_dtm;
 246                 sync_response_from_dm.enq(x);
 247             endrule
 248             rule read_synced_response_from_dm;
 249                 sync_response_from_dm.deq;
 250                 tap.response_from_dm(sync_response_from_dm.first);
 251             endrule
 252         `endif
 253         /*============================================================ */
 254
 255         `ifdef FlexBus
 256             //rule drive_flexbus_inputs;
 257                //flexbus.flexbus_side.m_TAn(1'b1);
 258                //flexbus.flexbus_side.m_din(32'haaaaaaaa);
 259             //endrule
 260          `endif
 261
 262         `ifdef CLINT
 263             SyncBitIfc#(Bit#(1)) clint_mtip_int <-
 264                                         mkSyncBitToCC(slow_clock,slow_reset);
 265             SyncBitIfc#(Bit#(1)) clint_msip_int <-
 266                                         mkSyncBitToCC(slow_clock,slow_reset);
 267             Reg#(Bit#(`DATA)) clint_mtime_value <-
 268                                         mkSyncRegToCC(0,slow_clock,slow_reset);
 269             rule synchronize_clint_data;
 270                 clint_mtip_int.send(slow_peripherals.mtip_int);
 271                 clint_msip_int.send(slow_peripherals.msip_int);
 272                 clint_mtime_value<=slow_peripherals.mtime;
 273             endrule
 274             rule connect_msip_mtip_from_clint;
 275                 core.clint_msip(clint_msip_int.read);
 276                 core.clint_mtip(clint_mtip_int.read);
 277             core.clint_mtime(clint_mtime_value);
 278             endrule
 279         `endif
 280         `ifdef PLIC
 281             Reg#(Tuple2#(Bool,Bool)) plic_interrupt_note <-
 282                                         mkSyncRegToCC(tuple2(False,False),
 283                                                       slow_clock,slow_reset);
 284             rule synchronize_interrupts;
 285                 let note <- slow_peripherals.intrpt_note;
 286                 plic_interrupt_note<=note;
 287             endrule
 288             rule rl_send_external_interrupt_to_csr;
 289                 core.set_external_interrupt(plic_interrupt_note);
 290             endrule
 291         `endif
 292
 293         `ifdef VME
 294             interface  proc_ifc = vme.proc_ifc;
 295             interface   proc_dbus = vme.proc_dbus;
 296         `endif
 297          method Action boot_sequence(Bit#(1) bootseq) =
 298                             core.boot_sequence(bootseq);
 299         `ifdef DDR
 300           interface master=fabric.v_to_slaves
 301                                 [fromInteger(valueOf(Sdram_slave_num))];
 302         `endif
 303         interface slow_ios = slow_peripherals.slow_ios;
 304         interface iocell_side = slow_peripherals.iocell_side;
 305
 306 {6}
 307     endmodule
 308 endpackage