src/bsv/bsv_lib/soc_template.bsv

   1 /*
   2 Copyright (c) 2013, IIT Madras
   3 All rights reserved.
   4
   5 Redistribution and use in source and binary forms, with or without
   6 modification, are permitted provided that the following conditions
   7 are met:
   8
   9 *  Redistributions of source code must retain the above copyright notice,
  10    this list of conditions and the following disclaimer.
  11 *  Redistributions in binary form must reproduce the above copyright
  12    notice, this list of conditions and the following disclaimer in the
  13    documentation and/or other materials provided with the distribution.
  14 *  Neither the name of IIT Madras  nor the names of its contributors
  15    may be used to endorse or promote products derived from this software
  16    without specific prior written permission.
  17
  18 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  19 "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  20 LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  21 A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  22 HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  23 SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
  24 TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
  25 PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
  26 LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
  27 NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  28 SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  29 -------------------------------------------------------------------
  30 */
  31 package socgen;
  32     /*====== Package imports === */
  33     import FIFO::*;
  34     import FIFOF::*;
  35     import SpecialFIFOs::*;
  36     import GetPut::*;
  37     import ClientServer::*;
  38     import Vector::*;
  39     import Connectable::*;
  40     import Clocks::*;
  41
  42     /*=== Project imports === */
  43     import ifc_sync:: *;
  44     import ConcatReg::*;
  45     import AXI4_Types::*;
  46     import AXI4_Fabric::*;
  47     import defined_types::*;
  48     import MemoryMap             :: *;
  49     import slow_peripherals::*;
  50     import fast_memory_map::*;
  51     import slow_memory_map::*;
  52 `ifdef DEBUG
  53     `include "defines.bsv"
  54 `endif
  55     `include "instance_defines.bsv"
  56     `include "core_parameters.bsv"
  57 {8}
  58
  59     `ifdef DMA
  60         import DMA                               :: *;
  61     `endif
  62     `ifdef BOOTROM
  63         import BootRom                  ::*;
  64     `endif
  65     `ifdef BRAM
  66         import Memory_AXI4      ::*;
  67     `endif
  68     `ifdef TCMemory
  69         import TCM::*;
  70     `endif
  71     `ifdef Debug
  72         import DebugModule::*;
  73     `else
  74         import core::*;
  75     `endif
  76     `ifdef  VME
  77         import vme_top ::*;
  78     `endif
  79
  80     `ifdef VME
  81         import vme_master::*;
  82     `endif
  83 {0}
  84
  85     /*========================= */
  86     interface Ifc_Soc;
  87         interface SP_dedicated_ios slow_ios;
  88         interface IOCellSide iocell_side;
  89         (*always_ready,always_enabled*)
  90         method Action boot_sequence(Bit#(1) bootseq);
  91
  92         `ifdef SDRAM
  93             (*always_ready*) interface Ifc_sdram_out sdram_out;
  94         `endif
  95         `ifdef DDR
  96             (*prefix="M_AXI"*) interface
  97                    AXI4_Master_IFC#(`PADDR, `DATA, `USERSPACE) master;
  98         `endif
  99         `ifdef HYPER
 100              (*always_ready,always_enabled*)
 101              interface Ifc_flash ifc_flash;
 102         `endif
 103         /*=============================================== */
 104         `ifdef VME
 105              interface Vme_out  proc_ifc;
 106              interface Data_bus_inf proc_dbus;
 107         `endif
 108 {1}
 109     endinterface
 110
 111     //============ mkSoc module =================
 112
 113     (*synthesize*)
 114     module mkSoc #(Bit#(`VADDR) reset_vector,
 115                  Clock slow_clock, Reset slow_reset, Clock uart_clock,
 116                  Reset uart_reset, Clock clk0, Clock tck, Reset trst
 117                  `ifdef PWM_AXI4Lite ,Clock ext_pwm_clock `endif )(Ifc_Soc);
 118         Clock core_clock <-exposeCurrentClock; // slow peripheral clock
 119         Reset core_reset <-exposeCurrentReset; // slow peripheral reset
 120 {2}
 121         `ifdef Debug
 122             Ifc_DebugModule core<-mkDebugModule(reset_vector);
 123         `else
 124             Ifc_core_AXI4 core <-mkcore_AXI4(reset_vector);
 125         `endif
 126         `ifdef BOOTROM
 127             BootRom_IFC bootrom <-mkBootRom;
 128         `endif
 129         `ifdef BRAM
 130             Memory_IFC#(`SDRAMMemBase,`Addr_space)main_memory <-
 131                         mkMemory("code.mem.MSB","code.mem.LSB","MainMEM");
 132         `endif
 133         `ifdef TCMemory
 134             Ifc_TCM                                     tcm                             <- mkTCM;
 135         `endif
 136         `ifdef DMA
 137             DmaC#(7,`NUM_DMACHANNELS) dma       <- mkDMA();
 138         `endif
 139             `ifdef VME
 140             Ifc_vme_top             vme             <-mkvme_top();
 141             `endif
 142         Ifc_slow_peripherals slow_peripherals <-mkslow_peripherals(
 143                           core_clock, core_reset,
 144                           uart_clock, uart_reset,
 145                           clocked_by slow_clock, reset_by slow_reset
 146                           `ifdef PWM_AXI4Lite , ext_pwm_clock `endif );
 147
 148         // clock sync mkConnections
 149 {12}
 150
 151         // Fabric
 152         AXI4_Fabric_IFC #(Num_Masters, Num_Fast_Slaves,
 153                           `PADDR, `DATA,`USERSPACE)
 154                         fabric <- mkAXI4_Fabric(fn_addr_to_slave_num);
 155
 156         // Connect traffic generators to fabric
 157         mkConnection (core.dmem_master,fabric.v_from_masters
 158                               [fromInteger(valueOf(Dmem_master_num))]);
 159         mkConnection (core.imem_master, fabric.v_from_masters
 160                               [fromInteger(valueOf(Imem_master_num))]);
 161         `ifdef Debug
 162             mkConnection (core.debug_master, fabric.v_from_masters
 163                               [fromInteger(valueOf(Debug_master_num))]);
 164         `endif
 165         `ifdef DMA
 166          mkConnection (dma.mmu, fabric.v_from_masters
 167                               [fromInteger(valueOf(DMA_master_num))]);
 168         `endif
 169 {13}
 170
 171
 172         // Connect fabric to memory slaves
 173             `ifdef Debug
 174                 mkConnection (fabric.v_to_slaves
 175                               [fromInteger(valueOf(Debug_slave_num))],
 176                               core.debug_slave);
 177             `endif
 178             `ifdef SDRAM
 179                 mkConnection (fabric.v_to_slaves
 180                               [fromInteger(valueOf(Sdram_slave_num))],
 181                               sdram.axi4_slave_sdram); //
 182             mkConnection (fabric.v_to_slaves
 183                               [fromInteger(valueOf(Sdram_cfg_slave_num))],
 184                               sdram.axi4_slave_cntrl_reg); //
 185       `endif
 186       `ifdef BRAM
 187                 mkConnection(fabric.v_to_slaves
 188                               [fromInteger(valueOf(Sdram_slave_num))],
 189                               main_memory.axi_slave);
 190             `endif
 191             `ifdef BOOTROM
 192                 mkConnection (fabric.v_to_slaves
 193                               [fromInteger(valueOf(BootRom_slave_num))],
 194                               bootrom.axi_slave);
 195             `endif
 196             `ifdef DMA
 197             mkConnection (fabric.v_to_slaves
 198                               [fromInteger(valueOf(Dma_slave_num))],
 199                               dma.cfg); //DMA slave
 200             `endif
 201             `ifdef TCMemory
 202                 mkConnection (fabric.v_to_slaves
 203                               [fromInteger(valueOf(TCM_slave_num))],
 204                               tcm.axi_slave);
 205             `endif
 206             mkConnection(fabric.v_to_slaves
 207                               [fromInteger(valueOf(SlowPeripheral_slave_num))],
 208                               slow_peripherals.axi_slave);
 209             `ifdef VME
 210                 mkConnection (fabric.v_to_slaves
 211                               [fromInteger(valueOf(VME_slave_num))],
 212                               vme.slave_axi_vme);
 213             `endif
 214
 215 //          pin connections
 216 {9}
 217
 218             // fabric connections
 219 {5}
 220
 221             `ifdef DMA
 222             // rule to connect all interrupt lines to the DMA
 223             // All the interrupt lines to DMA are active
 224             // HIGH. For peripherals that are not connected,
 225             // or those which do not
 226             // generate an interrupt (like TCM), drive a constant 1
 227             // on the corresponding interrupt line.
 228 {7}
 229             `endif
 230
 231
 232         /*==== Synchornization between the JTAG and the Debug Module ===== */
 233         `ifdef Debug
 234             SyncFIFOIfc#(Bit#(40)) sync_request_to_dm <-
 235                                         mkSyncFIFOToCC(1,tck,trst);
 236             SyncFIFOIfc#(Bit#(34)) sync_response_from_dm <-
 237                                         mkSyncFIFOFromCC(1,tck);
 238             rule connect_tap_request_to_syncfifo;
 239                 let x<-tap.request_to_dm;
 240                 sync_request_to_dm.enq(x);
 241             endrule
 242             rule read_synced_request_to_dm;
 243                 sync_request_to_dm.deq;
 244                 core.request_from_dtm(sync_request_to_dm.first);
 245             endrule
 246
 247             rule connect_debug_response_to_syncfifo;
 248                 let x<-core.response_to_dtm;
 249                 sync_response_from_dm.enq(x);
 250             endrule
 251             rule read_synced_response_from_dm;
 252                 sync_response_from_dm.deq;
 253                 tap.response_from_dm(sync_response_from_dm.first);
 254             endrule
 255         `endif
 256         /*============================================================ */
 257
 258         `ifdef FlexBus
 259             //rule drive_flexbus_inputs;
 260                //flexbus.flexbus_side.m_TAn(1'b1);
 261                //flexbus.flexbus_side.m_din(32'haaaaaaaa);
 262             //endrule
 263          `endif
 264
 265         `ifdef CLINT
 266             SyncBitIfc#(Bit#(1)) clint_mtip_int <-
 267                                         mkSyncBitToCC(slow_clock,slow_reset);
 268             SyncBitIfc#(Bit#(1)) clint_msip_int <-
 269                                         mkSyncBitToCC(slow_clock,slow_reset);
 270             Reg#(Bit#(`DATA)) clint_mtime_value <-
 271                                         mkSyncRegToCC(0,slow_clock,slow_reset);
 272             rule synchronize_clint_data;
 273                 clint_mtip_int.send(slow_peripherals.mtip_int);
 274                 clint_msip_int.send(slow_peripherals.msip_int);
 275                 clint_mtime_value<=slow_peripherals.mtime;
 276             endrule
 277             rule connect_msip_mtip_from_clint;
 278                 core.clint_msip(clint_msip_int.read);
 279                 core.clint_mtip(clint_mtip_int.read);
 280             core.clint_mtime(clint_mtime_value);
 281             endrule
 282         `endif
 283         `ifdef PLIC
 284             Reg#(Tuple2#(Bool,Bool)) plic_interrupt_note <-
 285                                         mkSyncRegToCC(tuple2(False,False),
 286                                                       slow_clock,slow_reset);
 287             rule synchronize_interrupts;
 288                 let note <- slow_peripherals.intrpt_note;
 289                 plic_interrupt_note<=note;
 290             endrule
 291             rule rl_send_external_interrupt_to_csr;
 292                 core.set_external_interrupt(plic_interrupt_note);
 293             endrule
 294         `endif
 295
 296         `ifdef VME
 297             interface  proc_ifc = vme.proc_ifc;
 298             interface   proc_dbus = vme.proc_dbus;
 299         `endif
 300          method Action boot_sequence(Bit#(1) bootseq) =
 301                             core.boot_sequence(bootseq);
 302         `ifdef SDRAM
 303             interface sdram_out=sdram.ifc_sdram_out;
 304         `endif
 305         `ifdef DDR
 306           interface master=fabric.v_to_slaves
 307                                 [fromInteger(valueOf(Sdram_slave_num))];
 308         `endif
 309         interface slow_ios = slow_peripherals.slow_ios;
 310         interface iocell_side = slow_peripherals.iocell_side;
 311
 312 {6}
 313     endmodule
 314 endpackage