2 Copyright (c) 2013, IIT Madras
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14 * Neither the name of IIT Madras nor the names of its contributors
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16 without specific prior written permission.
18 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
19 "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
20 LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
21 A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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24 TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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27 NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
28 SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 -------------------------------------------------------------------
32 /*====== Package imports === */
35 import SpecialFIFOs::*;
37 import ClientServer::*;
39 import Connectable::*;
41 /*========================== */
42 /*=== Project imports === */
45 import AXI4_Fabric::*;
46 import defined_types::*;
47 import MemoryMap :: *;
48 import slow_peripherals::*;
49 `include "defines.bsv"
50 `include "instance_defines.bsv"
52 /*====== AXI4 slave declarations =======*/
54 /*====== AXI4 Master declarations =======*/
68 import Memory_AXI4 ::*;
75 import DebugModule::*;
87 import FlexBus_Types::*;
91 /*========================= */
93 interface SP_ios slow_ios;
94 (*always_ready,always_enabled*)
95 method Action boot_sequence(Bit#(1) bootseq);
98 (*always_ready*) interface Ifc_sdram_out sdram_out;
101 (*prefix="M_AXI"*) interface
102 AXI4_Master_IFC#(`PADDR, `Reg_width, `USERSPACE) master;
105 (*always_ready,always_enabled*)
106 interface Ifc_flash ifc_flash;
108 /*=============================================== */
110 interface Vme_out proc_ifc;
111 interface Data_bus_inf proc_dbus;
114 interface FlexBus_Master_IFC flexbus_out;
119 module mkSoc #(Bit#(`VADDR) reset_vector,
120 Clock slow_clock, Reset slow_reset, Clock uart_clock,
121 Reset uart_reset, Clock clk0, Clock tck, Reset trst
122 `ifdef PWM_AXI4Lite ,Clock ext_pwm_clock `endif )(Ifc_Soc);
123 Clock core_clock <-exposeCurrentClock; // slow peripheral clock
124 Reset core_reset <-exposeCurrentReset; // slow peripheral reset
127 Ifc_DebugModule core<-mkDebugModule(reset_vector);
129 Ifc_core_AXI4 core <-mkcore_AXI4(reset_vector);
132 BootRom_IFC bootrom <-mkBootRom;
135 Ifc_sdr_slave sdram<- mksdr_axi4_slave(clk0);
138 Memory_IFC#(`SDRAMMemBase,`Addr_space)main_memory <-
139 mkMemory("code.mem.MSB","code.mem.LSB","MainMEM");
142 Ifc_TCM tcm <- mkTCM;
145 DmaC#(7,`NUM_DMACHANNELS) dma <- mkDMA();
148 Ifc_vme_top vme <-mkvme_top();
151 AXI4_Slave_to_FlexBus_Master_Xactor_IFC #(32, 64,0)
152 flexbus <- mkAXI4_Slave_to_FlexBus_Master_Xactor;
154 Ifc_slow_peripherals slow_peripherals <-mkslow_peripherals(
155 core_clock, core_reset, uart_clock,
156 uart_reset, clocked_by slow_clock , reset_by slow_reset
157 `ifdef PWM_AXI4Lite , ext_pwm_clock `endif );
160 AXI4_Fabric_IFC #(Num_Masters, Num_Slaves, `PADDR, `Reg_width,`USERSPACE)
161 fabric <- mkAXI4_Fabric(fn_addr_to_slave_num);
163 // Connect traffic generators to fabric
164 mkConnection (core.dmem_master,fabric.v_from_masters
165 [fromInteger(valueOf(Dmem_master_num))]);
166 mkConnection (core.imem_master, fabric.v_from_masters
167 [fromInteger(valueOf(Imem_master_num))]);
169 mkConnection (core.debug_master, fabric.v_from_masters
170 [fromInteger(valueOf(Debug_master_num))]);
173 mkConnection (dma.mmu, fabric.v_from_masters
174 [fromInteger(valueOf(DMA_master_num))]);
178 // Connect fabric to memory slaves
180 mkConnection (fabric.v_to_slaves
181 [fromInteger(valueOf(Debug_slave_num))],
185 mkConnection (fabric.v_to_slaves
186 [fromInteger(valueOf(Sdram_slave_num))],
187 sdram.axi4_slave_sdram); //
188 mkConnection (fabric.v_to_slaves
189 [fromInteger(valueOf(Sdram_cfg_slave_num))],
190 sdram.axi4_slave_cntrl_reg); //
193 mkConnection(fabric.v_to_slaves
194 [fromInteger(valueOf(Sdram_slave_num))],
195 main_memory.axi_slave);
198 mkConnection (fabric.v_to_slaves
199 [fromInteger(valueOf(BootRom_slave_num))],
203 mkConnection (fabric.v_to_slaves
204 [fromInteger(valueOf(Dma_slave_num))],
205 dma.cfg); //DMA slave
208 mkConnection (fabric.v_to_slaves
209 [fromInteger(valueOf(TCM_slave_num))],
212 mkConnection(fabric.v_to_slaves
213 [fromInteger(valueOf(SlowPeripheral_slave_num))],
214 slow_peripherals.axi_slave);
216 mkConnection (fabric.v_to_slaves
217 [fromInteger(valueOf(VME_slave_num))],
221 mkConnection (fabric.v_to_slaves
222 [fromInteger(valueOf(FlexBus_slave_num))],
226 // fabric connections
230 // rule to connect all interrupt lines to the DMA
231 // All the interrupt lines to DMA are active
232 // HIGH. For peripherals that are not connected,
233 // or those which do not
234 // generate an interrupt (like TCM), drive a constant 1
235 // on the corresponding interrupt line.
240 /*==== Synchornization between the JTAG and the Debug Module ===== */
242 SyncFIFOIfc#(Bit#(40)) sync_request_to_dm <-
243 mkSyncFIFOToCC(1,tck,trst);
244 SyncFIFOIfc#(Bit#(34)) sync_response_from_dm <-
245 mkSyncFIFOFromCC(1,tck);
246 rule connect_tap_request_to_syncfifo;
247 let x<-tap.request_to_dm;
248 sync_request_to_dm.enq(x);
250 rule read_synced_request_to_dm;
251 sync_request_to_dm.deq;
252 core.request_from_dtm(sync_request_to_dm.first);
255 rule connect_debug_response_to_syncfifo;
256 let x<-core.response_to_dtm;
257 sync_response_from_dm.enq(x);
259 rule read_synced_response_from_dm;
260 sync_response_from_dm.deq;
261 tap.response_from_dm(sync_response_from_dm.first);
264 /*============================================================ */
267 //rule drive_flexbus_inputs;
268 //flexbus.flexbus_side.m_TAn(1'b1);
269 //flexbus.flexbus_side.m_din(32'haaaaaaaa);
274 SyncBitIfc#(Bit#(1)) clint_mtip_int <-
275 mkSyncBitToCC(slow_clock,slow_reset);
276 SyncBitIfc#(Bit#(1)) clint_msip_int <-
277 mkSyncBitToCC(slow_clock,slow_reset);
278 Reg#(Bit#(`Reg_width)) clint_mtime_value <-
279 mkSyncRegToCC(0,slow_clock,slow_reset);
280 rule synchronize_clint_data;
281 clint_mtip_int.send(slow_peripherals.mtip_int);
282 clint_msip_int.send(slow_peripherals.msip_int);
283 clint_mtime_value<=slow_peripherals.mtime;
285 rule connect_msip_mtip_from_clint;
286 core.clint_msip(clint_msip_int.read);
287 core.clint_mtip(clint_mtip_int.read);
288 core.clint_mtime(clint_mtime_value);
292 Reg#(Tuple2#(Bool,Bool)) plic_interrupt_note <-
293 mkSyncRegToCC(tuple2(False,False),
294 slow_clock,slow_reset);
295 rule synchronize_interrupts;
296 let note <- slow_peripherals.intrpt_note;
297 plic_interrupt_note<=note;
299 rule rl_send_external_interrupt_to_csr;
300 core.set_external_interrupt(plic_interrupt_note);
305 interface proc_ifc = vme.proc_ifc;
306 interface proc_dbus = vme.proc_dbus;
309 interface flexbus_out = flexbus.flexbus_side;
311 method Action boot_sequence(Bit#(1) bootseq) =
312 core.boot_sequence(bootseq);
314 interface sdram_out=sdram.ifc_sdram_out;
317 interface master=fabric.v_to_slaves
318 [fromInteger(valueOf(Sdram_slave_num))];
320 interface slow_ios=slow_peripherals.slow_ios;