src/bsv/bsv_lib/soc_template.bsv

   1 /*
   2 Copyright (c) 2013, IIT Madras
   3 All rights reserved.
   4
   5 Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
   6
   7 *  Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
   8 *  Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
   9 *  Neither the name of IIT Madras  nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.
  10
  11 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  12 ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
  13 */
  14 package Soc;
  15         /*====== Package imports === */
  16         import FIFO::*;
  17         import FIFOF::*;
  18         import SpecialFIFOs::*;
  19         import GetPut::*;
  20         import ClientServer::*;
  21         import Vector::*;
  22         import Connectable::*;
  23         import Clocks::*;
  24         /*========================== */
  25         /*=== Project imports === */
  26         import ConcatReg::*;
  27         import AXI4_Types::*;
  28         import AXI4_Fabric::*;
  29         import defined_types::*;
  30         import MemoryMap                 :: *;
  31         import slow_peripherals::*;
  32         `include "defines.bsv"
  33         `include "instance_defines.bsv"
  34
  35                 `ifdef DMA
  36                         import DMA                               :: *;
  37                 `endif
  38                 `ifdef BOOTROM
  39                         import BootRom                  ::*;
  40                 `endif
  41                 `ifdef SDRAM
  42                         import sdr_top                   :: *;
  43     `endif
  44                 `ifdef BRAM
  45                         import Memory_AXI4      ::*;
  46                 `endif
  47                 `ifdef TCMemory
  48                         import TCM::*;
  49                 `endif
  50                 `ifdef Debug
  51                         import jtagdtm::*;
  52                         import DebugModule::*;
  53                 `else
  54                         import core::*;
  55                 `endif
  56 `ifdef  VME
  57                         import vme_top ::*;
  58 `endif
  59
  60 `ifdef VME
  61                         import vme_master::*;
  62 `endif
  63 `ifdef FlexBus
  64             import FlexBus_Types::*;
  65 `endif
  66 {0}
  67
  68         /*========================= */
  69         interface Ifc_Soc;
  70                 interface SP_ios slow_ios;
  71                 (*always_ready,always_enabled*)
  72                 method Action boot_sequence(Bit#(1) bootseq);
  73
  74                   `ifdef SDRAM
  75                         (*always_ready*) interface Ifc_sdram_out sdram_out;
  76                 `endif
  77       `ifdef DDR
  78         (*prefix="M_AXI"*) interface AXI4_Master_IFC#(`PADDR, `Reg_width, `USERSPACE) master;
  79       `endif
  80       `ifdef Debug
  81                         (*always_ready,always_enabled*)
  82                         method Action tms_i(Bit#(1) tms);
  83                         (*always_ready,always_enabled*)
  84                         method Action tdi_i(Bit#(1) tdi);
  85                         (*always_ready,always_enabled*)
  86                         method Action bs_chain_i(Bit#(1) bs_chain);
  87                         (*always_ready,always_enabled*)
  88                         method Bit#(1) shiftBscan2Edge;
  89                         (*always_ready,always_enabled*)
  90                         method Bit#(1) selectJtagInput;
  91                         (*always_ready,always_enabled*)
  92                         method Bit#(1) selectJtagOutput;
  93                         (*always_ready,always_enabled*)
  94                         method Bit#(1) updateBscan;
  95                         (*always_ready,always_enabled*)
  96                         method Bit#(1) bscan_in;
  97                         (*always_ready,always_enabled*)
  98                         method Bit#(1) scan_shift_en;
  99                         (*always_ready,always_enabled*)
 100                         method Bit#(1) tdo;
 101                         (*always_ready,always_enabled*)
 102                         method Bit#(1) tdo_oe;
 103                 `endif
 104                 `ifdef HYPER
 105                         (*always_ready,always_enabled*)
 106                    interface Ifc_flash ifc_flash;
 107                 `endif
 108         /*=============================================== */
 109            `ifdef VME
 110                         interface Vme_out  proc_ifc;
 111                         interface Data_bus_inf proc_dbus;
 112                 `endif
 113         `ifdef FlexBus
 114             interface FlexBus_Master_IFC flexbus_out;
 115         `endif
 116 {1}
 117         endinterface
 118         (*synthesize*)
 119         module mkSoc #(Bit#(`VADDR) reset_vector, Clock slow_clock, Reset slow_reset, Clock uart_clock,
 120                  Reset uart_reset, Clock clk0, Clock tck, Reset trst
 121                  `ifdef PWM_AXI4Lite ,Clock ext_pwm_clock `endif )(Ifc_Soc);
 122                 Clock core_clock <-exposeCurrentClock; // slow peripheral clock
 123                 Reset core_reset <-exposeCurrentReset; // slow peripheral reset
 124 {2}
 125       `ifdef Debug
 126                         Ifc_DebugModule core<-mkDebugModule(reset_vector);
 127                 `else
 128                         Ifc_core_AXI4 core <-mkcore_AXI4(reset_vector);
 129                 `endif
 130                 `ifdef BOOTROM
 131                         BootRom_IFC bootrom <-mkBootRom;
 132                 `endif
 133                 `ifdef SDRAM
 134                         Ifc_sdr_slave                   sdram                           <- mksdr_axi4_slave(clk0);
 135                 `endif
 136     `ifdef BRAM
 137                         Memory_IFC#(`SDRAMMemBase,`Addr_space) main_memory <- mkMemory("code.mem.MSB","code.mem.LSB","MainMEM");
 138                 `endif
 139                 `ifdef TCMemory
 140                         Ifc_TCM                                 tcm                             <- mkTCM;
 141                 `endif
 142                 `ifdef DMA
 143                         DmaC#(7,12)                             dma                             <- mkDMA();
 144                 `endif
 145                         `ifdef VME
 146                         Ifc_vme_top             vme             <-mkvme_top();
 147                         `endif
 148         `ifdef FlexBus
 149             AXI4_Slave_to_FlexBus_Master_Xactor_IFC #(32, 64,0)
 150                                             flexbus <- mkAXI4_Slave_to_FlexBus_Master_Xactor;
 151         `endif
 152                 Ifc_slow_peripherals slow_peripherals <-mkslow_peripherals(core_clock, core_reset, uart_clock,
 153           uart_reset, clocked_by slow_clock , reset_by slow_reset
 154           `ifdef PWM_AXI4Lite , ext_pwm_clock `endif );
 155
 156         // Fabric
 157         AXI4_Fabric_IFC #(Num_Masters, Num_Slaves, `PADDR, `Reg_width,`USERSPACE)
 158                                 fabric <- mkAXI4_Fabric(fn_addr_to_slave_num);
 159
 160         // Connect traffic generators to fabric
 161         mkConnection (core.dmem_master, fabric.v_from_masters [fromInteger(valueOf(Dmem_master_num))]);
 162         mkConnection (core.imem_master, fabric.v_from_masters [fromInteger(valueOf(Imem_master_num))]);
 163                 `ifdef Debug
 164                         mkConnection (core.debug_master, fabric.v_from_masters [fromInteger(valueOf(Debug_master_num))]);
 165                 `endif
 166                 `ifdef DMA
 167          mkConnection (dma.mmu, fabric.v_from_masters[fromInteger(valueOf(DMA_master_num))]);
 168                 `endif
 169
 170
 171                 // Connect fabric to memory slaves
 172                         `ifdef Debug
 173                                 mkConnection (fabric.v_to_slaves [fromInteger(valueOf(Debug_slave_num))],core.debug_slave);
 174                         `endif
 175                         `ifdef SDRAM
 176                                 mkConnection (fabric.v_to_slaves [fromInteger(valueOf(Sdram_slave_num))],       sdram.axi4_slave_sdram); //
 177                         mkConnection (fabric.v_to_slaves [fromInteger(valueOf(Sdram_cfg_slave_num))],   sdram.axi4_slave_cntrl_reg); //
 178       `endif
 179       `ifdef BRAM
 180                                 mkConnection(fabric.v_to_slaves[fromInteger(valueOf(Sdram_slave_num))],main_memory.axi_slave);
 181                         `endif
 182                         `ifdef BOOTROM
 183                                 mkConnection (fabric.v_to_slaves [fromInteger(valueOf(BootRom_slave_num))],bootrom.axi_slave);
 184                         `endif
 185                         `ifdef DMA
 186                         mkConnection (fabric.v_to_slaves [fromInteger(valueOf(Dma_slave_num))], dma.cfg); //DMA slave
 187                         `endif
 188                         `ifdef TCMemory
 189                                 mkConnection (fabric.v_to_slaves [fromInteger(valueOf(TCM_slave_num))],tcm.axi_slave);
 190                         `endif
 191                         mkConnection(fabric.v_to_slaves [fromInteger(valueOf(SlowPeripheral_slave_num))],slow_peripherals.axi_slave);
 192                         `ifdef VME
 193                                 mkConnection (fabric.v_to_slaves[fromInteger(valueOf(VME_slave_num))],vme.slave_axi_vme);
 194                         `endif
 195                         `ifdef FlexBus
 196                                 mkConnection (fabric.v_to_slaves[fromInteger(valueOf(FlexBus_slave_num))],flexbus.axi_side);
 197                         `endif
 198                         `ifdef DMA
 199                         //rule to connect all interrupt lines to the DMA
 200                         //All the interrupt lines to DMA are active HIGH. For peripherals that are not connected, or those which do not
 201                         //generate an interrupt (like TCM), drive a constant 1 on the corresponding interrupt line.
 202                                 `ifdef I2C1 SyncBitIfc#(Bit#(1)) i2c1_interrupt <-mkSyncBitToCC(slow_clock,slow_reset); `endif
 203                                 `ifdef I2C0 SyncBitIfc#(Bit#(1)) i2c0_interrupt <-mkSyncBitToCC(slow_clock,slow_reset); `endif
 204                                 `ifdef QSPI1 SyncBitIfc#(Bit#(1)) qspi1_interrupt <-mkSyncBitToCC(slow_clock,slow_reset); `endif
 205                                 `ifdef QSPI0 SyncBitIfc#(Bit#(1)) qspi0_interrupt <-mkSyncBitToCC(slow_clock,slow_reset); `endif
 206                                 `ifdef UART0 SyncBitIfc#(Bit#(1)) uart0_interrupt <-mkSyncBitToCC(uart_clock,uart_reset); `endif
 207                                 rule synchronize_i2c_interrupts;
 208                                         `ifdef I2C1 i2c1_interrupt.send(slow_peripherals.i2c1_isint); `endif
 209                                         `ifdef I2C0 i2c0_interrupt.send(slow_peripherals.i2c0_isint); `endif
 210                                 endrule
 211                                 rule synchronize_qspi_interrupts;
 212                                         `ifdef QSPI0 qspi0_interrupt.send(slow_peripherals.qspi0_isint); `endif
 213                                         `ifdef QSPI1 qspi1_interrupt.send(slow_peripherals.qspi1_isint); `endif
 214                                 endrule
 215                                 rule synchronize_uart0_interrupt;
 216                                         `ifdef UART0 uart0_interrupt.send(slow_peripherals.uart0_intr); `endif
 217                                 endrule
 218                                 rule rl_connect_interrupt_to_DMA;
 219                                         Bit#(12) lv_interrupt_to_DMA= {{'d-1,
 220                                                                                                                         `ifdef I2C1 i2c1_interrupt.read `else 1'b1 `endif ,
 221                                                                                                                         `ifdef I2C0 i2c0_interrupt.read `else 1'b1 `endif ,
 222                                                                                                                         `ifdef QSPI1 qspi1_interrupt.read `else 1'b1 `endif ,
 223                                                                                                                         1'b1,
 224                                                                                                                         `ifdef QSPI0 qspi0_interrupt.read `else 1'b1 `endif ,
 225                                                                                                                         1'b1,1'b0,
 226                                                                                                                         `ifdef UART0 uart0_interrupt.read `else 1'b1 `endif }};
 227                                         dma.interrupt_from_peripherals(lv_interrupt_to_DMA);
 228                                 endrule
 229                         `endif
 230
 231
 232                 /*======= Synchornization between the JTAG and the Debug Module ========= */
 233                 `ifdef Debug
 234                         SyncFIFOIfc#(Bit#(40)) sync_request_to_dm <-mkSyncFIFOToCC(1,tck,trst);
 235                         SyncFIFOIfc#(Bit#(34)) sync_response_from_dm <-mkSyncFIFOFromCC(1,tck);
 236                         rule connect_tap_request_to_syncfifo;
 237                                 let x<-tap.request_to_dm;
 238                                 sync_request_to_dm.enq(x);
 239                         endrule
 240                         rule read_synced_request_to_dm;
 241                                 sync_request_to_dm.deq;
 242                                 core.request_from_dtm(sync_request_to_dm.first);
 243                         endrule
 244
 245                         rule connect_debug_response_to_syncfifo;
 246                                 let x<-core.response_to_dtm;
 247                                 sync_response_from_dm.enq(x);
 248                         endrule
 249                         rule read_synced_response_from_dm;
 250                                 sync_response_from_dm.deq;
 251                                 tap.response_from_dm(sync_response_from_dm.first);
 252                         endrule
 253                 `endif
 254                 /*======================================================================= */
 255
 256         `ifdef FlexBus
 257             //rule drive_flexbus_inputs;
 258                //flexbus.flexbus_side.m_TAn(1'b1);
 259                //flexbus.flexbus_side.m_din(32'haaaaaaaa);
 260             //endrule
 261          `endif
 262
 263                 `ifdef CLINT
 264                         SyncBitIfc#(Bit#(1)) clint_mtip_int <-mkSyncBitToCC(slow_clock,slow_reset);
 265                         SyncBitIfc#(Bit#(1)) clint_msip_int <-mkSyncBitToCC(slow_clock,slow_reset);
 266                         Reg#(Bit#(`Reg_width)) clint_mtime_value <-mkSyncRegToCC(0,slow_clock,slow_reset);
 267                         rule synchronize_clint_data;
 268                                 clint_mtip_int.send(slow_peripherals.mtip_int);
 269                                 clint_msip_int.send(slow_peripherals.msip_int);
 270                                 clint_mtime_value<=slow_peripherals.mtime;
 271                         endrule
 272                         rule connect_msip_mtip_from_clint;
 273                                 core.clint_msip(clint_msip_int.read);
 274                                 core.clint_mtip(clint_mtip_int.read);
 275             core.clint_mtime(clint_mtime_value);
 276                         endrule
 277                 `endif
 278                 `ifdef PLIC
 279                         Reg#(Tuple2#(Bool,Bool)) plic_interrupt_note <-mkSyncRegToCC(tuple2(False,False),slow_clock,slow_reset);
 280                         rule synchronize_interrupts;
 281                                 let note <- slow_peripherals.intrpt_note;
 282                                 plic_interrupt_note<=note;
 283                         endrule
 284          rule rl_send_external_interrupt_to_csr;
 285                                 core.set_external_interrupt(plic_interrupt_note);
 286                         endrule
 287                 `endif
 288
 289                 `ifdef VME
 290                         interface  proc_ifc = vme.proc_ifc;
 291                         interface   proc_dbus = vme.proc_dbus;
 292                 `endif
 293                 `ifdef FlexBus
 294             interface flexbus_out = flexbus.flexbus_side;
 295                 `endif
 296       method Action boot_sequence(Bit#(1) bootseq) = core.boot_sequence(bootseq);
 297                 `ifdef SDRAM
 298                         interface sdram_out=sdram.ifc_sdram_out;
 299                 `endif
 300     `ifdef DDR
 301       interface master=fabric.v_to_slaves[fromInteger(valueOf(Sdram_slave_num))];
 302     `endif
 303                 `ifdef Debug
 304                         method Action tms_i(Bit#(1) tms);
 305                                 tap.tms_i(tms);
 306                         endmethod
 307                         method Action tdi_i(Bit#(1) tdi);
 308                                 tap.tdi_i(tdi);
 309                         endmethod
 310                         method Action bs_chain_i(Bit#(1) bs_chain);
 311                                 tap.bs_chain_i(bs_chain);
 312                         endmethod
 313                         method Bit#(1) shiftBscan2Edge=tap.shiftBscan2Edge;
 314                         method Bit#(1) selectJtagInput=tap.selectJtagInput;
 315                         method Bit#(1) selectJtagOutput=tap.selectJtagOutput;
 316                         method Bit#(1) updateBscan=tap.updateBscan;
 317                         method Bit#(1) bscan_in=tap.bscan_in;
 318             method Bit#(1) scan_shift_en=tap.scan_shift_en;
 319                         method Bit#(1) tdo=tap.tdo;
 320                         method Bit#(1) tdo_oe=tap.tdo_oe;
 321                 `endif
 322                 interface slow_ios=slow_peripherals.slow_ios;
 323
 324         endmodule
 325 endpackage