src/bsv/bsv_lib/soc_template.bsv

   1 /*
   2 Copyright (c) 2013, IIT Madras
   3 All rights reserved.
   4
   5 Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
   6
   7 *  Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
   8 *  Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
   9 *  Neither the name of IIT Madras  nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.
  10
  11 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  12 ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
  13 */
  14 package Soc;
  15         /*====== Package imports === */
  16         import FIFO::*;
  17         import FIFOF::*;
  18         import SpecialFIFOs::*;
  19         import GetPut::*;
  20         import ClientServer::*;
  21         import Vector::*;
  22         import Connectable::*;
  23         import Clocks::*;
  24         /*========================== */
  25         /*=== Project imports === */
  26         import ConcatReg::*;
  27         import AXI4_Types::*;
  28         import AXI4_Fabric::*;
  29         import defined_types::*;
  30         import MemoryMap                 :: *;
  31         import slow_peripherals::*;
  32         `include "defines.bsv"
  33         `include "instance_defines.bsv"
  34
  35                 `ifdef DMA
  36                         import DMA                               :: *;
  37                 `endif
  38                 `ifdef BOOTROM
  39                         import BootRom                  ::*;
  40                 `endif
  41                 `ifdef SDRAM
  42                         import sdr_top                   :: *;
  43     `endif
  44                 `ifdef BRAM
  45                         import Memory_AXI4      ::*;
  46                 `endif
  47                 `ifdef TCMemory
  48                         import TCM::*;
  49                 `endif
  50                 `ifdef Debug
  51                         import jtagdtm::*;
  52                         import DebugModule::*;
  53                 `else
  54                         import core::*;
  55                 `endif
  56 `ifdef  VME
  57                         import vme_top ::*;
  58 `endif
  59
  60 `ifdef VME
  61                         import vme_master::*;
  62 `endif
  63 `ifdef FlexBus
  64             import FlexBus_Types::*;
  65 `endif
  66 {0}
  67
  68         /*========================= */
  69         interface Ifc_Soc;
  70                 interface SP_ios slow_ios;
  71                 (*always_ready,always_enabled*)
  72                 method Action boot_sequence(Bit#(1) bootseq);
  73
  74                   `ifdef SDRAM
  75                         (*always_ready*) interface Ifc_sdram_out sdram_out;
  76                 `endif
  77       `ifdef DDR
  78         (*prefix="M_AXI"*) interface AXI4_Master_IFC#(`PADDR, `Reg_width, `USERSPACE) master;
  79       `endif
  80       `ifdef Debug
  81                         (*always_ready,always_enabled*)
  82                         method Action tms_i(Bit#(1) tms);
  83                         (*always_ready,always_enabled*)
  84                         method Action tdi_i(Bit#(1) tdi);
  85                         (*always_ready,always_enabled*)
  86                         method Action bs_chain_i(Bit#(1) bs_chain);
  87                         (*always_ready,always_enabled*)
  88                         method Bit#(1) shiftBscan2Edge;
  89                         (*always_ready,always_enabled*)
  90                         method Bit#(1) selectJtagInput;
  91                         (*always_ready,always_enabled*)
  92                         method Bit#(1) selectJtagOutput;
  93                         (*always_ready,always_enabled*)
  94                         method Bit#(1) updateBscan;
  95                         (*always_ready,always_enabled*)
  96                         method Bit#(1) bscan_in;
  97                         (*always_ready,always_enabled*)
  98                         method Bit#(1) scan_shift_en;
  99                         (*always_ready,always_enabled*)
 100                         method Bit#(1) tdo;
 101                         (*always_ready,always_enabled*)
 102                         method Bit#(1) tdo_oe;
 103                 `endif
 104                 `ifdef HYPER
 105                         (*always_ready,always_enabled*)
 106                    interface Ifc_flash ifc_flash;
 107                 `endif
 108         /*=============================================== */
 109            `ifdef VME
 110                         interface Vme_out  proc_ifc;
 111                         interface Data_bus_inf proc_dbus;
 112                 `endif
 113         `ifdef FlexBus
 114             interface FlexBus_Master_IFC flexbus_out;
 115         `endif
 116 {1}
 117         endinterface
 118         (*synthesize*)
 119         module mkSoc #(Bit#(`VADDR) reset_vector, Clock slow_clock, Reset slow_reset, Clock uart_clock,
 120                  Reset uart_reset, Clock clk0, Clock tck, Reset trst
 121                  `ifdef PWM_AXI4Lite ,Clock ext_pwm_clock `endif )(Ifc_Soc);
 122                 Clock core_clock <-exposeCurrentClock; // slow peripheral clock
 123                 Reset core_reset <-exposeCurrentReset; // slow peripheral reset
 124 {2}
 125       `ifdef Debug
 126                         Ifc_jtagdtm tap <-mkjtagdtm(clocked_by tck, reset_by trst);
 127          rule drive_tmp_scan_outs;
 128              tap.scan_out_1_i(1'b0);
 129              tap.scan_out_2_i(1'b0);
 130              tap.scan_out_3_i(1'b0);
 131              tap.scan_out_4_i(1'b0);
 132              tap.scan_out_5_i(1'b0);
 133          endrule
 134                         Ifc_DebugModule core<-mkDebugModule(reset_vector);
 135                 `else
 136                         Ifc_core_AXI4 core <-mkcore_AXI4(reset_vector);
 137                 `endif
 138                 `ifdef BOOTROM
 139                         BootRom_IFC bootrom <-mkBootRom;
 140                 `endif
 141                 `ifdef SDRAM
 142                         Ifc_sdr_slave                   sdram                           <- mksdr_axi4_slave(clk0);
 143                 `endif
 144     `ifdef BRAM
 145                         Memory_IFC#(`SDRAMMemBase,`Addr_space) main_memory <- mkMemory("code.mem.MSB","code.mem.LSB","MainMEM");
 146                 `endif
 147                 `ifdef TCMemory
 148                         Ifc_TCM                                 tcm                             <- mkTCM;
 149                 `endif
 150                 `ifdef DMA
 151                         DmaC#(7,12)                             dma                             <- mkDMA();
 152                 `endif
 153                         `ifdef VME
 154                         Ifc_vme_top             vme             <-mkvme_top();
 155                         `endif
 156         `ifdef FlexBus
 157             AXI4_Slave_to_FlexBus_Master_Xactor_IFC #(32, 64,0)
 158                                             flexbus <- mkAXI4_Slave_to_FlexBus_Master_Xactor;
 159         `endif
 160                 Ifc_slow_peripherals slow_peripherals <-mkslow_peripherals(core_clock, core_reset, uart_clock,
 161           uart_reset, clocked_by slow_clock , reset_by slow_reset
 162           `ifdef PWM_AXI4Lite , ext_pwm_clock `endif );
 163
 164         // Fabric
 165         AXI4_Fabric_IFC #(Num_Masters, Num_Slaves, `PADDR, `Reg_width,`USERSPACE)
 166                                 fabric <- mkAXI4_Fabric(fn_addr_to_slave_num);
 167
 168         // Connect traffic generators to fabric
 169         mkConnection (core.dmem_master, fabric.v_from_masters [fromInteger(valueOf(Dmem_master_num))]);
 170         mkConnection (core.imem_master, fabric.v_from_masters [fromInteger(valueOf(Imem_master_num))]);
 171                 `ifdef Debug
 172                         mkConnection (core.debug_master, fabric.v_from_masters [fromInteger(valueOf(Debug_master_num))]);
 173                 `endif
 174                 `ifdef DMA
 175          mkConnection (dma.mmu, fabric.v_from_masters[fromInteger(valueOf(DMA_master_num))]);
 176                 `endif
 177
 178
 179                 // Connect fabric to memory slaves
 180                         `ifdef Debug
 181                                 mkConnection (fabric.v_to_slaves [fromInteger(valueOf(Debug_slave_num))],core.debug_slave);
 182                         `endif
 183                         `ifdef SDRAM
 184                                 mkConnection (fabric.v_to_slaves [fromInteger(valueOf(Sdram_slave_num))],       sdram.axi4_slave_sdram); //
 185                         mkConnection (fabric.v_to_slaves [fromInteger(valueOf(Sdram_cfg_slave_num))],   sdram.axi4_slave_cntrl_reg); //
 186       `endif
 187       `ifdef BRAM
 188                                 mkConnection(fabric.v_to_slaves[fromInteger(valueOf(Sdram_slave_num))],main_memory.axi_slave);
 189                         `endif
 190                         `ifdef BOOTROM
 191                                 mkConnection (fabric.v_to_slaves [fromInteger(valueOf(BootRom_slave_num))],bootrom.axi_slave);
 192                         `endif
 193                         `ifdef DMA
 194                         mkConnection (fabric.v_to_slaves [fromInteger(valueOf(Dma_slave_num))], dma.cfg); //DMA slave
 195                         `endif
 196                         `ifdef TCMemory
 197                                 mkConnection (fabric.v_to_slaves [fromInteger(valueOf(TCM_slave_num))],tcm.axi_slave);
 198                         `endif
 199                         mkConnection(fabric.v_to_slaves [fromInteger(valueOf(SlowPeripheral_slave_num))],slow_peripherals.axi_slave);
 200                         `ifdef VME
 201                                 mkConnection (fabric.v_to_slaves[fromInteger(valueOf(VME_slave_num))],vme.slave_axi_vme);
 202                         `endif
 203                         `ifdef FlexBus
 204                                 mkConnection (fabric.v_to_slaves[fromInteger(valueOf(FlexBus_slave_num))],flexbus.axi_side);
 205                         `endif
 206                         `ifdef DMA
 207                         //rule to connect all interrupt lines to the DMA
 208                         //All the interrupt lines to DMA are active HIGH. For peripherals that are not connected, or those which do not
 209                         //generate an interrupt (like TCM), drive a constant 1 on the corresponding interrupt line.
 210                                 `ifdef I2C1 SyncBitIfc#(Bit#(1)) i2c1_interrupt <-mkSyncBitToCC(slow_clock,slow_reset); `endif
 211                                 `ifdef I2C0 SyncBitIfc#(Bit#(1)) i2c0_interrupt <-mkSyncBitToCC(slow_clock,slow_reset); `endif
 212                                 `ifdef QSPI1 SyncBitIfc#(Bit#(1)) qspi1_interrupt <-mkSyncBitToCC(slow_clock,slow_reset); `endif
 213                                 `ifdef QSPI0 SyncBitIfc#(Bit#(1)) qspi0_interrupt <-mkSyncBitToCC(slow_clock,slow_reset); `endif
 214                                 `ifdef UART0 SyncBitIfc#(Bit#(1)) uart0_interrupt <-mkSyncBitToCC(uart_clock,uart_reset); `endif
 215                                 rule synchronize_i2c_interrupts;
 216                                         `ifdef I2C1 i2c1_interrupt.send(slow_peripherals.i2c1_isint); `endif
 217                                         `ifdef I2C0 i2c0_interrupt.send(slow_peripherals.i2c0_isint); `endif
 218                                 endrule
 219                                 rule synchronize_qspi_interrupts;
 220                                         `ifdef QSPI0 qspi0_interrupt.send(slow_peripherals.qspi0_isint); `endif
 221                                         `ifdef QSPI1 qspi1_interrupt.send(slow_peripherals.qspi1_isint); `endif
 222                                 endrule
 223                                 rule synchronize_uart0_interrupt;
 224                                         `ifdef UART0 uart0_interrupt.send(slow_peripherals.uart0_intr); `endif
 225                                 endrule
 226                                 rule rl_connect_interrupt_to_DMA;
 227                                         Bit#(12) lv_interrupt_to_DMA= {{'d-1,
 228                                                                                                                         `ifdef I2C1 i2c1_interrupt.read `else 1'b1 `endif ,
 229                                                                                                                         `ifdef I2C0 i2c0_interrupt.read `else 1'b1 `endif ,
 230                                                                                                                         `ifdef QSPI1 qspi1_interrupt.read `else 1'b1 `endif ,
 231                                                                                                                         1'b1,
 232                                                                                                                         `ifdef QSPI0 qspi0_interrupt.read `else 1'b1 `endif ,
 233                                                                                                                         1'b1,1'b0,
 234                                                                                                                         `ifdef UART0 uart0_interrupt.read `else 1'b1 `endif }};
 235                                         dma.interrupt_from_peripherals(lv_interrupt_to_DMA);
 236                                 endrule
 237                         `endif
 238
 239
 240                 /*======= Synchornization between the JTAG and the Debug Module ========= */
 241                 `ifdef Debug
 242                         SyncFIFOIfc#(Bit#(40)) sync_request_to_dm <-mkSyncFIFOToCC(1,tck,trst);
 243                         SyncFIFOIfc#(Bit#(34)) sync_response_from_dm <-mkSyncFIFOFromCC(1,tck);
 244                         rule connect_tap_request_to_syncfifo;
 245                                 let x<-tap.request_to_dm;
 246                                 sync_request_to_dm.enq(x);
 247                         endrule
 248                         rule read_synced_request_to_dm;
 249                                 sync_request_to_dm.deq;
 250                                 core.request_from_dtm(sync_request_to_dm.first);
 251                         endrule
 252
 253                         rule connect_debug_response_to_syncfifo;
 254                                 let x<-core.response_to_dtm;
 255                                 sync_response_from_dm.enq(x);
 256                         endrule
 257                         rule read_synced_response_from_dm;
 258                                 sync_response_from_dm.deq;
 259                                 tap.response_from_dm(sync_response_from_dm.first);
 260                         endrule
 261                 `endif
 262                 /*======================================================================= */
 263
 264         `ifdef FlexBus
 265             //rule drive_flexbus_inputs;
 266                //flexbus.flexbus_side.m_TAn(1'b1);
 267                //flexbus.flexbus_side.m_din(32'haaaaaaaa);
 268             //endrule
 269          `endif
 270
 271                 `ifdef CLINT
 272                         SyncBitIfc#(Bit#(1)) clint_mtip_int <-mkSyncBitToCC(slow_clock,slow_reset);
 273                         SyncBitIfc#(Bit#(1)) clint_msip_int <-mkSyncBitToCC(slow_clock,slow_reset);
 274                         Reg#(Bit#(`Reg_width)) clint_mtime_value <-mkSyncRegToCC(0,slow_clock,slow_reset);
 275                         rule synchronize_clint_data;
 276                                 clint_mtip_int.send(slow_peripherals.mtip_int);
 277                                 clint_msip_int.send(slow_peripherals.msip_int);
 278                                 clint_mtime_value<=slow_peripherals.mtime;
 279                         endrule
 280                         rule connect_msip_mtip_from_clint;
 281                                 core.clint_msip(clint_msip_int.read);
 282                                 core.clint_mtip(clint_mtip_int.read);
 283             core.clint_mtime(clint_mtime_value);
 284                         endrule
 285                 `endif
 286                 `ifdef PLIC
 287                         Reg#(Tuple2#(Bool,Bool)) plic_interrupt_note <-mkSyncRegToCC(tuple2(False,False),slow_clock,slow_reset);
 288                         rule synchronize_interrupts;
 289                                 let note <- slow_peripherals.intrpt_note;
 290                                 plic_interrupt_note<=note;
 291                         endrule
 292          rule rl_send_external_interrupt_to_csr;
 293                                 core.set_external_interrupt(plic_interrupt_note);
 294                         endrule
 295                 `endif
 296
 297                 `ifdef VME
 298                         interface  proc_ifc = vme.proc_ifc;
 299                         interface   proc_dbus = vme.proc_dbus;
 300                 `endif
 301                 `ifdef FlexBus
 302             interface flexbus_out = flexbus.flexbus_side;
 303                 `endif
 304       method Action boot_sequence(Bit#(1) bootseq) = core.boot_sequence(bootseq);
 305                 `ifdef SDRAM
 306                         interface sdram_out=sdram.ifc_sdram_out;
 307                 `endif
 308     `ifdef DDR
 309       interface master=fabric.v_to_slaves[fromInteger(valueOf(Sdram_slave_num))];
 310     `endif
 311                 `ifdef Debug
 312                         method Action tms_i(Bit#(1) tms);
 313                                 tap.tms_i(tms);
 314                         endmethod
 315                         method Action tdi_i(Bit#(1) tdi);
 316                                 tap.tdi_i(tdi);
 317                         endmethod
 318                         method Action bs_chain_i(Bit#(1) bs_chain);
 319                                 tap.bs_chain_i(bs_chain);
 320                         endmethod
 321                         method Bit#(1) shiftBscan2Edge=tap.shiftBscan2Edge;
 322                         method Bit#(1) selectJtagInput=tap.selectJtagInput;
 323                         method Bit#(1) selectJtagOutput=tap.selectJtagOutput;
 324                         method Bit#(1) updateBscan=tap.updateBscan;
 325                         method Bit#(1) bscan_in=tap.bscan_in;
 326             method Bit#(1) scan_shift_en=tap.scan_shift_en;
 327                         method Bit#(1) tdo=tap.tdo;
 328                         method Bit#(1) tdo_oe=tap.tdo_oe;
 329                 `endif
 330                 interface slow_ios=slow_peripherals.slow_ios;
 331
 332         endmodule
 333 endpackage