src/bsv/bsv_lib/soc_template.bsv

   1 /*
   2 Copyright (c) 2013, IIT Madras
   3 All rights reserved.
   4
   5 Redistribution and use in source and binary forms, with or without
   6 modification, are permitted provided that the following conditions
   7 are met:
   8
   9 *  Redistributions of source code must retain the above copyright notice,
  10    this list of conditions and the following disclaimer.
  11 *  Redistributions in binary form must reproduce the above copyright
  12    notice, this list of conditions and the following disclaimer in the
  13    documentation and/or other materials provided with the distribution.
  14 *  Neither the name of IIT Madras  nor the names of its contributors
  15    may be used to endorse or promote products derived from this software
  16    without specific prior written permission.
  17
  18 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  19 "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  20 LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  21 A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  22 HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  23 SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
  24 TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
  25 PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
  26 LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
  27 NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  28 SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  29 -------------------------------------------------------------------
  30 */
  31 package Soc;
  32     /*====== Package imports === */
  33     import FIFO::*;
  34     import FIFOF::*;
  35     import SpecialFIFOs::*;
  36     import GetPut::*;
  37     import ClientServer::*;
  38     import Vector::*;
  39     import Connectable::*;
  40     import Clocks::*;
  41     /*========================== */
  42     /*=== Project imports === */
  43     import ConcatReg::*;
  44     import AXI4_Types::*;
  45     import AXI4_Fabric::*;
  46     import defined_types::*;
  47     import MemoryMap             :: *;
  48     import slow_peripherals::*;
  49     `include "defines.bsv"
  50     `include "instance_defines.bsv"
  51 {8}
  52     /*====== AXI4 slave declarations =======*/
  53 {3}
  54     /*====== AXI4 Master declarations =======*/
  55 {4}
  56
  57
  58     `ifdef DMA
  59         import DMA                               :: *;
  60     `endif
  61     `ifdef BOOTROM
  62         import BootRom                  ::*;
  63     `endif
  64     `ifdef SDRAM
  65         import sdr_top                   :: *;
  66     `endif
  67     `ifdef BRAM
  68         import Memory_AXI4      ::*;
  69     `endif
  70     `ifdef TCMemory
  71         import TCM::*;
  72     `endif
  73     `ifdef Debug
  74         import jtagdtm::*;
  75         import DebugModule::*;
  76     `else
  77         import core::*;
  78     `endif
  79     `ifdef  VME
  80         import vme_top ::*;
  81     `endif
  82
  83     `ifdef VME
  84         import vme_master::*;
  85     `endif
  86     `ifdef FlexBus
  87         import FlexBus_Types::*;
  88     `endif
  89 {0}
  90
  91     /*========================= */
  92     interface Ifc_Soc;
  93         interface SP_ios slow_ios;
  94         (*always_ready,always_enabled*)
  95         method Action boot_sequence(Bit#(1) bootseq);
  96
  97         `ifdef SDRAM
  98             (*always_ready*) interface Ifc_sdram_out sdram_out;
  99         `endif
 100         ifdef DDR
 101             (*prefix="M_AXI"*) interface
 102                    AXI4_Master_IFC#(`PADDR, `Reg_width, `USERSPACE) master;
 103         `endif
 104         `ifdef HYPER
 105              (*always_ready,always_enabled*)
 106              interface Ifc_flash ifc_flash;
 107         `endif
 108         /*=============================================== */
 109         `ifdef VME
 110              interface Vme_out  proc_ifc;
 111              interface Data_bus_inf proc_dbus;
 112         `endif
 113         `ifdef FlexBus
 114              interface FlexBus_Master_IFC flexbus_out;
 115         `endif
 116 {1}
 117     endinterface
 118
 119     (*synthesize*)
 120     module mkSoc #(Bit#(`VADDR) reset_vector,
 121                  Clock slow_clock, Reset slow_reset, Clock uart_clock,
 122                  Reset uart_reset, Clock clk0, Clock tck, Reset trst
 123                  `ifdef PWM_AXI4Lite ,Clock ext_pwm_clock `endif )(Ifc_Soc);
 124         Clock core_clock <-exposeCurrentClock; // slow peripheral clock
 125         Reset core_reset <-exposeCurrentReset; // slow peripheral reset
 126 {2}
 127         `ifdef Debug
 128             Ifc_DebugModule core<-mkDebugModule(reset_vector);
 129         `else
 130             Ifc_core_AXI4 core <-mkcore_AXI4(reset_vector);
 131         `endif
 132         `ifdef BOOTROM
 133             BootRom_IFC bootrom <-mkBootRom;
 134         `endif
 135         `ifdef SDRAM
 136             Ifc_sdr_slave sdram<- mksdr_axi4_slave(clk0);
 137         `endif
 138         `ifdef BRAM
 139             Memory_IFC#(`SDRAMMemBase,`Addr_space)main_memory <-
 140                         mkMemory("code.mem.MSB","code.mem.LSB","MainMEM");
 141         `endif
 142         `ifdef TCMemory
 143             Ifc_TCM                                     tcm                             <- mkTCM;
 144         `endif
 145         `ifdef DMA
 146             DmaC#(7,`NUM_DMACHANNELS) dma       <- mkDMA();
 147         `endif
 148             `ifdef VME
 149             Ifc_vme_top             vme             <-mkvme_top();
 150             `endif
 151         `ifdef FlexBus
 152             AXI4_Slave_to_FlexBus_Master_Xactor_IFC #(32, 64,0)
 153                             flexbus <- mkAXI4_Slave_to_FlexBus_Master_Xactor;
 154         `endif
 155         Ifc_slow_peripherals slow_peripherals <-mkslow_peripherals(
 156                           core_clock, core_reset, uart_clock,
 157                           uart_reset, clocked_by slow_clock ,
 158                           reset_by slow_reset
 159                           `ifdef PWM_AXI4Lite , ext_pwm_clock `endif );
 160
 161         // Fabric
 162         AXI4_Fabric_IFC #(Num_Masters, Num_Slaves,
 163                           `PADDR, `Reg_width,`USERSPACE)
 164                         fabric <- mkAXI4_Fabric(fn_addr_to_slave_num);
 165
 166         // Connect traffic generators to fabric
 167         mkConnection (core.dmem_master,fabric.v_from_masters
 168                               [fromInteger(valueOf(Dmem_master_num))]);
 169         mkConnection (core.imem_master, fabric.v_from_masters
 170                               [fromInteger(valueOf(Imem_master_num))]);
 171         `ifdef Debug
 172             mkConnection (core.debug_master, fabric.v_from_masters
 173                               [fromInteger(valueOf(Debug_master_num))]);
 174         `endif
 175         `ifdef DMA
 176          mkConnection (dma.mmu, fabric.v_from_masters
 177                               [fromInteger(valueOf(DMA_master_num))]);
 178         `endif
 179
 180
 181         // Connect fabric to memory slaves
 182             `ifdef Debug
 183                 mkConnection (fabric.v_to_slaves
 184                               [fromInteger(valueOf(Debug_slave_num))],
 185                               core.debug_slave);
 186             `endif
 187             `ifdef SDRAM
 188                 mkConnection (fabric.v_to_slaves
 189                               [fromInteger(valueOf(Sdram_slave_num))],
 190                               sdram.axi4_slave_sdram); //
 191             mkConnection (fabric.v_to_slaves
 192                               [fromInteger(valueOf(Sdram_cfg_slave_num))],
 193                               sdram.axi4_slave_cntrl_reg); //
 194       `endif
 195       `ifdef BRAM
 196                 mkConnection(fabric.v_to_slaves
 197                               [fromInteger(valueOf(Sdram_slave_num))],
 198                               main_memory.axi_slave);
 199             `endif
 200             `ifdef BOOTROM
 201                 mkConnection (fabric.v_to_slaves
 202                               [fromInteger(valueOf(BootRom_slave_num))],
 203                               bootrom.axi_slave);
 204             `endif
 205             `ifdef DMA
 206             mkConnection (fabric.v_to_slaves
 207                               [fromInteger(valueOf(Dma_slave_num))],
 208                               dma.cfg); //DMA slave
 209             `endif
 210             `ifdef TCMemory
 211                 mkConnection (fabric.v_to_slaves
 212                               [fromInteger(valueOf(TCM_slave_num))],
 213                               tcm.axi_slave);
 214             `endif
 215             mkConnection(fabric.v_to_slaves
 216                               [fromInteger(valueOf(SlowPeripheral_slave_num))],
 217                               slow_peripherals.axi_slave);
 218             `ifdef VME
 219                 mkConnection (fabric.v_to_slaves
 220                               [fromInteger(valueOf(VME_slave_num))],
 221                               vme.slave_axi_vme);
 222             `endif
 223             `ifdef FlexBus
 224                 mkConnection (fabric.v_to_slaves
 225                               [fromInteger(valueOf(FlexBus_slave_num))],
 226                               flexbus.axi_side);
 227             `endif
 228
 229             // fabric connections
 230 {5}
 231
 232             `ifdef DMA
 233             // rule to connect all interrupt lines to the DMA
 234             // All the interrupt lines to DMA are active
 235             // HIGH. For peripherals that are not connected,
 236             // or those which do not
 237             // generate an interrupt (like TCM), drive a constant 1
 238             // on the corresponding interrupt line.
 239 {7}
 240             `endif
 241
 242
 243         /*==== Synchornization between the JTAG and the Debug Module ===== */
 244         `ifdef Debug
 245             SyncFIFOIfc#(Bit#(40)) sync_request_to_dm <-
 246                                         mkSyncFIFOToCC(1,tck,trst);
 247             SyncFIFOIfc#(Bit#(34)) sync_response_from_dm <-
 248                                         mkSyncFIFOFromCC(1,tck);
 249             rule connect_tap_request_to_syncfifo;
 250                 let x<-tap.request_to_dm;
 251                 sync_request_to_dm.enq(x);
 252             endrule
 253             rule read_synced_request_to_dm;
 254                 sync_request_to_dm.deq;
 255                 core.request_from_dtm(sync_request_to_dm.first);
 256             endrule
 257
 258             rule connect_debug_response_to_syncfifo;
 259                 let x<-core.response_to_dtm;
 260                 sync_response_from_dm.enq(x);
 261             endrule
 262             rule read_synced_response_from_dm;
 263                 sync_response_from_dm.deq;
 264                 tap.response_from_dm(sync_response_from_dm.first);
 265             endrule
 266         `endif
 267         /*============================================================ */
 268
 269         `ifdef FlexBus
 270             //rule drive_flexbus_inputs;
 271                //flexbus.flexbus_side.m_TAn(1'b1);
 272                //flexbus.flexbus_side.m_din(32'haaaaaaaa);
 273             //endrule
 274          `endif
 275
 276         `ifdef CLINT
 277             SyncBitIfc#(Bit#(1)) clint_mtip_int <-
 278                                         mkSyncBitToCC(slow_clock,slow_reset);
 279             SyncBitIfc#(Bit#(1)) clint_msip_int <-
 280                                         mkSyncBitToCC(slow_clock,slow_reset);
 281             Reg#(Bit#(`Reg_width)) clint_mtime_value <-
 282                                         mkSyncRegToCC(0,slow_clock,slow_reset);
 283             rule synchronize_clint_data;
 284                 clint_mtip_int.send(slow_peripherals.mtip_int);
 285                 clint_msip_int.send(slow_peripherals.msip_int);
 286                 clint_mtime_value<=slow_peripherals.mtime;
 287             endrule
 288             rule connect_msip_mtip_from_clint;
 289                 core.clint_msip(clint_msip_int.read);
 290                 core.clint_mtip(clint_mtip_int.read);
 291             core.clint_mtime(clint_mtime_value);
 292             endrule
 293         `endif
 294         `ifdef PLIC
 295             Reg#(Tuple2#(Bool,Bool)) plic_interrupt_note <-
 296                                         mkSyncRegToCC(tuple2(False,False),
 297                                                       slow_clock,slow_reset);
 298             rule synchronize_interrupts;
 299                 let note <- slow_peripherals.intrpt_note;
 300                 plic_interrupt_note<=note;
 301             endrule
 302             rule rl_send_external_interrupt_to_csr;
 303                 core.set_external_interrupt(plic_interrupt_note);
 304             endrule
 305         `endif
 306
 307         `ifdef VME
 308             interface  proc_ifc = vme.proc_ifc;
 309             interface   proc_dbus = vme.proc_dbus;
 310         `endif
 311         `ifdef FlexBus
 312             interface flexbus_out = flexbus.flexbus_side;
 313         `endif
 314          method Action boot_sequence(Bit#(1) bootseq) =
 315                             core.boot_sequence(bootseq);
 316         `ifdef SDRAM
 317             interface sdram_out=sdram.ifc_sdram_out;
 318         `endif
 319         `ifdef DDR
 320           interface master=fabric.v_to_slaves
 321                                 [fromInteger(valueOf(Sdram_slave_num))];
 322         `endif
 323         interface slow_ios=slow_peripherals.slow_ios;
 324 {6}
 325     endmodule
 326 endpackage