src/bsv/bsv_lib/soc_template.bsv

   1 /*
   2 Copyright (c) 2013, IIT Madras
   3 All rights reserved.
   4
   5 Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
   6
   7 *  Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
   8 *  Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
   9 *  Neither the name of IIT Madras  nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.
  10
  11 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  12 ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
  13 */
  14 package Soc;
  15         /*====== Package imports === */
  16         import FIFO::*;
  17         import FIFOF::*;
  18         import SpecialFIFOs::*;
  19         import GetPut::*;
  20         import ClientServer::*;
  21         import Vector::*;
  22         import Connectable::*;
  23         import Clocks::*;
  24         /*========================== */
  25         /*=== Project imports === */
  26         import ConcatReg::*;
  27         import AXI4_Types::*;
  28         import AXI4_Fabric::*;
  29         import defined_types::*;
  30         import MemoryMap                 :: *;
  31         import slow_peripherals::*;
  32         `include "defines.bsv"
  33         `include "instance_defines.bsv"
  34     /*====== AXI4 slave declarations =======*/
  35 {3}
  36     /*====== AXI4 Master declarations =======*/
  37 {4}
  38
  39
  40                 `ifdef DMA
  41                         import DMA                               :: *;
  42                 `endif
  43                 `ifdef BOOTROM
  44                         import BootRom                  ::*;
  45                 `endif
  46                 `ifdef SDRAM
  47                         import sdr_top                   :: *;
  48     `endif
  49                 `ifdef BRAM
  50                         import Memory_AXI4      ::*;
  51                 `endif
  52                 `ifdef TCMemory
  53                         import TCM::*;
  54                 `endif
  55                 `ifdef Debug
  56                         import jtagdtm::*;
  57                         import DebugModule::*;
  58                 `else
  59                         import core::*;
  60                 `endif
  61 `ifdef  VME
  62                         import vme_top ::*;
  63 `endif
  64
  65 `ifdef VME
  66                         import vme_master::*;
  67 `endif
  68 `ifdef FlexBus
  69             import FlexBus_Types::*;
  70 `endif
  71 {0}
  72
  73         /*========================= */
  74         interface Ifc_Soc;
  75                 interface SP_ios slow_ios;
  76                 (*always_ready,always_enabled*)
  77                 method Action boot_sequence(Bit#(1) bootseq);
  78
  79                   `ifdef SDRAM
  80                         (*always_ready*) interface Ifc_sdram_out sdram_out;
  81                 `endif
  82       `ifdef DDR
  83         (*prefix="M_AXI"*) interface AXI4_Master_IFC#(`PADDR, `Reg_width, `USERSPACE) master;
  84       `endif
  85       `ifdef Debug
  86                         (*always_ready,always_enabled*)
  87                         method Action tms_i(Bit#(1) tms);
  88                         (*always_ready,always_enabled*)
  89                         method Action tdi_i(Bit#(1) tdi);
  90                         (*always_ready,always_enabled*)
  91                         method Action bs_chain_i(Bit#(1) bs_chain);
  92                         (*always_ready,always_enabled*)
  93                         method Bit#(1) shiftBscan2Edge;
  94                         (*always_ready,always_enabled*)
  95                         method Bit#(1) selectJtagInput;
  96                         (*always_ready,always_enabled*)
  97                         method Bit#(1) selectJtagOutput;
  98                         (*always_ready,always_enabled*)
  99                         method Bit#(1) updateBscan;
 100                         (*always_ready,always_enabled*)
 101                         method Bit#(1) bscan_in;
 102                         (*always_ready,always_enabled*)
 103                         method Bit#(1) scan_shift_en;
 104                         (*always_ready,always_enabled*)
 105                         method Bit#(1) tdo;
 106                         (*always_ready,always_enabled*)
 107                         method Bit#(1) tdo_oe;
 108                 `endif
 109                 `ifdef HYPER
 110                         (*always_ready,always_enabled*)
 111                    interface Ifc_flash ifc_flash;
 112                 `endif
 113         /*=============================================== */
 114            `ifdef VME
 115                         interface Vme_out  proc_ifc;
 116                         interface Data_bus_inf proc_dbus;
 117                 `endif
 118         `ifdef FlexBus
 119             interface FlexBus_Master_IFC flexbus_out;
 120         `endif
 121 {1}
 122         endinterface
 123         (*synthesize*)
 124         module mkSoc #(Bit#(`VADDR) reset_vector, Clock slow_clock, Reset slow_reset, Clock uart_clock,
 125                  Reset uart_reset, Clock clk0, Clock tck, Reset trst
 126                  `ifdef PWM_AXI4Lite ,Clock ext_pwm_clock `endif )(Ifc_Soc);
 127                 Clock core_clock <-exposeCurrentClock; // slow peripheral clock
 128                 Reset core_reset <-exposeCurrentReset; // slow peripheral reset
 129 {2}
 130       `ifdef Debug
 131                         Ifc_DebugModule core<-mkDebugModule(reset_vector);
 132                 `else
 133                         Ifc_core_AXI4 core <-mkcore_AXI4(reset_vector);
 134                 `endif
 135                 `ifdef BOOTROM
 136                         BootRom_IFC bootrom <-mkBootRom;
 137                 `endif
 138                 `ifdef SDRAM
 139                         Ifc_sdr_slave                   sdram                           <- mksdr_axi4_slave(clk0);
 140                 `endif
 141     `ifdef BRAM
 142                         Memory_IFC#(`SDRAMMemBase,`Addr_space) main_memory <- mkMemory("code.mem.MSB","code.mem.LSB","MainMEM");
 143                 `endif
 144                 `ifdef TCMemory
 145                         Ifc_TCM                                 tcm                             <- mkTCM;
 146                 `endif
 147                 `ifdef DMA
 148                         DmaC#(7,12)                             dma                             <- mkDMA();
 149                 `endif
 150                         `ifdef VME
 151                         Ifc_vme_top             vme             <-mkvme_top();
 152                         `endif
 153         `ifdef FlexBus
 154             AXI4_Slave_to_FlexBus_Master_Xactor_IFC #(32, 64,0)
 155                                             flexbus <- mkAXI4_Slave_to_FlexBus_Master_Xactor;
 156         `endif
 157                 Ifc_slow_peripherals slow_peripherals <-mkslow_peripherals(core_clock, core_reset, uart_clock,
 158           uart_reset, clocked_by slow_clock , reset_by slow_reset
 159           `ifdef PWM_AXI4Lite , ext_pwm_clock `endif );
 160
 161         // Fabric
 162         AXI4_Fabric_IFC #(Num_Masters, Num_Slaves, `PADDR, `Reg_width,`USERSPACE)
 163                                 fabric <- mkAXI4_Fabric(fn_addr_to_slave_num);
 164
 165         // Connect traffic generators to fabric
 166         mkConnection (core.dmem_master, fabric.v_from_masters [fromInteger(valueOf(Dmem_master_num))]);
 167         mkConnection (core.imem_master, fabric.v_from_masters [fromInteger(valueOf(Imem_master_num))]);
 168                 `ifdef Debug
 169                         mkConnection (core.debug_master, fabric.v_from_masters [fromInteger(valueOf(Debug_master_num))]);
 170                 `endif
 171                 `ifdef DMA
 172          mkConnection (dma.mmu, fabric.v_from_masters[fromInteger(valueOf(DMA_master_num))]);
 173                 `endif
 174
 175
 176                 // Connect fabric to memory slaves
 177                         `ifdef Debug
 178                                 mkConnection (fabric.v_to_slaves [fromInteger(valueOf(Debug_slave_num))],core.debug_slave);
 179                         `endif
 180                         `ifdef SDRAM
 181                                 mkConnection (fabric.v_to_slaves [fromInteger(valueOf(Sdram_slave_num))],       sdram.axi4_slave_sdram); //
 182                         mkConnection (fabric.v_to_slaves [fromInteger(valueOf(Sdram_cfg_slave_num))],   sdram.axi4_slave_cntrl_reg); //
 183       `endif
 184       `ifdef BRAM
 185                                 mkConnection(fabric.v_to_slaves[fromInteger(valueOf(Sdram_slave_num))],main_memory.axi_slave);
 186                         `endif
 187                         `ifdef BOOTROM
 188                                 mkConnection (fabric.v_to_slaves [fromInteger(valueOf(BootRom_slave_num))],bootrom.axi_slave);
 189                         `endif
 190                         `ifdef DMA
 191                         mkConnection (fabric.v_to_slaves [fromInteger(valueOf(Dma_slave_num))], dma.cfg); //DMA slave
 192                         `endif
 193                         `ifdef TCMemory
 194                                 mkConnection (fabric.v_to_slaves [fromInteger(valueOf(TCM_slave_num))],tcm.axi_slave);
 195                         `endif
 196                         mkConnection(fabric.v_to_slaves [fromInteger(valueOf(SlowPeripheral_slave_num))],slow_peripherals.axi_slave);
 197                         `ifdef VME
 198                                 mkConnection (fabric.v_to_slaves[fromInteger(valueOf(VME_slave_num))],vme.slave_axi_vme);
 199                         `endif
 200                         `ifdef FlexBus
 201                                 mkConnection (fabric.v_to_slaves[fromInteger(valueOf(FlexBus_slave_num))],flexbus.axi_side);
 202                         `endif
 203                         `ifdef DMA
 204                         //rule to connect all interrupt lines to the DMA
 205                         //All the interrupt lines to DMA are active HIGH. For peripherals that are not connected, or those which do not
 206                         //generate an interrupt (like TCM), drive a constant 1 on the corresponding interrupt line.
 207                                 `ifdef I2C1 SyncBitIfc#(Bit#(1)) i2c1_interrupt <-mkSyncBitToCC(slow_clock,slow_reset); `endif
 208                                 `ifdef I2C0 SyncBitIfc#(Bit#(1)) i2c0_interrupt <-mkSyncBitToCC(slow_clock,slow_reset); `endif
 209                                 `ifdef QSPI1 SyncBitIfc#(Bit#(1)) qspi1_interrupt <-mkSyncBitToCC(slow_clock,slow_reset); `endif
 210                                 `ifdef QSPI0 SyncBitIfc#(Bit#(1)) qspi0_interrupt <-mkSyncBitToCC(slow_clock,slow_reset); `endif
 211                                 `ifdef UART0 SyncBitIfc#(Bit#(1)) uart0_interrupt <-mkSyncBitToCC(uart_clock,uart_reset); `endif
 212                                 rule synchronize_i2c_interrupts;
 213                                         `ifdef I2C1 i2c1_interrupt.send(slow_peripherals.i2c1_isint); `endif
 214                                         `ifdef I2C0 i2c0_interrupt.send(slow_peripherals.i2c0_isint); `endif
 215                                 endrule
 216                                 rule synchronize_qspi_interrupts;
 217                                         `ifdef QSPI0 qspi0_interrupt.send(slow_peripherals.qspi0_isint); `endif
 218                                         `ifdef QSPI1 qspi1_interrupt.send(slow_peripherals.qspi1_isint); `endif
 219                                 endrule
 220                                 rule synchronize_uart0_interrupt;
 221                                         `ifdef UART0 uart0_interrupt.send(slow_peripherals.uart0_intr); `endif
 222                                 endrule
 223                                 rule rl_connect_interrupt_to_DMA;
 224                                         Bit#(12) lv_interrupt_to_DMA= {{'d-1,
 225                                                                                                                         `ifdef I2C1 i2c1_interrupt.read `else 1'b1 `endif ,
 226                                                                                                                         `ifdef I2C0 i2c0_interrupt.read `else 1'b1 `endif ,
 227                                                                                                                         `ifdef QSPI1 qspi1_interrupt.read `else 1'b1 `endif ,
 228                                                                                                                         1'b1,
 229                                                                                                                         `ifdef QSPI0 qspi0_interrupt.read `else 1'b1 `endif ,
 230                                                                                                                         1'b1,1'b0,
 231                                                                                                                         `ifdef UART0 uart0_interrupt.read `else 1'b1 `endif }};
 232                                         dma.interrupt_from_peripherals(lv_interrupt_to_DMA);
 233                                 endrule
 234                         `endif
 235
 236
 237                 /*======= Synchornization between the JTAG and the Debug Module ========= */
 238                 `ifdef Debug
 239                         SyncFIFOIfc#(Bit#(40)) sync_request_to_dm <-mkSyncFIFOToCC(1,tck,trst);
 240                         SyncFIFOIfc#(Bit#(34)) sync_response_from_dm <-mkSyncFIFOFromCC(1,tck);
 241                         rule connect_tap_request_to_syncfifo;
 242                                 let x<-tap.request_to_dm;
 243                                 sync_request_to_dm.enq(x);
 244                         endrule
 245                         rule read_synced_request_to_dm;
 246                                 sync_request_to_dm.deq;
 247                                 core.request_from_dtm(sync_request_to_dm.first);
 248                         endrule
 249
 250                         rule connect_debug_response_to_syncfifo;
 251                                 let x<-core.response_to_dtm;
 252                                 sync_response_from_dm.enq(x);
 253                         endrule
 254                         rule read_synced_response_from_dm;
 255                                 sync_response_from_dm.deq;
 256                                 tap.response_from_dm(sync_response_from_dm.first);
 257                         endrule
 258                 `endif
 259                 /*======================================================================= */
 260
 261         `ifdef FlexBus
 262             //rule drive_flexbus_inputs;
 263                //flexbus.flexbus_side.m_TAn(1'b1);
 264                //flexbus.flexbus_side.m_din(32'haaaaaaaa);
 265             //endrule
 266          `endif
 267
 268                 `ifdef CLINT
 269                         SyncBitIfc#(Bit#(1)) clint_mtip_int <-mkSyncBitToCC(slow_clock,slow_reset);
 270                         SyncBitIfc#(Bit#(1)) clint_msip_int <-mkSyncBitToCC(slow_clock,slow_reset);
 271                         Reg#(Bit#(`Reg_width)) clint_mtime_value <-mkSyncRegToCC(0,slow_clock,slow_reset);
 272                         rule synchronize_clint_data;
 273                                 clint_mtip_int.send(slow_peripherals.mtip_int);
 274                                 clint_msip_int.send(slow_peripherals.msip_int);
 275                                 clint_mtime_value<=slow_peripherals.mtime;
 276                         endrule
 277                         rule connect_msip_mtip_from_clint;
 278                                 core.clint_msip(clint_msip_int.read);
 279                                 core.clint_mtip(clint_mtip_int.read);
 280             core.clint_mtime(clint_mtime_value);
 281                         endrule
 282                 `endif
 283                 `ifdef PLIC
 284                         Reg#(Tuple2#(Bool,Bool)) plic_interrupt_note <-mkSyncRegToCC(tuple2(False,False),slow_clock,slow_reset);
 285                         rule synchronize_interrupts;
 286                                 let note <- slow_peripherals.intrpt_note;
 287                                 plic_interrupt_note<=note;
 288                         endrule
 289          rule rl_send_external_interrupt_to_csr;
 290                                 core.set_external_interrupt(plic_interrupt_note);
 291                         endrule
 292                 `endif
 293
 294                 `ifdef VME
 295                         interface  proc_ifc = vme.proc_ifc;
 296                         interface   proc_dbus = vme.proc_dbus;
 297                 `endif
 298                 `ifdef FlexBus
 299             interface flexbus_out = flexbus.flexbus_side;
 300                 `endif
 301       method Action boot_sequence(Bit#(1) bootseq) = core.boot_sequence(bootseq);
 302                 `ifdef SDRAM
 303                         interface sdram_out=sdram.ifc_sdram_out;
 304                 `endif
 305     `ifdef DDR
 306       interface master=fabric.v_to_slaves[fromInteger(valueOf(Sdram_slave_num))];
 307     `endif
 308                 `ifdef Debug
 309                         method Action tms_i(Bit#(1) tms);
 310                                 tap.tms_i(tms);
 311                         endmethod
 312                         method Action tdi_i(Bit#(1) tdi);
 313                                 tap.tdi_i(tdi);
 314                         endmethod
 315                         method Action bs_chain_i(Bit#(1) bs_chain);
 316                                 tap.bs_chain_i(bs_chain);
 317                         endmethod
 318                         method Bit#(1) shiftBscan2Edge=tap.shiftBscan2Edge;
 319                         method Bit#(1) selectJtagInput=tap.selectJtagInput;
 320                         method Bit#(1) selectJtagOutput=tap.selectJtagOutput;
 321                         method Bit#(1) updateBscan=tap.updateBscan;
 322                         method Bit#(1) bscan_in=tap.bscan_in;
 323             method Bit#(1) scan_shift_en=tap.scan_shift_en;
 324                         method Bit#(1) tdo=tap.tdo;
 325                         method Bit#(1) tdo_oe=tap.tdo_oe;
 326                 `endif
 327                 interface slow_ios=slow_peripherals.slow_ios;
 328
 329         endmodule
 330 endpackage