2 Copyright (c) 2013, IIT Madras
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16 without specific prior written permission.
18 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
19 "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
20 LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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24 TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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27 NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
28 SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 -------------------------------------------------------------------
32 /*====== Package imports === */
35 import SpecialFIFOs::*;
37 import ClientServer::*;
39 import Connectable::*;
42 /*=== Project imports === */
46 import AXI4_Fabric::*;
47 import defined_types::*;
48 import MemoryMap :: *;
49 import slow_peripherals::*;
50 import fast_memory_map::*;
51 import slow_memory_map::*;
53 `include "defines.bsv"
55 `include "instance_defines.bsv"
56 `include "core_parameters.bsv"
69 import Memory_AXI4 ::*;
75 import DebugModule::*;
87 import FlexBus_Types::*;
91 /*========================= */
93 interface SP_dedicated_ios slow_ios;
94 interface IOCellSide iocell_side;
95 (*always_ready,always_enabled*)
96 method Action boot_sequence(Bit#(1) bootseq);
99 (*always_ready*) interface Ifc_sdram_out sdram_out;
102 (*prefix="M_AXI"*) interface
103 AXI4_Master_IFC#(`PADDR, `DATA, `USERSPACE) master;
106 (*always_ready,always_enabled*)
107 interface Ifc_flash ifc_flash;
109 /*=============================================== */
111 interface Vme_out proc_ifc;
112 interface Data_bus_inf proc_dbus;
117 //============ mkSoc module =================
120 module mkSoc #(Bit#(`VADDR) reset_vector,
121 Clock slow_clock, Reset slow_reset, Clock uart_clock,
122 Reset uart_reset, Clock clk0, Clock tck, Reset trst
123 `ifdef PWM_AXI4Lite ,Clock ext_pwm_clock `endif )(Ifc_Soc);
124 Clock core_clock <-exposeCurrentClock; // slow peripheral clock
125 Reset core_reset <-exposeCurrentReset; // slow peripheral reset
128 Ifc_DebugModule core<-mkDebugModule(reset_vector);
130 Ifc_core_AXI4 core <-mkcore_AXI4(reset_vector);
133 BootRom_IFC bootrom <-mkBootRom;
136 Ifc_sdr_slave sdram<- mksdr_axi4_slave(clk0);
139 Memory_IFC#(`SDRAMMemBase,`Addr_space)main_memory <-
140 mkMemory("code.mem.MSB","code.mem.LSB","MainMEM");
143 Ifc_TCM tcm <- mkTCM;
146 DmaC#(7,`NUM_DMACHANNELS) dma <- mkDMA();
149 Ifc_vme_top vme <-mkvme_top();
151 Ifc_slow_peripherals slow_peripherals <-mkslow_peripherals(
152 core_clock, core_reset,
153 uart_clock, uart_reset,
154 clocked_by slow_clock, reset_by slow_reset
155 `ifdef PWM_AXI4Lite , ext_pwm_clock `endif );
157 // clock sync mkConnections
161 AXI4_Fabric_IFC #(Num_Masters, Num_Fast_Slaves,
162 `PADDR, `DATA,`USERSPACE)
163 fabric <- mkAXI4_Fabric(fn_addr_to_slave_num);
165 // Connect traffic generators to fabric
166 mkConnection (core.dmem_master,fabric.v_from_masters
167 [fromInteger(valueOf(Dmem_master_num))]);
168 mkConnection (core.imem_master, fabric.v_from_masters
169 [fromInteger(valueOf(Imem_master_num))]);
171 mkConnection (core.debug_master, fabric.v_from_masters
172 [fromInteger(valueOf(Debug_master_num))]);
175 mkConnection (dma.mmu, fabric.v_from_masters
176 [fromInteger(valueOf(DMA_master_num))]);
181 // Connect fabric to memory slaves
183 mkConnection (fabric.v_to_slaves
184 [fromInteger(valueOf(Debug_slave_num))],
188 mkConnection (fabric.v_to_slaves
189 [fromInteger(valueOf(Sdram_slave_num))],
190 sdram.axi4_slave_sdram); //
191 mkConnection (fabric.v_to_slaves
192 [fromInteger(valueOf(Sdram_cfg_slave_num))],
193 sdram.axi4_slave_cntrl_reg); //
196 mkConnection(fabric.v_to_slaves
197 [fromInteger(valueOf(Sdram_slave_num))],
198 main_memory.axi_slave);
201 mkConnection (fabric.v_to_slaves
202 [fromInteger(valueOf(BootRom_slave_num))],
206 mkConnection (fabric.v_to_slaves
207 [fromInteger(valueOf(Dma_slave_num))],
208 dma.cfg); //DMA slave
211 mkConnection (fabric.v_to_slaves
212 [fromInteger(valueOf(TCM_slave_num))],
215 mkConnection(fabric.v_to_slaves
216 [fromInteger(valueOf(SlowPeripheral_slave_num))],
217 slow_peripherals.axi_slave);
219 mkConnection (fabric.v_to_slaves
220 [fromInteger(valueOf(VME_slave_num))],
227 // fabric connections
231 // rule to connect all interrupt lines to the DMA
232 // All the interrupt lines to DMA are active
233 // HIGH. For peripherals that are not connected,
234 // or those which do not
235 // generate an interrupt (like TCM), drive a constant 1
236 // on the corresponding interrupt line.
241 /*==== Synchornization between the JTAG and the Debug Module ===== */
243 SyncFIFOIfc#(Bit#(40)) sync_request_to_dm <-
244 mkSyncFIFOToCC(1,tck,trst);
245 SyncFIFOIfc#(Bit#(34)) sync_response_from_dm <-
246 mkSyncFIFOFromCC(1,tck);
247 rule connect_tap_request_to_syncfifo;
248 let x<-tap.request_to_dm;
249 sync_request_to_dm.enq(x);
251 rule read_synced_request_to_dm;
252 sync_request_to_dm.deq;
253 core.request_from_dtm(sync_request_to_dm.first);
256 rule connect_debug_response_to_syncfifo;
257 let x<-core.response_to_dtm;
258 sync_response_from_dm.enq(x);
260 rule read_synced_response_from_dm;
261 sync_response_from_dm.deq;
262 tap.response_from_dm(sync_response_from_dm.first);
265 /*============================================================ */
268 //rule drive_flexbus_inputs;
269 //flexbus.flexbus_side.m_TAn(1'b1);
270 //flexbus.flexbus_side.m_din(32'haaaaaaaa);
275 SyncBitIfc#(Bit#(1)) clint_mtip_int <-
276 mkSyncBitToCC(slow_clock,slow_reset);
277 SyncBitIfc#(Bit#(1)) clint_msip_int <-
278 mkSyncBitToCC(slow_clock,slow_reset);
279 Reg#(Bit#(`DATA)) clint_mtime_value <-
280 mkSyncRegToCC(0,slow_clock,slow_reset);
281 rule synchronize_clint_data;
282 clint_mtip_int.send(slow_peripherals.mtip_int);
283 clint_msip_int.send(slow_peripherals.msip_int);
284 clint_mtime_value<=slow_peripherals.mtime;
286 rule connect_msip_mtip_from_clint;
287 core.clint_msip(clint_msip_int.read);
288 core.clint_mtip(clint_mtip_int.read);
289 core.clint_mtime(clint_mtime_value);
293 Reg#(Tuple2#(Bool,Bool)) plic_interrupt_note <-
294 mkSyncRegToCC(tuple2(False,False),
295 slow_clock,slow_reset);
296 rule synchronize_interrupts;
297 let note <- slow_peripherals.intrpt_note;
298 plic_interrupt_note<=note;
300 rule rl_send_external_interrupt_to_csr;
301 core.set_external_interrupt(plic_interrupt_note);
306 interface proc_ifc = vme.proc_ifc;
307 interface proc_dbus = vme.proc_dbus;
309 method Action boot_sequence(Bit#(1) bootseq) =
310 core.boot_sequence(bootseq);
312 interface sdram_out=sdram.ifc_sdram_out;
315 interface master=fabric.v_to_slaves
316 [fromInteger(valueOf(Sdram_slave_num))];
318 interface slow_ios = slow_peripherals.slow_ios;
319 interface iocell_side = slow_peripherals.iocell_side;