src/bsv/bsv_lib/soc_template.bsv

   1 /*
   2 Copyright (c) 2013, IIT Madras
   3 All rights reserved.
   4
   5 Redistribution and use in source and binary forms, with or without
   6 modification, are permitted provided that the following conditions
   7 are met:
   8
   9 *  Redistributions of source code must retain the above copyright notice,
  10    this list of conditions and the following disclaimer.
  11 *  Redistributions in binary form must reproduce the above copyright
  12    notice, this list of conditions and the following disclaimer in the
  13    documentation and/or other materials provided with the distribution.
  14 *  Neither the name of IIT Madras  nor the names of its contributors
  15    may be used to endorse or promote products derived from this software
  16    without specific prior written permission.
  17
  18 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  19 "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  20 LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  21 A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  22 HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  23 SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
  24 TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
  25 PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
  26 LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
  27 NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  28 SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  29 -------------------------------------------------------------------
  30 */
  31 package Soc;
  32     /*====== Package imports === */
  33     import FIFO::*;
  34     import FIFOF::*;
  35     import SpecialFIFOs::*;
  36     import GetPut::*;
  37     import ClientServer::*;
  38     import Vector::*;
  39     import Connectable::*;
  40     import Clocks::*;
  41     /*========================== */
  42     /*=== Project imports === */
  43     import ConcatReg::*;
  44     import AXI4_Types::*;
  45     import AXI4_Fabric::*;
  46     import defined_types::*;
  47     import MemoryMap             :: *;
  48     import slow_peripherals::*;
  49     `include "defines.bsv"
  50     `include "instance_defines.bsv"
  51 {8}
  52     /*====== AXI4 slave declarations =======*/
  53 {3}
  54     /*====== AXI4 Master declarations =======*/
  55 {4}
  56
  57
  58         `ifdef DMA
  59             import DMA                           :: *;
  60         `endif
  61         `ifdef BOOTROM
  62             import BootRom                      ::*;
  63         `endif
  64         `ifdef SDRAM
  65             import sdr_top                       :: *;
  66     `endif
  67         `ifdef BRAM
  68             import Memory_AXI4  ::*;
  69         `endif
  70         `ifdef TCMemory
  71             import TCM::*;
  72         `endif
  73         `ifdef Debug
  74             import jtagdtm::*;
  75             import DebugModule::*;
  76         `else
  77             import core::*;
  78         `endif
  79 `ifdef  VME
  80             import vme_top ::*;
  81 `endif
  82
  83 `ifdef VME
  84             import vme_master::*;
  85 `endif
  86 `ifdef FlexBus
  87             import FlexBus_Types::*;
  88 `endif
  89 {0}
  90
  91     /*========================= */
  92     interface Ifc_Soc;
  93         interface SP_ios slow_ios;
  94         (*always_ready,always_enabled*)
  95         method Action boot_sequence(Bit#(1) bootseq);
  96
  97           `ifdef SDRAM
  98             (*always_ready*) interface Ifc_sdram_out sdram_out;
  99         `endif
 100       `ifdef DDR
 101         (*prefix="M_AXI"*) interface
 102                 AXI4_Master_IFC#(`PADDR, `Reg_width, `USERSPACE) master;
 103       `endif
 104         `ifdef HYPER
 105             (*always_ready,always_enabled*)
 106            interface Ifc_flash ifc_flash;
 107         `endif
 108     /*=============================================== */
 109        `ifdef VME
 110                 interface Vme_out  proc_ifc;
 111             interface Data_bus_inf proc_dbus;
 112         `endif
 113         `ifdef FlexBus
 114             interface FlexBus_Master_IFC flexbus_out;
 115         `endif
 116 {1}
 117     endinterface
 118     (*synthesize*)
 119     module mkSoc #(Bit#(`VADDR) reset_vector,
 120                  Clock slow_clock, Reset slow_reset, Clock uart_clock,
 121                  Reset uart_reset, Clock clk0, Clock tck, Reset trst
 122                  `ifdef PWM_AXI4Lite ,Clock ext_pwm_clock `endif )(Ifc_Soc);
 123         Clock core_clock <-exposeCurrentClock; // slow peripheral clock
 124         Reset core_reset <-exposeCurrentReset; // slow peripheral reset
 125 {2}
 126       `ifdef Debug
 127             Ifc_DebugModule core<-mkDebugModule(reset_vector);
 128         `else
 129             Ifc_core_AXI4 core <-mkcore_AXI4(reset_vector);
 130         `endif
 131         `ifdef BOOTROM
 132             BootRom_IFC bootrom <-mkBootRom;
 133         `endif
 134         `ifdef SDRAM
 135             Ifc_sdr_slave sdram<- mksdr_axi4_slave(clk0);
 136         `endif
 137     `ifdef BRAM
 138             Memory_IFC#(`SDRAMMemBase,`Addr_space)main_memory <-
 139                         mkMemory("code.mem.MSB","code.mem.LSB","MainMEM");
 140         `endif
 141         `ifdef TCMemory
 142             Ifc_TCM                                     tcm                             <- mkTCM;
 143         `endif
 144         `ifdef DMA
 145             DmaC#(7,`NUM_DMACHANNELS) dma       <- mkDMA();
 146         `endif
 147             `ifdef VME
 148             Ifc_vme_top             vme             <-mkvme_top();
 149             `endif
 150         `ifdef FlexBus
 151             AXI4_Slave_to_FlexBus_Master_Xactor_IFC #(32, 64,0)
 152                             flexbus <- mkAXI4_Slave_to_FlexBus_Master_Xactor;
 153         `endif
 154         Ifc_slow_peripherals slow_peripherals <-mkslow_peripherals(
 155           core_clock, core_reset, uart_clock,
 156           uart_reset, clocked_by slow_clock , reset_by slow_reset
 157           `ifdef PWM_AXI4Lite , ext_pwm_clock `endif );
 158
 159     // Fabric
 160     AXI4_Fabric_IFC #(Num_Masters, Num_Slaves, `PADDR, `Reg_width,`USERSPACE)
 161                 fabric <- mkAXI4_Fabric(fn_addr_to_slave_num);
 162
 163     // Connect traffic generators to fabric
 164     mkConnection (core.dmem_master,fabric.v_from_masters
 165                               [fromInteger(valueOf(Dmem_master_num))]);
 166     mkConnection (core.imem_master,     fabric.v_from_masters
 167                               [fromInteger(valueOf(Imem_master_num))]);
 168         `ifdef Debug
 169             mkConnection (core.debug_master, fabric.v_from_masters
 170                               [fromInteger(valueOf(Debug_master_num))]);
 171         `endif
 172         `ifdef DMA
 173          mkConnection (dma.mmu, fabric.v_from_masters
 174                               [fromInteger(valueOf(DMA_master_num))]);
 175         `endif
 176
 177
 178         // Connect fabric to memory slaves
 179             `ifdef Debug
 180                 mkConnection (fabric.v_to_slaves
 181                               [fromInteger(valueOf(Debug_slave_num))],
 182                               core.debug_slave);
 183             `endif
 184             `ifdef SDRAM
 185                 mkConnection (fabric.v_to_slaves
 186                               [fromInteger(valueOf(Sdram_slave_num))],
 187                               sdram.axi4_slave_sdram); //
 188             mkConnection (fabric.v_to_slaves
 189                               [fromInteger(valueOf(Sdram_cfg_slave_num))],
 190                               sdram.axi4_slave_cntrl_reg); //
 191       `endif
 192       `ifdef BRAM
 193                 mkConnection(fabric.v_to_slaves
 194                               [fromInteger(valueOf(Sdram_slave_num))],
 195                               main_memory.axi_slave);
 196             `endif
 197             `ifdef BOOTROM
 198                 mkConnection (fabric.v_to_slaves
 199                               [fromInteger(valueOf(BootRom_slave_num))],
 200                               bootrom.axi_slave);
 201             `endif
 202             `ifdef DMA
 203             mkConnection (fabric.v_to_slaves
 204                               [fromInteger(valueOf(Dma_slave_num))],
 205                               dma.cfg); //DMA slave
 206             `endif
 207             `ifdef TCMemory
 208                 mkConnection (fabric.v_to_slaves
 209                               [fromInteger(valueOf(TCM_slave_num))],
 210                               tcm.axi_slave);
 211             `endif
 212             mkConnection(fabric.v_to_slaves
 213                               [fromInteger(valueOf(SlowPeripheral_slave_num))],
 214                               slow_peripherals.axi_slave);
 215             `ifdef VME
 216                 mkConnection (fabric.v_to_slaves
 217                               [fromInteger(valueOf(VME_slave_num))],
 218                               vme.slave_axi_vme);
 219             `endif
 220             `ifdef FlexBus
 221                 mkConnection (fabric.v_to_slaves
 222                               [fromInteger(valueOf(FlexBus_slave_num))],
 223                               flexbus.axi_side);
 224             `endif
 225
 226             // fabric connections
 227 {5}
 228
 229             `ifdef DMA
 230             // rule to connect all interrupt lines to the DMA
 231             // All the interrupt lines to DMA are active
 232             // HIGH. For peripherals that are not connected,
 233             // or those which do not
 234             // generate an interrupt (like TCM), drive a constant 1
 235             // on the corresponding interrupt line.
 236 {7}
 237             `endif
 238
 239
 240         /*==== Synchornization between the JTAG and the Debug Module ===== */
 241         `ifdef Debug
 242             SyncFIFOIfc#(Bit#(40)) sync_request_to_dm <-
 243                                         mkSyncFIFOToCC(1,tck,trst);
 244             SyncFIFOIfc#(Bit#(34)) sync_response_from_dm <-
 245                                         mkSyncFIFOFromCC(1,tck);
 246             rule connect_tap_request_to_syncfifo;
 247                 let x<-tap.request_to_dm;
 248                 sync_request_to_dm.enq(x);
 249             endrule
 250             rule read_synced_request_to_dm;
 251                 sync_request_to_dm.deq;
 252                 core.request_from_dtm(sync_request_to_dm.first);
 253             endrule
 254
 255             rule connect_debug_response_to_syncfifo;
 256                 let x<-core.response_to_dtm;
 257                 sync_response_from_dm.enq(x);
 258             endrule
 259             rule read_synced_response_from_dm;
 260                 sync_response_from_dm.deq;
 261                 tap.response_from_dm(sync_response_from_dm.first);
 262             endrule
 263         `endif
 264         /*============================================================ */
 265
 266         `ifdef FlexBus
 267             //rule drive_flexbus_inputs;
 268                //flexbus.flexbus_side.m_TAn(1'b1);
 269                //flexbus.flexbus_side.m_din(32'haaaaaaaa);
 270             //endrule
 271          `endif
 272
 273         `ifdef CLINT
 274             SyncBitIfc#(Bit#(1)) clint_mtip_int <-
 275                                         mkSyncBitToCC(slow_clock,slow_reset);
 276             SyncBitIfc#(Bit#(1)) clint_msip_int <-
 277                                         mkSyncBitToCC(slow_clock,slow_reset);
 278             Reg#(Bit#(`Reg_width)) clint_mtime_value <-
 279                                         mkSyncRegToCC(0,slow_clock,slow_reset);
 280             rule synchronize_clint_data;
 281                 clint_mtip_int.send(slow_peripherals.mtip_int);
 282                 clint_msip_int.send(slow_peripherals.msip_int);
 283                 clint_mtime_value<=slow_peripherals.mtime;
 284             endrule
 285             rule connect_msip_mtip_from_clint;
 286                 core.clint_msip(clint_msip_int.read);
 287                 core.clint_mtip(clint_mtip_int.read);
 288             core.clint_mtime(clint_mtime_value);
 289             endrule
 290         `endif
 291         `ifdef PLIC
 292             Reg#(Tuple2#(Bool,Bool)) plic_interrupt_note <-
 293                                         mkSyncRegToCC(tuple2(False,False),
 294                                                       slow_clock,slow_reset);
 295             rule synchronize_interrupts;
 296                 let note <- slow_peripherals.intrpt_note;
 297                 plic_interrupt_note<=note;
 298             endrule
 299             rule rl_send_external_interrupt_to_csr;
 300                 core.set_external_interrupt(plic_interrupt_note);
 301             endrule
 302         `endif
 303
 304         `ifdef VME
 305             interface  proc_ifc = vme.proc_ifc;
 306             interface   proc_dbus = vme.proc_dbus;
 307         `endif
 308         `ifdef FlexBus
 309             interface flexbus_out = flexbus.flexbus_side;
 310         `endif
 311          method Action boot_sequence(Bit#(1) bootseq) =
 312                             core.boot_sequence(bootseq);
 313         `ifdef SDRAM
 314             interface sdram_out=sdram.ifc_sdram_out;
 315         `endif
 316         `ifdef DDR
 317           interface master=fabric.v_to_slaves
 318                                 [fromInteger(valueOf(Sdram_slave_num))];
 319         `endif
 320         interface slow_ios=slow_peripherals.slow_ios;
 321 {6}
 322     endmodule
 323 endpackage