src/bsv/bsv_lib/soc_template.bsv

   1 /*
   2 Copyright (c) 2013, IIT Madras
   3 All rights reserved.
   4
   5 Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
   6
   7 *  Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
   8 *  Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
   9 *  Neither the name of IIT Madras  nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.
  10
  11 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  12 ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
  13 */
  14 package Soc;
  15         /*====== Package imports === */
  16         import FIFO::*;
  17         import FIFOF::*;
  18         import SpecialFIFOs::*;
  19         import GetPut::*;
  20         import ClientServer::*;
  21         import Vector::*;
  22         import Connectable::*;
  23         import Clocks::*;
  24         /*========================== */
  25         /*=== Project imports === */
  26         import ConcatReg::*;
  27         import AXI4_Types::*;
  28         import AXI4_Fabric::*;
  29         import defined_types::*;
  30         import MemoryMap                 :: *;
  31         import slow_peripherals::*;
  32         `include "defines.bsv"
  33         `include "instance_defines.bsv"
  34     /*====== AXI4 Lite slave declarations =======*/
  35 {3}
  36
  37                 `ifdef DMA
  38                         import DMA                               :: *;
  39                 `endif
  40                 `ifdef BOOTROM
  41                         import BootRom                  ::*;
  42                 `endif
  43                 `ifdef SDRAM
  44                         import sdr_top                   :: *;
  45     `endif
  46                 `ifdef BRAM
  47                         import Memory_AXI4      ::*;
  48                 `endif
  49                 `ifdef TCMemory
  50                         import TCM::*;
  51                 `endif
  52                 `ifdef Debug
  53                         import jtagdtm::*;
  54                         import DebugModule::*;
  55                 `else
  56                         import core::*;
  57                 `endif
  58 `ifdef  VME
  59                         import vme_top ::*;
  60 `endif
  61
  62 `ifdef VME
  63                         import vme_master::*;
  64 `endif
  65 `ifdef FlexBus
  66             import FlexBus_Types::*;
  67 `endif
  68 {0}
  69
  70         /*========================= */
  71         interface Ifc_Soc;
  72                 interface SP_ios slow_ios;
  73                 (*always_ready,always_enabled*)
  74                 method Action boot_sequence(Bit#(1) bootseq);
  75
  76                   `ifdef SDRAM
  77                         (*always_ready*) interface Ifc_sdram_out sdram_out;
  78                 `endif
  79       `ifdef DDR
  80         (*prefix="M_AXI"*) interface AXI4_Master_IFC#(`PADDR, `Reg_width, `USERSPACE) master;
  81       `endif
  82       `ifdef Debug
  83                         (*always_ready,always_enabled*)
  84                         method Action tms_i(Bit#(1) tms);
  85                         (*always_ready,always_enabled*)
  86                         method Action tdi_i(Bit#(1) tdi);
  87                         (*always_ready,always_enabled*)
  88                         method Action bs_chain_i(Bit#(1) bs_chain);
  89                         (*always_ready,always_enabled*)
  90                         method Bit#(1) shiftBscan2Edge;
  91                         (*always_ready,always_enabled*)
  92                         method Bit#(1) selectJtagInput;
  93                         (*always_ready,always_enabled*)
  94                         method Bit#(1) selectJtagOutput;
  95                         (*always_ready,always_enabled*)
  96                         method Bit#(1) updateBscan;
  97                         (*always_ready,always_enabled*)
  98                         method Bit#(1) bscan_in;
  99                         (*always_ready,always_enabled*)
 100                         method Bit#(1) scan_shift_en;
 101                         (*always_ready,always_enabled*)
 102                         method Bit#(1) tdo;
 103                         (*always_ready,always_enabled*)
 104                         method Bit#(1) tdo_oe;
 105                 `endif
 106                 `ifdef HYPER
 107                         (*always_ready,always_enabled*)
 108                    interface Ifc_flash ifc_flash;
 109                 `endif
 110         /*=============================================== */
 111            `ifdef VME
 112                         interface Vme_out  proc_ifc;
 113                         interface Data_bus_inf proc_dbus;
 114                 `endif
 115         `ifdef FlexBus
 116             interface FlexBus_Master_IFC flexbus_out;
 117         `endif
 118 {1}
 119         endinterface
 120         (*synthesize*)
 121         module mkSoc #(Bit#(`VADDR) reset_vector, Clock slow_clock, Reset slow_reset, Clock uart_clock,
 122                  Reset uart_reset, Clock clk0, Clock tck, Reset trst
 123                  `ifdef PWM_AXI4Lite ,Clock ext_pwm_clock `endif )(Ifc_Soc);
 124                 Clock core_clock <-exposeCurrentClock; // slow peripheral clock
 125                 Reset core_reset <-exposeCurrentReset; // slow peripheral reset
 126 {2}
 127       `ifdef Debug
 128                         Ifc_DebugModule core<-mkDebugModule(reset_vector);
 129                 `else
 130                         Ifc_core_AXI4 core <-mkcore_AXI4(reset_vector);
 131                 `endif
 132                 `ifdef BOOTROM
 133                         BootRom_IFC bootrom <-mkBootRom;
 134                 `endif
 135                 `ifdef SDRAM
 136                         Ifc_sdr_slave                   sdram                           <- mksdr_axi4_slave(clk0);
 137                 `endif
 138     `ifdef BRAM
 139                         Memory_IFC#(`SDRAMMemBase,`Addr_space) main_memory <- mkMemory("code.mem.MSB","code.mem.LSB","MainMEM");
 140                 `endif
 141                 `ifdef TCMemory
 142                         Ifc_TCM                                 tcm                             <- mkTCM;
 143                 `endif
 144                 `ifdef DMA
 145                         DmaC#(7,12)                             dma                             <- mkDMA();
 146                 `endif
 147                         `ifdef VME
 148                         Ifc_vme_top             vme             <-mkvme_top();
 149                         `endif
 150         `ifdef FlexBus
 151             AXI4_Slave_to_FlexBus_Master_Xactor_IFC #(32, 64,0)
 152                                             flexbus <- mkAXI4_Slave_to_FlexBus_Master_Xactor;
 153         `endif
 154                 Ifc_slow_peripherals slow_peripherals <-mkslow_peripherals(core_clock, core_reset, uart_clock,
 155           uart_reset, clocked_by slow_clock , reset_by slow_reset
 156           `ifdef PWM_AXI4Lite , ext_pwm_clock `endif );
 157
 158         // Fabric
 159         AXI4_Fabric_IFC #(Num_Masters, Num_Slaves, `PADDR, `Reg_width,`USERSPACE)
 160                                 fabric <- mkAXI4_Fabric(fn_addr_to_slave_num);
 161
 162         // Connect traffic generators to fabric
 163         mkConnection (core.dmem_master, fabric.v_from_masters [fromInteger(valueOf(Dmem_master_num))]);
 164         mkConnection (core.imem_master, fabric.v_from_masters [fromInteger(valueOf(Imem_master_num))]);
 165                 `ifdef Debug
 166                         mkConnection (core.debug_master, fabric.v_from_masters [fromInteger(valueOf(Debug_master_num))]);
 167                 `endif
 168                 `ifdef DMA
 169          mkConnection (dma.mmu, fabric.v_from_masters[fromInteger(valueOf(DMA_master_num))]);
 170                 `endif
 171
 172
 173                 // Connect fabric to memory slaves
 174                         `ifdef Debug
 175                                 mkConnection (fabric.v_to_slaves [fromInteger(valueOf(Debug_slave_num))],core.debug_slave);
 176                         `endif
 177                         `ifdef SDRAM
 178                                 mkConnection (fabric.v_to_slaves [fromInteger(valueOf(Sdram_slave_num))],       sdram.axi4_slave_sdram); //
 179                         mkConnection (fabric.v_to_slaves [fromInteger(valueOf(Sdram_cfg_slave_num))],   sdram.axi4_slave_cntrl_reg); //
 180       `endif
 181       `ifdef BRAM
 182                                 mkConnection(fabric.v_to_slaves[fromInteger(valueOf(Sdram_slave_num))],main_memory.axi_slave);
 183                         `endif
 184                         `ifdef BOOTROM
 185                                 mkConnection (fabric.v_to_slaves [fromInteger(valueOf(BootRom_slave_num))],bootrom.axi_slave);
 186                         `endif
 187                         `ifdef DMA
 188                         mkConnection (fabric.v_to_slaves [fromInteger(valueOf(Dma_slave_num))], dma.cfg); //DMA slave
 189                         `endif
 190                         `ifdef TCMemory
 191                                 mkConnection (fabric.v_to_slaves [fromInteger(valueOf(TCM_slave_num))],tcm.axi_slave);
 192                         `endif
 193                         mkConnection(fabric.v_to_slaves [fromInteger(valueOf(SlowPeripheral_slave_num))],slow_peripherals.axi_slave);
 194                         `ifdef VME
 195                                 mkConnection (fabric.v_to_slaves[fromInteger(valueOf(VME_slave_num))],vme.slave_axi_vme);
 196                         `endif
 197                         `ifdef FlexBus
 198                                 mkConnection (fabric.v_to_slaves[fromInteger(valueOf(FlexBus_slave_num))],flexbus.axi_side);
 199                         `endif
 200                         `ifdef DMA
 201                         //rule to connect all interrupt lines to the DMA
 202                         //All the interrupt lines to DMA are active HIGH. For peripherals that are not connected, or those which do not
 203                         //generate an interrupt (like TCM), drive a constant 1 on the corresponding interrupt line.
 204                                 `ifdef I2C1 SyncBitIfc#(Bit#(1)) i2c1_interrupt <-mkSyncBitToCC(slow_clock,slow_reset); `endif
 205                                 `ifdef I2C0 SyncBitIfc#(Bit#(1)) i2c0_interrupt <-mkSyncBitToCC(slow_clock,slow_reset); `endif
 206                                 `ifdef QSPI1 SyncBitIfc#(Bit#(1)) qspi1_interrupt <-mkSyncBitToCC(slow_clock,slow_reset); `endif
 207                                 `ifdef QSPI0 SyncBitIfc#(Bit#(1)) qspi0_interrupt <-mkSyncBitToCC(slow_clock,slow_reset); `endif
 208                                 `ifdef UART0 SyncBitIfc#(Bit#(1)) uart0_interrupt <-mkSyncBitToCC(uart_clock,uart_reset); `endif
 209                                 rule synchronize_i2c_interrupts;
 210                                         `ifdef I2C1 i2c1_interrupt.send(slow_peripherals.i2c1_isint); `endif
 211                                         `ifdef I2C0 i2c0_interrupt.send(slow_peripherals.i2c0_isint); `endif
 212                                 endrule
 213                                 rule synchronize_qspi_interrupts;
 214                                         `ifdef QSPI0 qspi0_interrupt.send(slow_peripherals.qspi0_isint); `endif
 215                                         `ifdef QSPI1 qspi1_interrupt.send(slow_peripherals.qspi1_isint); `endif
 216                                 endrule
 217                                 rule synchronize_uart0_interrupt;
 218                                         `ifdef UART0 uart0_interrupt.send(slow_peripherals.uart0_intr); `endif
 219                                 endrule
 220                                 rule rl_connect_interrupt_to_DMA;
 221                                         Bit#(12) lv_interrupt_to_DMA= {{'d-1,
 222                                                                                                                         `ifdef I2C1 i2c1_interrupt.read `else 1'b1 `endif ,
 223                                                                                                                         `ifdef I2C0 i2c0_interrupt.read `else 1'b1 `endif ,
 224                                                                                                                         `ifdef QSPI1 qspi1_interrupt.read `else 1'b1 `endif ,
 225                                                                                                                         1'b1,
 226                                                                                                                         `ifdef QSPI0 qspi0_interrupt.read `else 1'b1 `endif ,
 227                                                                                                                         1'b1,1'b0,
 228                                                                                                                         `ifdef UART0 uart0_interrupt.read `else 1'b1 `endif }};
 229                                         dma.interrupt_from_peripherals(lv_interrupt_to_DMA);
 230                                 endrule
 231                         `endif
 232
 233
 234                 /*======= Synchornization between the JTAG and the Debug Module ========= */
 235                 `ifdef Debug
 236                         SyncFIFOIfc#(Bit#(40)) sync_request_to_dm <-mkSyncFIFOToCC(1,tck,trst);
 237                         SyncFIFOIfc#(Bit#(34)) sync_response_from_dm <-mkSyncFIFOFromCC(1,tck);
 238                         rule connect_tap_request_to_syncfifo;
 239                                 let x<-tap.request_to_dm;
 240                                 sync_request_to_dm.enq(x);
 241                         endrule
 242                         rule read_synced_request_to_dm;
 243                                 sync_request_to_dm.deq;
 244                                 core.request_from_dtm(sync_request_to_dm.first);
 245                         endrule
 246
 247                         rule connect_debug_response_to_syncfifo;
 248                                 let x<-core.response_to_dtm;
 249                                 sync_response_from_dm.enq(x);
 250                         endrule
 251                         rule read_synced_response_from_dm;
 252                                 sync_response_from_dm.deq;
 253                                 tap.response_from_dm(sync_response_from_dm.first);
 254                         endrule
 255                 `endif
 256                 /*======================================================================= */
 257
 258         `ifdef FlexBus
 259             //rule drive_flexbus_inputs;
 260                //flexbus.flexbus_side.m_TAn(1'b1);
 261                //flexbus.flexbus_side.m_din(32'haaaaaaaa);
 262             //endrule
 263          `endif
 264
 265                 `ifdef CLINT
 266                         SyncBitIfc#(Bit#(1)) clint_mtip_int <-mkSyncBitToCC(slow_clock,slow_reset);
 267                         SyncBitIfc#(Bit#(1)) clint_msip_int <-mkSyncBitToCC(slow_clock,slow_reset);
 268                         Reg#(Bit#(`Reg_width)) clint_mtime_value <-mkSyncRegToCC(0,slow_clock,slow_reset);
 269                         rule synchronize_clint_data;
 270                                 clint_mtip_int.send(slow_peripherals.mtip_int);
 271                                 clint_msip_int.send(slow_peripherals.msip_int);
 272                                 clint_mtime_value<=slow_peripherals.mtime;
 273                         endrule
 274                         rule connect_msip_mtip_from_clint;
 275                                 core.clint_msip(clint_msip_int.read);
 276                                 core.clint_mtip(clint_mtip_int.read);
 277             core.clint_mtime(clint_mtime_value);
 278                         endrule
 279                 `endif
 280                 `ifdef PLIC
 281                         Reg#(Tuple2#(Bool,Bool)) plic_interrupt_note <-mkSyncRegToCC(tuple2(False,False),slow_clock,slow_reset);
 282                         rule synchronize_interrupts;
 283                                 let note <- slow_peripherals.intrpt_note;
 284                                 plic_interrupt_note<=note;
 285                         endrule
 286          rule rl_send_external_interrupt_to_csr;
 287                                 core.set_external_interrupt(plic_interrupt_note);
 288                         endrule
 289                 `endif
 290
 291                 `ifdef VME
 292                         interface  proc_ifc = vme.proc_ifc;
 293                         interface   proc_dbus = vme.proc_dbus;
 294                 `endif
 295                 `ifdef FlexBus
 296             interface flexbus_out = flexbus.flexbus_side;
 297                 `endif
 298       method Action boot_sequence(Bit#(1) bootseq) = core.boot_sequence(bootseq);
 299                 `ifdef SDRAM
 300                         interface sdram_out=sdram.ifc_sdram_out;
 301                 `endif
 302     `ifdef DDR
 303       interface master=fabric.v_to_slaves[fromInteger(valueOf(Sdram_slave_num))];
 304     `endif
 305                 `ifdef Debug
 306                         method Action tms_i(Bit#(1) tms);
 307                                 tap.tms_i(tms);
 308                         endmethod
 309                         method Action tdi_i(Bit#(1) tdi);
 310                                 tap.tdi_i(tdi);
 311                         endmethod
 312                         method Action bs_chain_i(Bit#(1) bs_chain);
 313                                 tap.bs_chain_i(bs_chain);
 314                         endmethod
 315                         method Bit#(1) shiftBscan2Edge=tap.shiftBscan2Edge;
 316                         method Bit#(1) selectJtagInput=tap.selectJtagInput;
 317                         method Bit#(1) selectJtagOutput=tap.selectJtagOutput;
 318                         method Bit#(1) updateBscan=tap.updateBscan;
 319                         method Bit#(1) bscan_in=tap.bscan_in;
 320             method Bit#(1) scan_shift_en=tap.scan_shift_en;
 321                         method Bit#(1) tdo=tap.tdo;
 322                         method Bit#(1) tdo_oe=tap.tdo_oe;
 323                 `endif
 324                 interface slow_ios=slow_peripherals.slow_ios;
 325
 326         endmodule
 327 endpackage