src/bsv/bsv_lib/soc_template.bsv

   1 /*
   2 Copyright (c) 2013, IIT Madras
   3 All rights reserved.
   4
   5 Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
   6
   7 *  Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
   8 *  Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
   9 *  Neither the name of IIT Madras  nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.
  10
  11 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  12 ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
  13 */
  14 package Soc;
  15         /*====== Package imports === */
  16         import FIFO::*;
  17         import FIFOF::*;
  18         import SpecialFIFOs::*;
  19         import GetPut::*;
  20         import ClientServer::*;
  21         import Vector::*;
  22         import Connectable::*;
  23         import Clocks::*;
  24         /*========================== */
  25         /*=== Project imports === */
  26         import ConcatReg::*;
  27         import AXI4_Types::*;
  28         import AXI4_Fabric::*;
  29         import defined_types::*;
  30         import MemoryMap                 :: *;
  31         import slow_peripherals::*;
  32         `include "defines.bsv"
  33         `include "instance_defines.bsv"
  34     /*====== AXI4 slave declarations =======*/
  35 {3}
  36     /*====== AXI4 Master declarations =======*/
  37 {4}
  38
  39
  40                 `ifdef DMA
  41                         import DMA                               :: *;
  42                 `endif
  43                 `ifdef BOOTROM
  44                         import BootRom                  ::*;
  45                 `endif
  46                 `ifdef SDRAM
  47                         import sdr_top                   :: *;
  48     `endif
  49                 `ifdef BRAM
  50                         import Memory_AXI4      ::*;
  51                 `endif
  52                 `ifdef TCMemory
  53                         import TCM::*;
  54                 `endif
  55                 `ifdef Debug
  56                         import jtagdtm::*;
  57                         import DebugModule::*;
  58                 `else
  59                         import core::*;
  60                 `endif
  61 `ifdef  VME
  62                         import vme_top ::*;
  63 `endif
  64
  65 `ifdef VME
  66                         import vme_master::*;
  67 `endif
  68 `ifdef FlexBus
  69             import FlexBus_Types::*;
  70 `endif
  71 {0}
  72
  73         /*========================= */
  74         interface Ifc_Soc;
  75                 interface SP_ios slow_ios;
  76                 (*always_ready,always_enabled*)
  77                 method Action boot_sequence(Bit#(1) bootseq);
  78
  79                   `ifdef SDRAM
  80                         (*always_ready*) interface Ifc_sdram_out sdram_out;
  81                 `endif
  82       `ifdef DDR
  83         (*prefix="M_AXI"*) interface AXI4_Master_IFC#(`PADDR, `Reg_width, `USERSPACE) master;
  84       `endif
  85                 `ifdef HYPER
  86                         (*always_ready,always_enabled*)
  87                    interface Ifc_flash ifc_flash;
  88                 `endif
  89         /*=============================================== */
  90            `ifdef VME
  91                         interface Vme_out  proc_ifc;
  92                         interface Data_bus_inf proc_dbus;
  93                 `endif
  94         `ifdef FlexBus
  95             interface FlexBus_Master_IFC flexbus_out;
  96         `endif
  97 {1}
  98         endinterface
  99         (*synthesize*)
 100         module mkSoc #(Bit#(`VADDR) reset_vector, Clock slow_clock, Reset slow_reset, Clock uart_clock,
 101                  Reset uart_reset, Clock clk0, Clock tck, Reset trst
 102                  `ifdef PWM_AXI4Lite ,Clock ext_pwm_clock `endif )(Ifc_Soc);
 103                 Clock core_clock <-exposeCurrentClock; // slow peripheral clock
 104                 Reset core_reset <-exposeCurrentReset; // slow peripheral reset
 105 {2}
 106       `ifdef Debug
 107                         Ifc_DebugModule core<-mkDebugModule(reset_vector);
 108                 `else
 109                         Ifc_core_AXI4 core <-mkcore_AXI4(reset_vector);
 110                 `endif
 111                 `ifdef BOOTROM
 112                         BootRom_IFC bootrom <-mkBootRom;
 113                 `endif
 114                 `ifdef SDRAM
 115                         Ifc_sdr_slave                   sdram                           <- mksdr_axi4_slave(clk0);
 116                 `endif
 117     `ifdef BRAM
 118                         Memory_IFC#(`SDRAMMemBase,`Addr_space) main_memory <- mkMemory("code.mem.MSB","code.mem.LSB","MainMEM");
 119                 `endif
 120                 `ifdef TCMemory
 121                         Ifc_TCM                                 tcm                             <- mkTCM;
 122                 `endif
 123                 `ifdef DMA
 124                         DmaC#(7,12)                             dma                             <- mkDMA();
 125                 `endif
 126                         `ifdef VME
 127                         Ifc_vme_top             vme             <-mkvme_top();
 128                         `endif
 129         `ifdef FlexBus
 130             AXI4_Slave_to_FlexBus_Master_Xactor_IFC #(32, 64,0)
 131                                             flexbus <- mkAXI4_Slave_to_FlexBus_Master_Xactor;
 132         `endif
 133                 Ifc_slow_peripherals slow_peripherals <-mkslow_peripherals(core_clock, core_reset, uart_clock,
 134           uart_reset, clocked_by slow_clock , reset_by slow_reset
 135           `ifdef PWM_AXI4Lite , ext_pwm_clock `endif );
 136
 137         // Fabric
 138         AXI4_Fabric_IFC #(Num_Masters, Num_Slaves, `PADDR, `Reg_width,`USERSPACE)
 139                                 fabric <- mkAXI4_Fabric(fn_addr_to_slave_num);
 140
 141         // Connect traffic generators to fabric
 142         mkConnection (core.dmem_master, fabric.v_from_masters [fromInteger(valueOf(Dmem_master_num))]);
 143         mkConnection (core.imem_master, fabric.v_from_masters [fromInteger(valueOf(Imem_master_num))]);
 144                 `ifdef Debug
 145                         mkConnection (core.debug_master, fabric.v_from_masters [fromInteger(valueOf(Debug_master_num))]);
 146                 `endif
 147                 `ifdef DMA
 148          mkConnection (dma.mmu, fabric.v_from_masters[fromInteger(valueOf(DMA_master_num))]);
 149                 `endif
 150
 151
 152                 // Connect fabric to memory slaves
 153                         `ifdef Debug
 154                                 mkConnection (fabric.v_to_slaves [fromInteger(valueOf(Debug_slave_num))],core.debug_slave);
 155                         `endif
 156                         `ifdef SDRAM
 157                                 mkConnection (fabric.v_to_slaves [fromInteger(valueOf(Sdram_slave_num))],       sdram.axi4_slave_sdram); //
 158                         mkConnection (fabric.v_to_slaves [fromInteger(valueOf(Sdram_cfg_slave_num))],   sdram.axi4_slave_cntrl_reg); //
 159       `endif
 160       `ifdef BRAM
 161                                 mkConnection(fabric.v_to_slaves[fromInteger(valueOf(Sdram_slave_num))],main_memory.axi_slave);
 162                         `endif
 163                         `ifdef BOOTROM
 164                                 mkConnection (fabric.v_to_slaves [fromInteger(valueOf(BootRom_slave_num))],bootrom.axi_slave);
 165                         `endif
 166                         `ifdef DMA
 167                         mkConnection (fabric.v_to_slaves [fromInteger(valueOf(Dma_slave_num))], dma.cfg); //DMA slave
 168                         `endif
 169                         `ifdef TCMemory
 170                                 mkConnection (fabric.v_to_slaves [fromInteger(valueOf(TCM_slave_num))],tcm.axi_slave);
 171                         `endif
 172                         mkConnection(fabric.v_to_slaves [fromInteger(valueOf(SlowPeripheral_slave_num))],slow_peripherals.axi_slave);
 173                         `ifdef VME
 174                                 mkConnection (fabric.v_to_slaves[fromInteger(valueOf(VME_slave_num))],vme.slave_axi_vme);
 175                         `endif
 176                         `ifdef FlexBus
 177                                 mkConnection (fabric.v_to_slaves[fromInteger(valueOf(FlexBus_slave_num))],flexbus.axi_side);
 178                         `endif
 179
 180 // fabric connections
 181 {5}
 182
 183                         `ifdef DMA
 184                         //rule to connect all interrupt lines to the DMA
 185                         //All the interrupt lines to DMA are active HIGH. For peripherals that are not connected, or those which do not
 186                         //generate an interrupt (like TCM), drive a constant 1 on the corresponding interrupt line.
 187                                 `ifdef I2C1 SyncBitIfc#(Bit#(1)) i2c1_interrupt <-mkSyncBitToCC(slow_clock,slow_reset); `endif
 188                                 `ifdef I2C0 SyncBitIfc#(Bit#(1)) i2c0_interrupt <-mkSyncBitToCC(slow_clock,slow_reset); `endif
 189                                 `ifdef QSPI1 SyncBitIfc#(Bit#(1)) qspi1_interrupt <-mkSyncBitToCC(slow_clock,slow_reset); `endif
 190                                 `ifdef QSPI0 SyncBitIfc#(Bit#(1)) qspi0_interrupt <-mkSyncBitToCC(slow_clock,slow_reset); `endif
 191                                 `ifdef UART0 SyncBitIfc#(Bit#(1)) uart0_interrupt <-mkSyncBitToCC(uart_clock,uart_reset); `endif
 192                                 rule synchronize_i2c_interrupts;
 193                                         `ifdef I2C1 i2c1_interrupt.send(slow_peripherals.i2c1_isint); `endif
 194                                         `ifdef I2C0 i2c0_interrupt.send(slow_peripherals.i2c0_isint); `endif
 195                                 endrule
 196                                 rule synchronize_qspi_interrupts;
 197                                         `ifdef QSPI0 qspi0_interrupt.send(slow_peripherals.qspi0_isint); `endif
 198                                         `ifdef QSPI1 qspi1_interrupt.send(slow_peripherals.qspi1_isint); `endif
 199                                 endrule
 200                                 rule synchronize_uart0_interrupt;
 201                                         `ifdef UART0 uart0_interrupt.send(slow_peripherals.uart0_intr); `endif
 202                                 endrule
 203                                 rule rl_connect_interrupt_to_DMA;
 204                                         Bit#(12) lv_interrupt_to_DMA= {{'d-1,
 205                                                                                                                         `ifdef I2C1 i2c1_interrupt.read `else 1'b1 `endif ,
 206                                                                                                                         `ifdef I2C0 i2c0_interrupt.read `else 1'b1 `endif ,
 207                                                                                                                         `ifdef QSPI1 qspi1_interrupt.read `else 1'b1 `endif ,
 208                                                                                                                         1'b1,
 209                                                                                                                         `ifdef QSPI0 qspi0_interrupt.read `else 1'b1 `endif ,
 210                                                                                                                         1'b1,1'b0,
 211                                                                                                                         `ifdef UART0 uart0_interrupt.read `else 1'b1 `endif }};
 212                                         dma.interrupt_from_peripherals(lv_interrupt_to_DMA);
 213                                 endrule
 214 {7}
 215                         `endif
 216
 217
 218                 /*======= Synchornization between the JTAG and the Debug Module ========= */
 219                 `ifdef Debug
 220                         SyncFIFOIfc#(Bit#(40)) sync_request_to_dm <-mkSyncFIFOToCC(1,tck,trst);
 221                         SyncFIFOIfc#(Bit#(34)) sync_response_from_dm <-mkSyncFIFOFromCC(1,tck);
 222                         rule connect_tap_request_to_syncfifo;
 223                                 let x<-tap.request_to_dm;
 224                                 sync_request_to_dm.enq(x);
 225                         endrule
 226                         rule read_synced_request_to_dm;
 227                                 sync_request_to_dm.deq;
 228                                 core.request_from_dtm(sync_request_to_dm.first);
 229                         endrule
 230
 231                         rule connect_debug_response_to_syncfifo;
 232                                 let x<-core.response_to_dtm;
 233                                 sync_response_from_dm.enq(x);
 234                         endrule
 235                         rule read_synced_response_from_dm;
 236                                 sync_response_from_dm.deq;
 237                                 tap.response_from_dm(sync_response_from_dm.first);
 238                         endrule
 239                 `endif
 240                 /*======================================================================= */
 241
 242         `ifdef FlexBus
 243             //rule drive_flexbus_inputs;
 244                //flexbus.flexbus_side.m_TAn(1'b1);
 245                //flexbus.flexbus_side.m_din(32'haaaaaaaa);
 246             //endrule
 247          `endif
 248
 249                 `ifdef CLINT
 250                         SyncBitIfc#(Bit#(1)) clint_mtip_int <-mkSyncBitToCC(slow_clock,slow_reset);
 251                         SyncBitIfc#(Bit#(1)) clint_msip_int <-mkSyncBitToCC(slow_clock,slow_reset);
 252                         Reg#(Bit#(`Reg_width)) clint_mtime_value <-mkSyncRegToCC(0,slow_clock,slow_reset);
 253                         rule synchronize_clint_data;
 254                                 clint_mtip_int.send(slow_peripherals.mtip_int);
 255                                 clint_msip_int.send(slow_peripherals.msip_int);
 256                                 clint_mtime_value<=slow_peripherals.mtime;
 257                         endrule
 258                         rule connect_msip_mtip_from_clint;
 259                                 core.clint_msip(clint_msip_int.read);
 260                                 core.clint_mtip(clint_mtip_int.read);
 261             core.clint_mtime(clint_mtime_value);
 262                         endrule
 263                 `endif
 264                 `ifdef PLIC
 265                         Reg#(Tuple2#(Bool,Bool)) plic_interrupt_note <-mkSyncRegToCC(tuple2(False,False),slow_clock,slow_reset);
 266                         rule synchronize_interrupts;
 267                                 let note <- slow_peripherals.intrpt_note;
 268                                 plic_interrupt_note<=note;
 269                         endrule
 270          rule rl_send_external_interrupt_to_csr;
 271                                 core.set_external_interrupt(plic_interrupt_note);
 272                         endrule
 273                 `endif
 274
 275                 `ifdef VME
 276                         interface  proc_ifc = vme.proc_ifc;
 277                         interface   proc_dbus = vme.proc_dbus;
 278                 `endif
 279                 `ifdef FlexBus
 280             interface flexbus_out = flexbus.flexbus_side;
 281                 `endif
 282       method Action boot_sequence(Bit#(1) bootseq) = core.boot_sequence(bootseq);
 283                 `ifdef SDRAM
 284                         interface sdram_out=sdram.ifc_sdram_out;
 285                 `endif
 286     `ifdef DDR
 287       interface master=fabric.v_to_slaves[fromInteger(valueOf(Sdram_slave_num))];
 288     `endif
 289                 interface slow_ios=slow_peripherals.slow_ios;
 290 {6}
 291         endmodule
 292 endpackage