src/bsv/bsv_lib/soc_template.bsv

   1 /*
   2 Copyright (c) 2013, IIT Madras
   3 All rights reserved.
   4
   5 Redistribution and use in source and binary forms, with or without
   6 modification, are permitted provided that the following conditions
   7 are met:
   8
   9 *  Redistributions of source code must retain the above copyright notice,
  10    this list of conditions and the following disclaimer.
  11 *  Redistributions in binary form must reproduce the above copyright
  12    notice, this list of conditions and the following disclaimer in the
  13    documentation and/or other materials provided with the distribution.
  14 *  Neither the name of IIT Madras  nor the names of its contributors
  15    may be used to endorse or promote products derived from this software
  16    without specific prior written permission.
  17
  18 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  19 "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  20 LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  21 A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  22 HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  23 SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
  24 TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
  25 PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
  26 LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
  27 NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  28 SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  29 -------------------------------------------------------------------
  30 */
  31 package socgen;
  32     /*====== Package imports === */
  33     import FIFO::*;
  34     import FIFOF::*;
  35     import SpecialFIFOs::*;
  36     import GetPut::*;
  37     import ClientServer::*;
  38     import Vector::*;
  39     import Connectable::*;
  40     import Clocks::*;
  41
  42     /*=== Project imports === */
  43     import ConcatReg::*;
  44     import AXI4_Types::*;
  45     import AXI4_Fabric::*;
  46     import defined_types::*;
  47     import MemoryMap             :: *;
  48     import slow_peripherals::*;
  49 `ifdef DEBUG
  50     `include "defines.bsv"
  51 `endif
  52     `include "instance_defines.bsv"
  53     `include "core_parameters.bsv"
  54 {8}
  55
  56     `ifdef DMA
  57         import DMA                               :: *;
  58     `endif
  59     `ifdef BOOTROM
  60         import BootRom                  ::*;
  61     `endif
  62     `ifdef SDRAM
  63         import sdr_top                   :: *;
  64     `endif
  65     `ifdef BRAM
  66         import Memory_AXI4      ::*;
  67     `endif
  68     `ifdef TCMemory
  69         import TCM::*;
  70     `endif
  71     `ifdef Debug
  72         import DebugModule::*;
  73     `else
  74         import core::*;
  75     `endif
  76     `ifdef  VME
  77         import vme_top ::*;
  78     `endif
  79
  80     `ifdef VME
  81         import vme_master::*;
  82     `endif
  83     `ifdef FlexBus
  84         import FlexBus_Types::*;
  85     `endif
  86 {0}
  87
  88     /*========================= */
  89     interface Ifc_Soc;
  90         interface SP_ios slow_ios;
  91         (*always_ready,always_enabled*)
  92         method Action boot_sequence(Bit#(1) bootseq);
  93
  94         `ifdef SDRAM
  95             (*always_ready*) interface Ifc_sdram_out sdram_out;
  96         `endif
  97         `ifdef DDR
  98             (*prefix="M_AXI"*) interface
  99                    AXI4_Master_IFC#(`ADDR, `DATA, `USERSPACE) master;
 100         `endif
 101         `ifdef HYPER
 102              (*always_ready,always_enabled*)
 103              interface Ifc_flash ifc_flash;
 104         `endif
 105         /*=============================================== */
 106         `ifdef VME
 107              interface Vme_out  proc_ifc;
 108              interface Data_bus_inf proc_dbus;
 109         `endif
 110 {1}
 111     endinterface
 112
 113     //============ mkSoc module =================
 114
 115     (*synthesize*)
 116     module mkSoc #(Bit#(`VADDR) reset_vector,
 117                  Clock slow_clock, Reset slow_reset, Clock uart_clock,
 118                  Reset uart_reset, Clock clk0, Clock tck, Reset trst
 119                  `ifdef PWM_AXI4Lite ,Clock ext_pwm_clock `endif )(Ifc_Soc);
 120         Clock core_clock <-exposeCurrentClock; // slow peripheral clock
 121         Reset core_reset <-exposeCurrentReset; // slow peripheral reset
 122 {2}
 123         `ifdef Debug
 124             Ifc_DebugModule core<-mkDebugModule(reset_vector);
 125         `else
 126             Ifc_core_AXI4 core <-mkcore_AXI4(reset_vector);
 127         `endif
 128         `ifdef BOOTROM
 129             BootRom_IFC bootrom <-mkBootRom;
 130         `endif
 131         `ifdef SDRAM
 132             Ifc_sdr_slave sdram<- mksdr_axi4_slave(clk0);
 133         `endif
 134         `ifdef BRAM
 135             Memory_IFC#(`SDRAMMemBase,`Addr_space)main_memory <-
 136                         mkMemory("code.mem.MSB","code.mem.LSB","MainMEM");
 137         `endif
 138         `ifdef TCMemory
 139             Ifc_TCM                                     tcm                             <- mkTCM;
 140         `endif
 141         `ifdef DMA
 142             DmaC#(7,`NUM_DMACHANNELS) dma       <- mkDMA();
 143         `endif
 144             `ifdef VME
 145             Ifc_vme_top             vme             <-mkvme_top();
 146             `endif
 147         Ifc_slow_peripherals slow_peripherals <-mkslow_peripherals(
 148                           core_clock, core_reset, uart_clock,
 149                           uart_reset, clocked_by slow_clock ,
 150                           reset_by slow_reset
 151                           `ifdef PWM_AXI4Lite , ext_pwm_clock `endif );
 152
 153         // Fabric
 154         AXI4_Fabric_IFC #(Num_Masters, Num_Fast_Slaves,
 155                           `ADDR, `DATA,`USERSPACE)
 156                         fabric <- mkAXI4_Fabric(fn_addr_to_slave_num);
 157
 158         // Connect traffic generators to fabric
 159         mkConnection (core.dmem_master,fabric.v_from_masters
 160                               [fromInteger(valueOf(Dmem_master_num))]);
 161         mkConnection (core.imem_master, fabric.v_from_masters
 162                               [fromInteger(valueOf(Imem_master_num))]);
 163         `ifdef Debug
 164             mkConnection (core.debug_master, fabric.v_from_masters
 165                               [fromInteger(valueOf(Debug_master_num))]);
 166         `endif
 167         `ifdef DMA
 168          mkConnection (dma.mmu, fabric.v_from_masters
 169                               [fromInteger(valueOf(DMA_master_num))]);
 170         `endif
 171
 172
 173         // Connect fabric to memory slaves
 174             `ifdef Debug
 175                 mkConnection (fabric.v_to_slaves
 176                               [fromInteger(valueOf(Debug_slave_num))],
 177                               core.debug_slave);
 178             `endif
 179             `ifdef SDRAM
 180                 mkConnection (fabric.v_to_slaves
 181                               [fromInteger(valueOf(Sdram_slave_num))],
 182                               sdram.axi4_slave_sdram); //
 183             mkConnection (fabric.v_to_slaves
 184                               [fromInteger(valueOf(Sdram_cfg_slave_num))],
 185                               sdram.axi4_slave_cntrl_reg); //
 186       `endif
 187       `ifdef BRAM
 188                 mkConnection(fabric.v_to_slaves
 189                               [fromInteger(valueOf(Sdram_slave_num))],
 190                               main_memory.axi_slave);
 191             `endif
 192             `ifdef BOOTROM
 193                 mkConnection (fabric.v_to_slaves
 194                               [fromInteger(valueOf(BootRom_slave_num))],
 195                               bootrom.axi_slave);
 196             `endif
 197             `ifdef DMA
 198             mkConnection (fabric.v_to_slaves
 199                               [fromInteger(valueOf(Dma_slave_num))],
 200                               dma.cfg); //DMA slave
 201             `endif
 202             `ifdef TCMemory
 203                 mkConnection (fabric.v_to_slaves
 204                               [fromInteger(valueOf(TCM_slave_num))],
 205                               tcm.axi_slave);
 206             `endif
 207             mkConnection(fabric.v_to_slaves
 208                               [fromInteger(valueOf(SlowPeripheral_slave_num))],
 209                               slow_peripherals.axi_slave);
 210             `ifdef VME
 211                 mkConnection (fabric.v_to_slaves
 212                               [fromInteger(valueOf(VME_slave_num))],
 213                               vme.slave_axi_vme);
 214             `endif
 215
 216 //          pin connections
 217 {9}
 218
 219             // fabric connections
 220 {5}
 221
 222             `ifdef DMA
 223             // rule to connect all interrupt lines to the DMA
 224             // All the interrupt lines to DMA are active
 225             // HIGH. For peripherals that are not connected,
 226             // or those which do not
 227             // generate an interrupt (like TCM), drive a constant 1
 228             // on the corresponding interrupt line.
 229 {7}
 230             `endif
 231
 232
 233         /*==== Synchornization between the JTAG and the Debug Module ===== */
 234         `ifdef Debug
 235             SyncFIFOIfc#(Bit#(40)) sync_request_to_dm <-
 236                                         mkSyncFIFOToCC(1,tck,trst);
 237             SyncFIFOIfc#(Bit#(34)) sync_response_from_dm <-
 238                                         mkSyncFIFOFromCC(1,tck);
 239             rule connect_tap_request_to_syncfifo;
 240                 let x<-tap.request_to_dm;
 241                 sync_request_to_dm.enq(x);
 242             endrule
 243             rule read_synced_request_to_dm;
 244                 sync_request_to_dm.deq;
 245                 core.request_from_dtm(sync_request_to_dm.first);
 246             endrule
 247
 248             rule connect_debug_response_to_syncfifo;
 249                 let x<-core.response_to_dtm;
 250                 sync_response_from_dm.enq(x);
 251             endrule
 252             rule read_synced_response_from_dm;
 253                 sync_response_from_dm.deq;
 254                 tap.response_from_dm(sync_response_from_dm.first);
 255             endrule
 256         `endif
 257         /*============================================================ */
 258
 259         `ifdef FlexBus
 260             //rule drive_flexbus_inputs;
 261                //flexbus.flexbus_side.m_TAn(1'b1);
 262                //flexbus.flexbus_side.m_din(32'haaaaaaaa);
 263             //endrule
 264          `endif
 265
 266         `ifdef CLINT
 267             SyncBitIfc#(Bit#(1)) clint_mtip_int <-
 268                                         mkSyncBitToCC(slow_clock,slow_reset);
 269             SyncBitIfc#(Bit#(1)) clint_msip_int <-
 270                                         mkSyncBitToCC(slow_clock,slow_reset);
 271             Reg#(Bit#(`DATA)) clint_mtime_value <-
 272                                         mkSyncRegToCC(0,slow_clock,slow_reset);
 273             rule synchronize_clint_data;
 274                 clint_mtip_int.send(slow_peripherals.mtip_int);
 275                 clint_msip_int.send(slow_peripherals.msip_int);
 276                 clint_mtime_value<=slow_peripherals.mtime;
 277             endrule
 278             rule connect_msip_mtip_from_clint;
 279                 core.clint_msip(clint_msip_int.read);
 280                 core.clint_mtip(clint_mtip_int.read);
 281             core.clint_mtime(clint_mtime_value);
 282             endrule
 283         `endif
 284         `ifdef PLIC
 285             Reg#(Tuple2#(Bool,Bool)) plic_interrupt_note <-
 286                                         mkSyncRegToCC(tuple2(False,False),
 287                                                       slow_clock,slow_reset);
 288             rule synchronize_interrupts;
 289                 let note <- slow_peripherals.intrpt_note;
 290                 plic_interrupt_note<=note;
 291             endrule
 292             rule rl_send_external_interrupt_to_csr;
 293                 core.set_external_interrupt(plic_interrupt_note);
 294             endrule
 295         `endif
 296
 297         `ifdef VME
 298             interface  proc_ifc = vme.proc_ifc;
 299             interface   proc_dbus = vme.proc_dbus;
 300         `endif
 301          method Action boot_sequence(Bit#(1) bootseq) =
 302                             core.boot_sequence(bootseq);
 303         `ifdef SDRAM
 304             interface sdram_out=sdram.ifc_sdram_out;
 305         `endif
 306         `ifdef DDR
 307           interface master=fabric.v_to_slaves
 308                                 [fromInteger(valueOf(Sdram_slave_num))];
 309         `endif
 310         interface slow_ios=slow_peripherals.slow_ios;
 311 {6}
 312     endmodule
 313 endpackage