src/bsv/bsv_lib/soc_template.bsv

   1 /*
   2 Copyright (c) 2013, IIT Madras
   3 All rights reserved.
   4
   5 Redistribution and use in source and binary forms, with or without
   6 modification, are permitted provided that the following conditions
   7 are met:
   8
   9 *  Redistributions of source code must retain the above copyright notice,
  10    this list of conditions and the following disclaimer.
  11 *  Redistributions in binary form must reproduce the above copyright
  12    notice, this list of conditions and the following disclaimer in the
  13    documentation and/or other materials provided with the distribution.
  14 *  Neither the name of IIT Madras  nor the names of its contributors
  15    may be used to endorse or promote products derived from this software
  16    without specific prior written permission.
  17
  18 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  19 "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  20 LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  21 A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  22 HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  23 SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
  24 TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
  25 PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
  26 LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
  27 NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  28 SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  29 -------------------------------------------------------------------
  30 */
  31 package Soc;
  32     /*====== Package imports === */
  33     import FIFO::*;
  34     import FIFOF::*;
  35     import SpecialFIFOs::*;
  36     import GetPut::*;
  37     import ClientServer::*;
  38     import Vector::*;
  39     import Connectable::*;
  40     import Clocks::*;
  41     /*========================== */
  42     /*=== Project imports === */
  43     import ConcatReg::*;
  44     import AXI4_Types::*;
  45     import AXI4_Fabric::*;
  46     import defined_types::*;
  47     import MemoryMap             :: *;
  48     import slow_peripherals::*;
  49     `include "defines.bsv"
  50     `include "instance_defines.bsv"
  51 {8}
  52     /*====== AXI4 slave declarations =======*/
  53 {3}
  54     /*====== AXI4 Master declarations =======*/
  55 {4}
  56
  57
  58     `ifdef DMA
  59         import DMA                               :: *;
  60     `endif
  61     `ifdef BOOTROM
  62         import BootRom                  ::*;
  63     `endif
  64     `ifdef SDRAM
  65         import sdr_top                   :: *;
  66     `endif
  67     `ifdef BRAM
  68         import Memory_AXI4      ::*;
  69     `endif
  70     `ifdef TCMemory
  71         import TCM::*;
  72     `endif
  73     `ifdef Debug
  74         import DebugModule::*;
  75     `else
  76         import core::*;
  77     `endif
  78     `ifdef  VME
  79         import vme_top ::*;
  80     `endif
  81
  82     `ifdef VME
  83         import vme_master::*;
  84     `endif
  85     `ifdef FlexBus
  86         import FlexBus_Types::*;
  87     `endif
  88 {0}
  89
  90     /*========================= */
  91     interface Ifc_Soc;
  92         interface SP_ios slow_ios;
  93         (*always_ready,always_enabled*)
  94         method Action boot_sequence(Bit#(1) bootseq);
  95
  96         `ifdef SDRAM
  97             (*always_ready*) interface Ifc_sdram_out sdram_out;
  98         `endif
  99         ifdef DDR
 100             (*prefix="M_AXI"*) interface
 101                    AXI4_Master_IFC#(`PADDR, `Reg_width, `USERSPACE) master;
 102         `endif
 103         `ifdef HYPER
 104              (*always_ready,always_enabled*)
 105              interface Ifc_flash ifc_flash;
 106         `endif
 107         /*=============================================== */
 108         `ifdef VME
 109              interface Vme_out  proc_ifc;
 110              interface Data_bus_inf proc_dbus;
 111         `endif
 112         `ifdef FlexBus
 113              interface FlexBus_Master_IFC flexbus_out;
 114         `endif
 115 {1}
 116     endinterface
 117
 118     (*synthesize*)
 119     module mkSoc #(Bit#(`VADDR) reset_vector,
 120                  Clock slow_clock, Reset slow_reset, Clock uart_clock,
 121                  Reset uart_reset, Clock clk0, Clock tck, Reset trst
 122                  `ifdef PWM_AXI4Lite ,Clock ext_pwm_clock `endif )(Ifc_Soc);
 123         Clock core_clock <-exposeCurrentClock; // slow peripheral clock
 124         Reset core_reset <-exposeCurrentReset; // slow peripheral reset
 125 {2}
 126         `ifdef Debug
 127             Ifc_DebugModule core<-mkDebugModule(reset_vector);
 128         `else
 129             Ifc_core_AXI4 core <-mkcore_AXI4(reset_vector);
 130         `endif
 131         `ifdef BOOTROM
 132             BootRom_IFC bootrom <-mkBootRom;
 133         `endif
 134         `ifdef SDRAM
 135             Ifc_sdr_slave sdram<- mksdr_axi4_slave(clk0);
 136         `endif
 137         `ifdef BRAM
 138             Memory_IFC#(`SDRAMMemBase,`Addr_space)main_memory <-
 139                         mkMemory("code.mem.MSB","code.mem.LSB","MainMEM");
 140         `endif
 141         `ifdef TCMemory
 142             Ifc_TCM                                     tcm                             <- mkTCM;
 143         `endif
 144         `ifdef DMA
 145             DmaC#(7,`NUM_DMACHANNELS) dma       <- mkDMA();
 146         `endif
 147             `ifdef VME
 148             Ifc_vme_top             vme             <-mkvme_top();
 149             `endif
 150         `ifdef FlexBus
 151             AXI4_Slave_to_FlexBus_Master_Xactor_IFC #(32, 64,0)
 152                             flexbus <- mkAXI4_Slave_to_FlexBus_Master_Xactor;
 153         `endif
 154         Ifc_slow_peripherals slow_peripherals <-mkslow_peripherals(
 155                           core_clock, core_reset, uart_clock,
 156                           uart_reset, clocked_by slow_clock ,
 157                           reset_by slow_reset
 158                           `ifdef PWM_AXI4Lite , ext_pwm_clock `endif );
 159
 160         // Fabric
 161         AXI4_Fabric_IFC #(Num_Masters, Num_Slaves,
 162                           `PADDR, `Reg_width,`USERSPACE)
 163                         fabric <- mkAXI4_Fabric(fn_addr_to_slave_num);
 164
 165         // Connect traffic generators to fabric
 166         mkConnection (core.dmem_master,fabric.v_from_masters
 167                               [fromInteger(valueOf(Dmem_master_num))]);
 168         mkConnection (core.imem_master, fabric.v_from_masters
 169                               [fromInteger(valueOf(Imem_master_num))]);
 170         `ifdef Debug
 171             mkConnection (core.debug_master, fabric.v_from_masters
 172                               [fromInteger(valueOf(Debug_master_num))]);
 173         `endif
 174         `ifdef DMA
 175          mkConnection (dma.mmu, fabric.v_from_masters
 176                               [fromInteger(valueOf(DMA_master_num))]);
 177         `endif
 178
 179
 180         // Connect fabric to memory slaves
 181             `ifdef Debug
 182                 mkConnection (fabric.v_to_slaves
 183                               [fromInteger(valueOf(Debug_slave_num))],
 184                               core.debug_slave);
 185             `endif
 186             `ifdef SDRAM
 187                 mkConnection (fabric.v_to_slaves
 188                               [fromInteger(valueOf(Sdram_slave_num))],
 189                               sdram.axi4_slave_sdram); //
 190             mkConnection (fabric.v_to_slaves
 191                               [fromInteger(valueOf(Sdram_cfg_slave_num))],
 192                               sdram.axi4_slave_cntrl_reg); //
 193       `endif
 194       `ifdef BRAM
 195                 mkConnection(fabric.v_to_slaves
 196                               [fromInteger(valueOf(Sdram_slave_num))],
 197                               main_memory.axi_slave);
 198             `endif
 199             `ifdef BOOTROM
 200                 mkConnection (fabric.v_to_slaves
 201                               [fromInteger(valueOf(BootRom_slave_num))],
 202                               bootrom.axi_slave);
 203             `endif
 204             `ifdef DMA
 205             mkConnection (fabric.v_to_slaves
 206                               [fromInteger(valueOf(Dma_slave_num))],
 207                               dma.cfg); //DMA slave
 208             `endif
 209             `ifdef TCMemory
 210                 mkConnection (fabric.v_to_slaves
 211                               [fromInteger(valueOf(TCM_slave_num))],
 212                               tcm.axi_slave);
 213             `endif
 214             mkConnection(fabric.v_to_slaves
 215                               [fromInteger(valueOf(SlowPeripheral_slave_num))],
 216                               slow_peripherals.axi_slave);
 217             `ifdef VME
 218                 mkConnection (fabric.v_to_slaves
 219                               [fromInteger(valueOf(VME_slave_num))],
 220                               vme.slave_axi_vme);
 221             `endif
 222             `ifdef FlexBus
 223                 mkConnection (fabric.v_to_slaves
 224                               [fromInteger(valueOf(FlexBus_slave_num))],
 225                               flexbus.axi_side);
 226             `endif
 227
 228             // fabric connections
 229 {5}
 230
 231             `ifdef DMA
 232             // rule to connect all interrupt lines to the DMA
 233             // All the interrupt lines to DMA are active
 234             // HIGH. For peripherals that are not connected,
 235             // or those which do not
 236             // generate an interrupt (like TCM), drive a constant 1
 237             // on the corresponding interrupt line.
 238 {7}
 239             `endif
 240
 241
 242         /*==== Synchornization between the JTAG and the Debug Module ===== */
 243         `ifdef Debug
 244             SyncFIFOIfc#(Bit#(40)) sync_request_to_dm <-
 245                                         mkSyncFIFOToCC(1,tck,trst);
 246             SyncFIFOIfc#(Bit#(34)) sync_response_from_dm <-
 247                                         mkSyncFIFOFromCC(1,tck);
 248             rule connect_tap_request_to_syncfifo;
 249                 let x<-tap.request_to_dm;
 250                 sync_request_to_dm.enq(x);
 251             endrule
 252             rule read_synced_request_to_dm;
 253                 sync_request_to_dm.deq;
 254                 core.request_from_dtm(sync_request_to_dm.first);
 255             endrule
 256
 257             rule connect_debug_response_to_syncfifo;
 258                 let x<-core.response_to_dtm;
 259                 sync_response_from_dm.enq(x);
 260             endrule
 261             rule read_synced_response_from_dm;
 262                 sync_response_from_dm.deq;
 263                 tap.response_from_dm(sync_response_from_dm.first);
 264             endrule
 265         `endif
 266         /*============================================================ */
 267
 268         `ifdef FlexBus
 269             //rule drive_flexbus_inputs;
 270                //flexbus.flexbus_side.m_TAn(1'b1);
 271                //flexbus.flexbus_side.m_din(32'haaaaaaaa);
 272             //endrule
 273          `endif
 274
 275         `ifdef CLINT
 276             SyncBitIfc#(Bit#(1)) clint_mtip_int <-
 277                                         mkSyncBitToCC(slow_clock,slow_reset);
 278             SyncBitIfc#(Bit#(1)) clint_msip_int <-
 279                                         mkSyncBitToCC(slow_clock,slow_reset);
 280             Reg#(Bit#(`Reg_width)) clint_mtime_value <-
 281                                         mkSyncRegToCC(0,slow_clock,slow_reset);
 282             rule synchronize_clint_data;
 283                 clint_mtip_int.send(slow_peripherals.mtip_int);
 284                 clint_msip_int.send(slow_peripherals.msip_int);
 285                 clint_mtime_value<=slow_peripherals.mtime;
 286             endrule
 287             rule connect_msip_mtip_from_clint;
 288                 core.clint_msip(clint_msip_int.read);
 289                 core.clint_mtip(clint_mtip_int.read);
 290             core.clint_mtime(clint_mtime_value);
 291             endrule
 292         `endif
 293         `ifdef PLIC
 294             Reg#(Tuple2#(Bool,Bool)) plic_interrupt_note <-
 295                                         mkSyncRegToCC(tuple2(False,False),
 296                                                       slow_clock,slow_reset);
 297             rule synchronize_interrupts;
 298                 let note <- slow_peripherals.intrpt_note;
 299                 plic_interrupt_note<=note;
 300             endrule
 301             rule rl_send_external_interrupt_to_csr;
 302                 core.set_external_interrupt(plic_interrupt_note);
 303             endrule
 304         `endif
 305
 306         `ifdef VME
 307             interface  proc_ifc = vme.proc_ifc;
 308             interface   proc_dbus = vme.proc_dbus;
 309         `endif
 310         `ifdef FlexBus
 311             interface flexbus_out = flexbus.flexbus_side;
 312         `endif
 313          method Action boot_sequence(Bit#(1) bootseq) =
 314                             core.boot_sequence(bootseq);
 315         `ifdef SDRAM
 316             interface sdram_out=sdram.ifc_sdram_out;
 317         `endif
 318         `ifdef DDR
 319           interface master=fabric.v_to_slaves
 320                                 [fromInteger(valueOf(Sdram_slave_num))];
 321         `endif
 322         interface slow_ios=slow_peripherals.slow_ios;
 323 {6}
 324     endmodule
 325 endpackage