src/bsv/bsv_lib/soc_template.bsv

   1 /*
   2 Copyright (c) 2013, IIT Madras
   3 All rights reserved.
   4
   5 Redistribution and use in source and binary forms, with or without
   6 modification, are permitted provided that the following conditions
   7 are met:
   8
   9 *  Redistributions of source code must retain the above copyright notice,
  10    this list of conditions and the following disclaimer.
  11 *  Redistributions in binary form must reproduce the above copyright
  12    notice, this list of conditions and the following disclaimer in the
  13    documentation and/or other materials provided with the distribution.
  14 *  Neither the name of IIT Madras  nor the names of its contributors
  15    may be used to endorse or promote products derived from this software
  16    without specific prior written permission.
  17
  18 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  19 "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  20 LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  21 A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  22 HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  23 SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
  24 TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
  25 PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
  26 LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
  27 NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  28 SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  29 -------------------------------------------------------------------
  30 */
  31 package soc;
  32     /*====== Package imports === */
  33     import FIFO::*;
  34     import FIFOF::*;
  35     import SpecialFIFOs::*;
  36     import GetPut::*;
  37     import ClientServer::*;
  38     import Vector::*;
  39     import Connectable::*;
  40     import Clocks::*;
  41     /*========================== */
  42 {10}
  43     /*=== Project imports === */
  44     import ConcatReg::*;
  45     import AXI4_Types::*;
  46     import AXI4_Fabric::*;
  47     import defined_types::*;
  48     import MemoryMap             :: *;
  49     import slow_peripherals::*;
  50 `ifdef DEBUG
  51     `include "defines.bsv"
  52 `endif
  53     `include "instance_defines.bsv"
  54     `include "core_parameters.bsv"
  55 {8}
  56     /*====== AXI4 slave declarations =======*/
  57 {3}
  58     /*====== AXI4 Master declarations =======*/
  59 {4}
  60
  61
  62     `ifdef DMA
  63         import DMA                               :: *;
  64     `endif
  65     `ifdef BOOTROM
  66         import BootRom                  ::*;
  67     `endif
  68     `ifdef SDRAM
  69         import sdr_top                   :: *;
  70     `endif
  71     `ifdef BRAM
  72         import Memory_AXI4      ::*;
  73     `endif
  74     `ifdef TCMemory
  75         import TCM::*;
  76     `endif
  77     `ifdef Debug
  78         import DebugModule::*;
  79     `else
  80         import core::*;
  81     `endif
  82     `ifdef  VME
  83         import vme_top ::*;
  84     `endif
  85
  86     `ifdef VME
  87         import vme_master::*;
  88     `endif
  89     `ifdef FlexBus
  90         import FlexBus_Types::*;
  91     `endif
  92 {0}
  93
  94     /*========================= */
  95     interface Ifc_Soc;
  96         interface SP_ios slow_ios;
  97         (*always_ready,always_enabled*)
  98         method Action boot_sequence(Bit#(1) bootseq);
  99
 100         `ifdef SDRAM
 101             (*always_ready*) interface Ifc_sdram_out sdram_out;
 102         `endif
 103         `ifdef DDR
 104             (*prefix="M_AXI"*) interface
 105                    AXI4_Master_IFC#(`ADDR, `DATA, `USERSPACE) master;
 106         `endif
 107         `ifdef HYPER
 108              (*always_ready,always_enabled*)
 109              interface Ifc_flash ifc_flash;
 110         `endif
 111         /*=============================================== */
 112         `ifdef VME
 113              interface Vme_out  proc_ifc;
 114              interface Data_bus_inf proc_dbus;
 115         `endif
 116 {1}
 117     endinterface
 118
 119 function FastTuple2 #(Bool, Bit#(TLog#(Num_Slaves)))
 120                 fn_addr_to_slave_num  (Bit#(`PADDR) addr);
 121
 122     if(addr>=`SDRAMMemBase && addr<=`SDRAMMemEnd)
 123         return tuple2(True,fromInteger(valueOf(Sdram_slave_num)));
 124     else if(addr>=`DebugBase && addr<=`DebugEnd)
 125         return tuple2(True,fromInteger(valueOf(Debug_slave_num)));
 126     `ifdef SDRAM
 127         else if(addr>=`SDRAMCfgBase && addr<=`SDRAMCfgEnd )
 128             return tuple2(True,fromInteger(valueOf(Sdram_cfg_slave_num)));
 129     `endif
 130     `ifdef BOOTROM
 131         else if(addr>=`BootRomBase && addr<=`BootRomEnd)
 132             return tuple2(True,fromInteger(valueOf(BootRom_slave_num)));
 133     `endif
 134     `ifdef DMA
 135         else if(addr>=`DMABase && addr<=`DMAEnd)
 136             return tuple2(True,fromInteger(valueOf(Dma_slave_num)));
 137     `endif
 138     `ifdef VME
 139         else if(addr>=`VMEBase && addr<=`VMEEnd)
 140             return tuple2(True,fromInteger(valueOf(VME_slave_num)));
 141     `endif
 142     `ifdef TCMemory
 143         else if(addr>=`TCMBase && addr<=`TCMEnd)
 144             return tuple2(True,fromInteger(valueOf(TCM_slave_num)));
 145     `endif
 146         else
 147 {11}
 148             return tuple2(False,?);
 149 endfunction
 150
 151
 152     (*synthesize*)
 153     module mkSoc #(Bit#(`VADDR) reset_vector,
 154                  Clock slow_clock, Reset slow_reset, Clock uart_clock,
 155                  Reset uart_reset, Clock clk0, Clock tck, Reset trst
 156                  `ifdef PWM_AXI4Lite ,Clock ext_pwm_clock `endif )(Ifc_Soc);
 157         Clock core_clock <-exposeCurrentClock; // slow peripheral clock
 158         Reset core_reset <-exposeCurrentReset; // slow peripheral reset
 159 {2}
 160         `ifdef Debug
 161             Ifc_DebugModule core<-mkDebugModule(reset_vector);
 162         `else
 163             Ifc_core_AXI4 core <-mkcore_AXI4(reset_vector);
 164         `endif
 165         `ifdef BOOTROM
 166             BootRom_IFC bootrom <-mkBootRom;
 167         `endif
 168         `ifdef SDRAM
 169             Ifc_sdr_slave sdram<- mksdr_axi4_slave(clk0);
 170         `endif
 171         `ifdef BRAM
 172             Memory_IFC#(`SDRAMMemBase,`Addr_space)main_memory <-
 173                         mkMemory("code.mem.MSB","code.mem.LSB","MainMEM");
 174         `endif
 175         `ifdef TCMemory
 176             Ifc_TCM                                     tcm                             <- mkTCM;
 177         `endif
 178         `ifdef DMA
 179             DmaC#(7,`NUM_DMACHANNELS) dma       <- mkDMA();
 180         `endif
 181             `ifdef VME
 182             Ifc_vme_top             vme             <-mkvme_top();
 183             `endif
 184         Ifc_slow_peripherals slow_peripherals <-mkslow_peripherals(
 185                           core_clock, core_reset, uart_clock,
 186                           uart_reset, clocked_by slow_clock ,
 187                           reset_by slow_reset
 188                           `ifdef PWM_AXI4Lite , ext_pwm_clock `endif );
 189
 190         // Fabric
 191         AXI4_Fabric_IFC #(Num_Masters, Num_Slaves,
 192                           `ADDR, `DATA,`USERSPACE)
 193                         fabric <- mkAXI4_Fabric(fn_addr_to_slave_num);
 194
 195         // Connect traffic generators to fabric
 196         mkConnection (core.dmem_master,fabric.v_from_masters
 197                               [fromInteger(valueOf(Dmem_master_num))]);
 198         mkConnection (core.imem_master, fabric.v_from_masters
 199                               [fromInteger(valueOf(Imem_master_num))]);
 200         `ifdef Debug
 201             mkConnection (core.debug_master, fabric.v_from_masters
 202                               [fromInteger(valueOf(Debug_master_num))]);
 203         `endif
 204         `ifdef DMA
 205          mkConnection (dma.mmu, fabric.v_from_masters
 206                               [fromInteger(valueOf(DMA_master_num))]);
 207         `endif
 208
 209
 210         // Connect fabric to memory slaves
 211             `ifdef Debug
 212                 mkConnection (fabric.v_to_slaves
 213                               [fromInteger(valueOf(Debug_slave_num))],
 214                               core.debug_slave);
 215             `endif
 216             `ifdef SDRAM
 217                 mkConnection (fabric.v_to_slaves
 218                               [fromInteger(valueOf(Sdram_slave_num))],
 219                               sdram.axi4_slave_sdram); //
 220             mkConnection (fabric.v_to_slaves
 221                               [fromInteger(valueOf(Sdram_cfg_slave_num))],
 222                               sdram.axi4_slave_cntrl_reg); //
 223       `endif
 224       `ifdef BRAM
 225                 mkConnection(fabric.v_to_slaves
 226                               [fromInteger(valueOf(Sdram_slave_num))],
 227                               main_memory.axi_slave);
 228             `endif
 229             `ifdef BOOTROM
 230                 mkConnection (fabric.v_to_slaves
 231                               [fromInteger(valueOf(BootRom_slave_num))],
 232                               bootrom.axi_slave);
 233             `endif
 234             `ifdef DMA
 235             mkConnection (fabric.v_to_slaves
 236                               [fromInteger(valueOf(Dma_slave_num))],
 237                               dma.cfg); //DMA slave
 238             `endif
 239             `ifdef TCMemory
 240                 mkConnection (fabric.v_to_slaves
 241                               [fromInteger(valueOf(TCM_slave_num))],
 242                               tcm.axi_slave);
 243             `endif
 244             mkConnection(fabric.v_to_slaves
 245                               [fromInteger(valueOf(SlowPeripheral_slave_num))],
 246                               slow_peripherals.axi_slave);
 247             `ifdef VME
 248                 mkConnection (fabric.v_to_slaves
 249                               [fromInteger(valueOf(VME_slave_num))],
 250                               vme.slave_axi_vme);
 251             `endif
 252
 253 //          pin connections
 254 {9}
 255
 256             // fabric connections
 257 {5}
 258
 259             `ifdef DMA
 260             // rule to connect all interrupt lines to the DMA
 261             // All the interrupt lines to DMA are active
 262             // HIGH. For peripherals that are not connected,
 263             // or those which do not
 264             // generate an interrupt (like TCM), drive a constant 1
 265             // on the corresponding interrupt line.
 266 {7}
 267             `endif
 268
 269
 270         /*==== Synchornization between the JTAG and the Debug Module ===== */
 271         `ifdef Debug
 272             SyncFIFOIfc#(Bit#(40)) sync_request_to_dm <-
 273                                         mkSyncFIFOToCC(1,tck,trst);
 274             SyncFIFOIfc#(Bit#(34)) sync_response_from_dm <-
 275                                         mkSyncFIFOFromCC(1,tck);
 276             rule connect_tap_request_to_syncfifo;
 277                 let x<-tap.request_to_dm;
 278                 sync_request_to_dm.enq(x);
 279             endrule
 280             rule read_synced_request_to_dm;
 281                 sync_request_to_dm.deq;
 282                 core.request_from_dtm(sync_request_to_dm.first);
 283             endrule
 284
 285             rule connect_debug_response_to_syncfifo;
 286                 let x<-core.response_to_dtm;
 287                 sync_response_from_dm.enq(x);
 288             endrule
 289             rule read_synced_response_from_dm;
 290                 sync_response_from_dm.deq;
 291                 tap.response_from_dm(sync_response_from_dm.first);
 292             endrule
 293         `endif
 294         /*============================================================ */
 295
 296         `ifdef FlexBus
 297             //rule drive_flexbus_inputs;
 298                //flexbus.flexbus_side.m_TAn(1'b1);
 299                //flexbus.flexbus_side.m_din(32'haaaaaaaa);
 300             //endrule
 301          `endif
 302
 303         `ifdef CLINT
 304             SyncBitIfc#(Bit#(1)) clint_mtip_int <-
 305                                         mkSyncBitToCC(slow_clock,slow_reset);
 306             SyncBitIfc#(Bit#(1)) clint_msip_int <-
 307                                         mkSyncBitToCC(slow_clock,slow_reset);
 308             Reg#(Bit#(`DATA)) clint_mtime_value <-
 309                                         mkSyncRegToCC(0,slow_clock,slow_reset);
 310             rule synchronize_clint_data;
 311                 clint_mtip_int.send(slow_peripherals.mtip_int);
 312                 clint_msip_int.send(slow_peripherals.msip_int);
 313                 clint_mtime_value<=slow_peripherals.mtime;
 314             endrule
 315             rule connect_msip_mtip_from_clint;
 316                 core.clint_msip(clint_msip_int.read);
 317                 core.clint_mtip(clint_mtip_int.read);
 318             core.clint_mtime(clint_mtime_value);
 319             endrule
 320         `endif
 321         `ifdef PLIC
 322             Reg#(Tuple2#(Bool,Bool)) plic_interrupt_note <-
 323                                         mkSyncRegToCC(tuple2(False,False),
 324                                                       slow_clock,slow_reset);
 325             rule synchronize_interrupts;
 326                 let note <- slow_peripherals.intrpt_note;
 327                 plic_interrupt_note<=note;
 328             endrule
 329             rule rl_send_external_interrupt_to_csr;
 330                 core.set_external_interrupt(plic_interrupt_note);
 331             endrule
 332         `endif
 333
 334         `ifdef VME
 335             interface  proc_ifc = vme.proc_ifc;
 336             interface   proc_dbus = vme.proc_dbus;
 337         `endif
 338          method Action boot_sequence(Bit#(1) bootseq) =
 339                             core.boot_sequence(bootseq);
 340         `ifdef SDRAM
 341             interface sdram_out=sdram.ifc_sdram_out;
 342         `endif
 343         `ifdef DDR
 344           interface master=fabric.v_to_slaves
 345                                 [fromInteger(valueOf(Sdram_slave_num))];
 346         `endif
 347         interface slow_ios=slow_peripherals.slow_ios;
 348 {6}
 349     endmodule
 350 endpackage