src/bsv/bsv_lib/soc_template.bsv

   1 /*
   2 Copyright (c) 2013, IIT Madras
   3 All rights reserved.
   4
   5 Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
   6
   7 *  Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
   8 *  Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
   9 *  Neither the name of IIT Madras  nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.
  10
  11 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  12 ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
  13 */
  14 package Soc;
  15         /*====== Package imports === */
  16         import FIFO::*;
  17         import FIFOF::*;
  18         import SpecialFIFOs::*;
  19         import GetPut::*;
  20         import ClientServer::*;
  21         import Vector::*;
  22         import Connectable::*;
  23         import Clocks::*;
  24         /*========================== */
  25         /*=== Project imports === */
  26         import ConcatReg::*;
  27         import AXI4_Types::*;
  28         import AXI4_Fabric::*;
  29         import defined_types::*;
  30         import MemoryMap                 :: *;
  31         import slow_peripherals::*;
  32         `include "defines.bsv"
  33         `include "instance_defines.bsv"
  34 {8}
  35     /*====== AXI4 slave declarations =======*/
  36 {3}
  37     /*====== AXI4 Master declarations =======*/
  38 {4}
  39
  40
  41                 `ifdef DMA
  42                         import DMA                               :: *;
  43                 `endif
  44                 `ifdef BOOTROM
  45                         import BootRom                  ::*;
  46                 `endif
  47                 `ifdef SDRAM
  48                         import sdr_top                   :: *;
  49     `endif
  50                 `ifdef BRAM
  51                         import Memory_AXI4      ::*;
  52                 `endif
  53                 `ifdef TCMemory
  54                         import TCM::*;
  55                 `endif
  56                 `ifdef Debug
  57                         import jtagdtm::*;
  58                         import DebugModule::*;
  59                 `else
  60                         import core::*;
  61                 `endif
  62 `ifdef  VME
  63                         import vme_top ::*;
  64 `endif
  65
  66 `ifdef VME
  67                         import vme_master::*;
  68 `endif
  69 `ifdef FlexBus
  70             import FlexBus_Types::*;
  71 `endif
  72 {0}
  73
  74         /*========================= */
  75         interface Ifc_Soc;
  76                 interface SP_ios slow_ios;
  77                 (*always_ready,always_enabled*)
  78                 method Action boot_sequence(Bit#(1) bootseq);
  79
  80                   `ifdef SDRAM
  81                         (*always_ready*) interface Ifc_sdram_out sdram_out;
  82                 `endif
  83       `ifdef DDR
  84         (*prefix="M_AXI"*) interface
  85                 AXI4_Master_IFC#(`PADDR, `Reg_width, `USERSPACE) master;
  86       `endif
  87                 `ifdef HYPER
  88                         (*always_ready,always_enabled*)
  89                    interface Ifc_flash ifc_flash;
  90                 `endif
  91         /*=============================================== */
  92            `ifdef VME
  93                         interface Vme_out  proc_ifc;
  94                         interface Data_bus_inf proc_dbus;
  95                 `endif
  96         `ifdef FlexBus
  97             interface FlexBus_Master_IFC flexbus_out;
  98         `endif
  99 {1}
 100         endinterface
 101         (*synthesize*)
 102         module mkSoc #(Bit#(`VADDR) reset_vector,
 103                  Clock slow_clock, Reset slow_reset, Clock uart_clock,
 104                  Reset uart_reset, Clock clk0, Clock tck, Reset trst
 105                  `ifdef PWM_AXI4Lite ,Clock ext_pwm_clock `endif )(Ifc_Soc);
 106                 Clock core_clock <-exposeCurrentClock; // slow peripheral clock
 107                 Reset core_reset <-exposeCurrentReset; // slow peripheral reset
 108 {2}
 109       `ifdef Debug
 110                         Ifc_DebugModule core<-mkDebugModule(reset_vector);
 111                 `else
 112                         Ifc_core_AXI4 core <-mkcore_AXI4(reset_vector);
 113                 `endif
 114                 `ifdef BOOTROM
 115                         BootRom_IFC bootrom <-mkBootRom;
 116                 `endif
 117                 `ifdef SDRAM
 118                         Ifc_sdr_slave sdram<- mksdr_axi4_slave(clk0);
 119                 `endif
 120     `ifdef BRAM
 121                         Memory_IFC#(`SDRAMMemBase,`Addr_space)main_memory <-
 122                         mkMemory("code.mem.MSB","code.mem.LSB","MainMEM");
 123                 `endif
 124                 `ifdef TCMemory
 125                         Ifc_TCM                                 tcm                             <- mkTCM;
 126                 `endif
 127                 `ifdef DMA
 128                         DmaC#(7,`NUM_DMACHANNELS) dma   <- mkDMA();
 129                 `endif
 130                         `ifdef VME
 131                         Ifc_vme_top             vme             <-mkvme_top();
 132                         `endif
 133         `ifdef FlexBus
 134             AXI4_Slave_to_FlexBus_Master_Xactor_IFC #(32, 64,0)
 135                             flexbus <- mkAXI4_Slave_to_FlexBus_Master_Xactor;
 136         `endif
 137                 Ifc_slow_peripherals slow_peripherals <-mkslow_peripherals(
 138           core_clock, core_reset, uart_clock,
 139           uart_reset, clocked_by slow_clock , reset_by slow_reset
 140           `ifdef PWM_AXI4Lite , ext_pwm_clock `endif );
 141
 142         // Fabric
 143         AXI4_Fabric_IFC #(Num_Masters, Num_Slaves, `PADDR, `Reg_width,`USERSPACE)
 144                                 fabric <- mkAXI4_Fabric(fn_addr_to_slave_num);
 145
 146         // Connect traffic generators to fabric
 147         mkConnection (core.dmem_master,fabric.v_from_masters
 148                               [fromInteger(valueOf(Dmem_master_num))]);
 149         mkConnection (core.imem_master, fabric.v_from_masters
 150                               [fromInteger(valueOf(Imem_master_num))]);
 151                 `ifdef Debug
 152                         mkConnection (core.debug_master, fabric.v_from_masters
 153                               [fromInteger(valueOf(Debug_master_num))]);
 154                 `endif
 155                 `ifdef DMA
 156          mkConnection (dma.mmu, fabric.v_from_masters
 157                               [fromInteger(valueOf(DMA_master_num))]);
 158                 `endif
 159
 160
 161                 // Connect fabric to memory slaves
 162                         `ifdef Debug
 163                                 mkConnection (fabric.v_to_slaves
 164                               [fromInteger(valueOf(Debug_slave_num))],
 165                               core.debug_slave);
 166                         `endif
 167                         `ifdef SDRAM
 168                                 mkConnection (fabric.v_to_slaves
 169                               [fromInteger(valueOf(Sdram_slave_num))],
 170                               sdram.axi4_slave_sdram); //
 171                         mkConnection (fabric.v_to_slaves
 172                               [fromInteger(valueOf(Sdram_cfg_slave_num))],
 173                               sdram.axi4_slave_cntrl_reg); //
 174       `endif
 175       `ifdef BRAM
 176                                 mkConnection(fabric.v_to_slaves
 177                               [fromInteger(valueOf(Sdram_slave_num))],
 178                               main_memory.axi_slave);
 179                         `endif
 180                         `ifdef BOOTROM
 181                                 mkConnection (fabric.v_to_slaves
 182                               [fromInteger(valueOf(BootRom_slave_num))],
 183                               bootrom.axi_slave);
 184                         `endif
 185                         `ifdef DMA
 186                         mkConnection (fabric.v_to_slaves
 187                               [fromInteger(valueOf(Dma_slave_num))],
 188                               dma.cfg); //DMA slave
 189                         `endif
 190                         `ifdef TCMemory
 191                                 mkConnection (fabric.v_to_slaves
 192                               [fromInteger(valueOf(TCM_slave_num))],
 193                               tcm.axi_slave);
 194                         `endif
 195                         mkConnection(fabric.v_to_slaves
 196                               [fromInteger(valueOf(SlowPeripheral_slave_num))],
 197                               slow_peripherals.axi_slave);
 198                         `ifdef VME
 199                                 mkConnection (fabric.v_to_slaves
 200                               [fromInteger(valueOf(VME_slave_num))],
 201                               vme.slave_axi_vme);
 202                         `endif
 203                         `ifdef FlexBus
 204                                 mkConnection (fabric.v_to_slaves
 205                               [fromInteger(valueOf(FlexBus_slave_num))],
 206                               flexbus.axi_side);
 207                         `endif
 208
 209 // fabric connections
 210 {5}
 211
 212                         `ifdef DMA
 213                         // rule to connect all interrupt lines to the DMA
 214                         // All the interrupt lines to DMA are active
 215                         // HIGH. For peripherals that are not connected,
 216                         // or those which do not
 217                         // generate an interrupt (like TCM), drive a constant 1
 218             // on the corresponding interrupt line.
 219 {7}
 220                         `endif
 221
 222
 223                 /*==== Synchornization between the JTAG and the Debug Module ===== */
 224                 `ifdef Debug
 225                         SyncFIFOIfc#(Bit#(40)) sync_request_to_dm <-
 226                                         mkSyncFIFOToCC(1,tck,trst);
 227                         SyncFIFOIfc#(Bit#(34)) sync_response_from_dm <-
 228                                         mkSyncFIFOFromCC(1,tck);
 229                         rule connect_tap_request_to_syncfifo;
 230                                 let x<-tap.request_to_dm;
 231                                 sync_request_to_dm.enq(x);
 232                         endrule
 233                         rule read_synced_request_to_dm;
 234                                 sync_request_to_dm.deq;
 235                                 core.request_from_dtm(sync_request_to_dm.first);
 236                         endrule
 237
 238                         rule connect_debug_response_to_syncfifo;
 239                                 let x<-core.response_to_dtm;
 240                                 sync_response_from_dm.enq(x);
 241                         endrule
 242                         rule read_synced_response_from_dm;
 243                                 sync_response_from_dm.deq;
 244                                 tap.response_from_dm(sync_response_from_dm.first);
 245                         endrule
 246                 `endif
 247                 /*============================================================ */
 248
 249         `ifdef FlexBus
 250             //rule drive_flexbus_inputs;
 251                //flexbus.flexbus_side.m_TAn(1'b1);
 252                //flexbus.flexbus_side.m_din(32'haaaaaaaa);
 253             //endrule
 254          `endif
 255
 256                 `ifdef CLINT
 257                         SyncBitIfc#(Bit#(1)) clint_mtip_int <-
 258                                         mkSyncBitToCC(slow_clock,slow_reset);
 259                         SyncBitIfc#(Bit#(1)) clint_msip_int <-
 260                                         mkSyncBitToCC(slow_clock,slow_reset);
 261                         Reg#(Bit#(`Reg_width)) clint_mtime_value <-
 262                                         mkSyncRegToCC(0,slow_clock,slow_reset);
 263                         rule synchronize_clint_data;
 264                                 clint_mtip_int.send(slow_peripherals.mtip_int);
 265                                 clint_msip_int.send(slow_peripherals.msip_int);
 266                                 clint_mtime_value<=slow_peripherals.mtime;
 267                         endrule
 268                         rule connect_msip_mtip_from_clint;
 269                                 core.clint_msip(clint_msip_int.read);
 270                                 core.clint_mtip(clint_mtip_int.read);
 271             core.clint_mtime(clint_mtime_value);
 272                         endrule
 273                 `endif
 274                 `ifdef PLIC
 275                         Reg#(Tuple2#(Bool,Bool)) plic_interrupt_note <-
 276                                         mkSyncRegToCC(tuple2(False,False),
 277                                                       slow_clock,slow_reset);
 278                         rule synchronize_interrupts;
 279                                 let note <- slow_peripherals.intrpt_note;
 280                                 plic_interrupt_note<=note;
 281                         endrule
 282          rule rl_send_external_interrupt_to_csr;
 283                                 core.set_external_interrupt(plic_interrupt_note);
 284                         endrule
 285                 `endif
 286
 287                 `ifdef VME
 288                         interface  proc_ifc = vme.proc_ifc;
 289                         interface   proc_dbus = vme.proc_dbus;
 290                 `endif
 291                 `ifdef FlexBus
 292             interface flexbus_out = flexbus.flexbus_side;
 293                 `endif
 294       method Action boot_sequence(Bit#(1) bootseq) =
 295                             core.boot_sequence(bootseq);
 296                 `ifdef SDRAM
 297                         interface sdram_out=sdram.ifc_sdram_out;
 298                 `endif
 299     `ifdef DDR
 300       interface master=fabric.v_to_slaves
 301                             [fromInteger(valueOf(Sdram_slave_num))];
 302     `endif
 303                 interface slow_ios=slow_peripherals.slow_ios;
 304 {6}
 305         endmodule
 306 endpackage