src/bsv/bsv_lib/soc_template.bsv

   1 /*
   2 Copyright (c) 2013, IIT Madras
   3 All rights reserved.
   4
   5 Redistribution and use in source and binary forms, with or without
   6 modification, are permitted provided that the following conditions
   7 are met:
   8
   9 *  Redistributions of source code must retain the above copyright notice,
  10    this list of conditions and the following disclaimer.
  11 *  Redistributions in binary form must reproduce the above copyright
  12    notice, this list of conditions and the following disclaimer in the
  13    documentation and/or other materials provided with the distribution.
  14 *  Neither the name of IIT Madras  nor the names of its contributors
  15    may be used to endorse or promote products derived from this software
  16    without specific prior written permission.
  17
  18 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  19 "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  20 LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  21 A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  22 HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  23 SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
  24 TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
  25 PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
  26 LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
  27 NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  28 SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  29 -------------------------------------------------------------------
  30 */
  31 package Soc;
  32     /*====== Package imports === */
  33     import FIFO::*;
  34     import FIFOF::*;
  35     import SpecialFIFOs::*;
  36     import GetPut::*;
  37     import ClientServer::*;
  38     import Vector::*;
  39     import Connectable::*;
  40     import Clocks::*;
  41     /*========================== */
  42 {10}
  43     /*=== Project imports === */
  44     import ConcatReg::*;
  45     import AXI4_Types::*;
  46     import AXI4_Fabric::*;
  47     import defined_types::*;
  48     import MemoryMap             :: *;
  49     import slow_peripherals::*;
  50 `ifdef DEBUG
  51     `include "defines.bsv"
  52 `endif
  53     `include "instance_defines.bsv"
  54 {8}
  55     /*====== AXI4 slave declarations =======*/
  56 {3}
  57     /*====== AXI4 Master declarations =======*/
  58 {4}
  59
  60
  61     `ifdef DMA
  62         import DMA                               :: *;
  63     `endif
  64     `ifdef BOOTROM
  65         import BootRom                  ::*;
  66     `endif
  67     `ifdef SDRAM
  68         import sdr_top                   :: *;
  69     `endif
  70     `ifdef BRAM
  71         import Memory_AXI4      ::*;
  72     `endif
  73     `ifdef TCMemory
  74         import TCM::*;
  75     `endif
  76     `ifdef Debug
  77         import DebugModule::*;
  78     `else
  79         import core::*;
  80     `endif
  81     `ifdef  VME
  82         import vme_top ::*;
  83     `endif
  84
  85     `ifdef VME
  86         import vme_master::*;
  87     `endif
  88     `ifdef FlexBus
  89         import FlexBus_Types::*;
  90     `endif
  91 {0}
  92
  93     /*========================= */
  94     interface Ifc_Soc;
  95         interface SP_ios slow_ios;
  96         (*always_ready,always_enabled*)
  97         method Action boot_sequence(Bit#(1) bootseq);
  98
  99         `ifdef SDRAM
 100             (*always_ready*) interface Ifc_sdram_out sdram_out;
 101         `endif
 102         `ifdef DDR
 103             (*prefix="M_AXI"*) interface
 104                    AXI4_Master_IFC#(`ADDR, `DATA, `USERSPACE) master;
 105         `endif
 106         `ifdef HYPER
 107              (*always_ready,always_enabled*)
 108              interface Ifc_flash ifc_flash;
 109         `endif
 110         /*=============================================== */
 111         `ifdef VME
 112              interface Vme_out  proc_ifc;
 113              interface Data_bus_inf proc_dbus;
 114         `endif
 115 {1}
 116     endinterface
 117
 118 function FastTuple2 #(Bool, Bit#(TLog#(Num_Slaves)))
 119                 fn_addr_to_slave_num  (Bit#(`PADDR) addr);
 120
 121     if(addr>=`SDRAMMemBase && addr<=`SDRAMMemEnd)
 122         return tuple2(True,fromInteger(valueOf(Sdram_slave_num)));
 123     else if(addr>=`DebugBase && addr<=`DebugEnd)
 124         return tuple2(True,fromInteger(valueOf(Debug_slave_num)));
 125     `ifdef SDRAM
 126         else if(addr>=`SDRAMCfgBase && addr<=`SDRAMCfgEnd )
 127             return tuple2(True,fromInteger(valueOf(Sdram_cfg_slave_num)));
 128     `endif
 129     `ifdef BOOTROM
 130         else if(addr>=`BootRomBase && addr<=`BootRomEnd)
 131             return tuple2(True,fromInteger(valueOf(BootRom_slave_num)));
 132     `endif
 133     `ifdef DMA
 134         else if(addr>=`DMABase && addr<=`DMAEnd)
 135             return tuple2(True,fromInteger(valueOf(Dma_slave_num)));
 136     `endif
 137     `ifdef VME
 138         else if(addr>=`VMEBase && addr<=`VMEEnd)
 139             return tuple2(True,fromInteger(valueOf(VME_slave_num)));
 140     `endif
 141     `ifdef TCMemory
 142         else if(addr>=`TCMBase && addr<=`TCMEnd)
 143             return tuple2(True,fromInteger(valueOf(TCM_slave_num)));
 144     `endif
 145         else
 146 {11}
 147             return tuple2(False,?);
 148 endfunction
 149
 150
 151     (*synthesize*)
 152     module mkSoc #(Bit#(`VADDR) reset_vector,
 153                  Clock slow_clock, Reset slow_reset, Clock uart_clock,
 154                  Reset uart_reset, Clock clk0, Clock tck, Reset trst
 155                  `ifdef PWM_AXI4Lite ,Clock ext_pwm_clock `endif )(Ifc_Soc);
 156         Clock core_clock <-exposeCurrentClock; // slow peripheral clock
 157         Reset core_reset <-exposeCurrentReset; // slow peripheral reset
 158 {2}
 159         `ifdef Debug
 160             Ifc_DebugModule core<-mkDebugModule(reset_vector);
 161         `else
 162             Ifc_core_AXI4 core <-mkcore_AXI4(reset_vector);
 163         `endif
 164         `ifdef BOOTROM
 165             BootRom_IFC bootrom <-mkBootRom;
 166         `endif
 167         `ifdef SDRAM
 168             Ifc_sdr_slave sdram<- mksdr_axi4_slave(clk0);
 169         `endif
 170         `ifdef BRAM
 171             Memory_IFC#(`SDRAMMemBase,`Addr_space)main_memory <-
 172                         mkMemory("code.mem.MSB","code.mem.LSB","MainMEM");
 173         `endif
 174         `ifdef TCMemory
 175             Ifc_TCM                                     tcm                             <- mkTCM;
 176         `endif
 177         `ifdef DMA
 178             DmaC#(7,`NUM_DMACHANNELS) dma       <- mkDMA();
 179         `endif
 180             `ifdef VME
 181             Ifc_vme_top             vme             <-mkvme_top();
 182             `endif
 183         Ifc_slow_peripherals slow_peripherals <-mkslow_peripherals(
 184                           core_clock, core_reset, uart_clock,
 185                           uart_reset, clocked_by slow_clock ,
 186                           reset_by slow_reset
 187                           `ifdef PWM_AXI4Lite , ext_pwm_clock `endif );
 188
 189         // Fabric
 190         AXI4_Fabric_IFC #(Num_Masters, Num_Slaves,
 191                           `ADDR, `DATA,`USERSPACE)
 192                         fabric <- mkAXI4_Fabric(fn_addr_to_slave_num);
 193
 194         // Connect traffic generators to fabric
 195         mkConnection (core.dmem_master,fabric.v_from_masters
 196                               [fromInteger(valueOf(Dmem_master_num))]);
 197         mkConnection (core.imem_master, fabric.v_from_masters
 198                               [fromInteger(valueOf(Imem_master_num))]);
 199         `ifdef Debug
 200             mkConnection (core.debug_master, fabric.v_from_masters
 201                               [fromInteger(valueOf(Debug_master_num))]);
 202         `endif
 203         `ifdef DMA
 204          mkConnection (dma.mmu, fabric.v_from_masters
 205                               [fromInteger(valueOf(DMA_master_num))]);
 206         `endif
 207
 208
 209         // Connect fabric to memory slaves
 210             `ifdef Debug
 211                 mkConnection (fabric.v_to_slaves
 212                               [fromInteger(valueOf(Debug_slave_num))],
 213                               core.debug_slave);
 214             `endif
 215             `ifdef SDRAM
 216                 mkConnection (fabric.v_to_slaves
 217                               [fromInteger(valueOf(Sdram_slave_num))],
 218                               sdram.axi4_slave_sdram); //
 219             mkConnection (fabric.v_to_slaves
 220                               [fromInteger(valueOf(Sdram_cfg_slave_num))],
 221                               sdram.axi4_slave_cntrl_reg); //
 222       `endif
 223       `ifdef BRAM
 224                 mkConnection(fabric.v_to_slaves
 225                               [fromInteger(valueOf(Sdram_slave_num))],
 226                               main_memory.axi_slave);
 227             `endif
 228             `ifdef BOOTROM
 229                 mkConnection (fabric.v_to_slaves
 230                               [fromInteger(valueOf(BootRom_slave_num))],
 231                               bootrom.axi_slave);
 232             `endif
 233             `ifdef DMA
 234             mkConnection (fabric.v_to_slaves
 235                               [fromInteger(valueOf(Dma_slave_num))],
 236                               dma.cfg); //DMA slave
 237             `endif
 238             `ifdef TCMemory
 239                 mkConnection (fabric.v_to_slaves
 240                               [fromInteger(valueOf(TCM_slave_num))],
 241                               tcm.axi_slave);
 242             `endif
 243             mkConnection(fabric.v_to_slaves
 244                               [fromInteger(valueOf(SlowPeripheral_slave_num))],
 245                               slow_peripherals.axi_slave);
 246             `ifdef VME
 247                 mkConnection (fabric.v_to_slaves
 248                               [fromInteger(valueOf(VME_slave_num))],
 249                               vme.slave_axi_vme);
 250             `endif
 251
 252 //          pin connections
 253 {9}
 254
 255             // fabric connections
 256 {5}
 257
 258             `ifdef DMA
 259             // rule to connect all interrupt lines to the DMA
 260             // All the interrupt lines to DMA are active
 261             // HIGH. For peripherals that are not connected,
 262             // or those which do not
 263             // generate an interrupt (like TCM), drive a constant 1
 264             // on the corresponding interrupt line.
 265 {7}
 266             `endif
 267
 268
 269         /*==== Synchornization between the JTAG and the Debug Module ===== */
 270         `ifdef Debug
 271             SyncFIFOIfc#(Bit#(40)) sync_request_to_dm <-
 272                                         mkSyncFIFOToCC(1,tck,trst);
 273             SyncFIFOIfc#(Bit#(34)) sync_response_from_dm <-
 274                                         mkSyncFIFOFromCC(1,tck);
 275             rule connect_tap_request_to_syncfifo;
 276                 let x<-tap.request_to_dm;
 277                 sync_request_to_dm.enq(x);
 278             endrule
 279             rule read_synced_request_to_dm;
 280                 sync_request_to_dm.deq;
 281                 core.request_from_dtm(sync_request_to_dm.first);
 282             endrule
 283
 284             rule connect_debug_response_to_syncfifo;
 285                 let x<-core.response_to_dtm;
 286                 sync_response_from_dm.enq(x);
 287             endrule
 288             rule read_synced_response_from_dm;
 289                 sync_response_from_dm.deq;
 290                 tap.response_from_dm(sync_response_from_dm.first);
 291             endrule
 292         `endif
 293         /*============================================================ */
 294
 295         `ifdef FlexBus
 296             //rule drive_flexbus_inputs;
 297                //flexbus.flexbus_side.m_TAn(1'b1);
 298                //flexbus.flexbus_side.m_din(32'haaaaaaaa);
 299             //endrule
 300          `endif
 301
 302         `ifdef CLINT
 303             SyncBitIfc#(Bit#(1)) clint_mtip_int <-
 304                                         mkSyncBitToCC(slow_clock,slow_reset);
 305             SyncBitIfc#(Bit#(1)) clint_msip_int <-
 306                                         mkSyncBitToCC(slow_clock,slow_reset);
 307             Reg#(Bit#(`DATA)) clint_mtime_value <-
 308                                         mkSyncRegToCC(0,slow_clock,slow_reset);
 309             rule synchronize_clint_data;
 310                 clint_mtip_int.send(slow_peripherals.mtip_int);
 311                 clint_msip_int.send(slow_peripherals.msip_int);
 312                 clint_mtime_value<=slow_peripherals.mtime;
 313             endrule
 314             rule connect_msip_mtip_from_clint;
 315                 core.clint_msip(clint_msip_int.read);
 316                 core.clint_mtip(clint_mtip_int.read);
 317             core.clint_mtime(clint_mtime_value);
 318             endrule
 319         `endif
 320         `ifdef PLIC
 321             Reg#(Tuple2#(Bool,Bool)) plic_interrupt_note <-
 322                                         mkSyncRegToCC(tuple2(False,False),
 323                                                       slow_clock,slow_reset);
 324             rule synchronize_interrupts;
 325                 let note <- slow_peripherals.intrpt_note;
 326                 plic_interrupt_note<=note;
 327             endrule
 328             rule rl_send_external_interrupt_to_csr;
 329                 core.set_external_interrupt(plic_interrupt_note);
 330             endrule
 331         `endif
 332
 333         `ifdef VME
 334             interface  proc_ifc = vme.proc_ifc;
 335             interface   proc_dbus = vme.proc_dbus;
 336         `endif
 337          method Action boot_sequence(Bit#(1) bootseq) =
 338                             core.boot_sequence(bootseq);
 339         `ifdef SDRAM
 340             interface sdram_out=sdram.ifc_sdram_out;
 341         `endif
 342         `ifdef DDR
 343           interface master=fabric.v_to_slaves
 344                                 [fromInteger(valueOf(Sdram_slave_num))];
 345         `endif
 346         interface slow_ios=slow_peripherals.slow_ios;
 347 {6}
 348     endmodule
 349 endpackage