4 from UserDict
import UserDict
6 from collections
import UserDict
8 from bsv
.wire_def
import generic_io
# special case
9 from bsv
.wire_def
import muxwire
# special case
13 """ pin interface declaration.
14 * name is the name of the pin
15 * ready, enabled and io all create a (* .... *) prefix
16 * action changes it to an "in" if true
19 def __init__(self
, name
,
28 self
.enabled
= enabled
31 self
.bitspec
= bitspec
if bitspec
else 'Bit#(1)'
32 self
.outenmode
= outenmode
34 # bsv will look like this (method declaration):
36 (*always_ready,always_enabled*) method Bit#(1) io0_cell_outen;
37 (*always_ready,always_enabled,result="io"*) method
38 Action io0_inputval (Bit#(1) in);
40 def ifacefmt(self
, fmtfn
):
44 status
.append('always_ready')
46 status
.append('always_enabled')
48 status
.append('result="io"')
51 res
+= ','.join(status
)
56 name
= fmtfn(self
.name
)
60 res
+= ' (%s in)' % self
.bitspec
62 res
+= " %s " % self
.bitspec
67 # sample bsv method definition :
69 method Action cell0_mux(Bit#(2) in);
73 def ifacedef(self
, fmtoutfn
, fmtinfn
, fmtdecfn
):
76 fmtname
= fmtinfn(self
.name
)
78 res
+= fmtdecfn(self
.name
)
79 res
+= '(%s in);\n' % self
.bitspec
80 res
+= ' %s<=in;\n' % fmtname
83 fmtname
= fmtoutfn(self
.name
)
84 res
+= "%s=%s;" % (self
.name
, fmtname
)
86 #sample bsv wire (wire definiton):
88 Wire#(Bit#(2)) wrcell0_mux<-mkDWire(0);
90 def wirefmt(self
, fmtoutfn
, fmtinfn
, fmtdecfn
):
91 res
= ' Wire#(%s) ' % self
.bitspec
93 res
+= '%s' % fmtinfn(self
.name
)
95 res
+= '%s' % fmtoutfn(self
.name
)
96 res
+= "<-mkDWire(0);"
100 class Interface(object):
101 """ create an interface from a list of pinspecs.
102 each pinspec is a dictionary, see Pin class arguments
103 single indicates that there is only one of these, and
104 so the name must *not* be extended numerically (see pname)
106 #sample interface object:
108 twiinterface_decl = Interface('twi',
109 [{'name': 'sda', 'outen': True},
110 {'name': 'scl', 'outen': True},
113 def __init__(self
, ifacename
, pinspecs
, ganged
=None, single
=False):
114 self
.ifacename
= ifacename
115 self
.ganged
= ganged
or {}
116 self
.pins
= [] # a list of instances of class Pin
117 self
.pinspecs
= pinspecs
# a list of dictionary
122 if p
.get('outen') is True: # special case, generate 3 pins
124 for psuffix
in ['out', 'outen', 'in']:
125 # changing the name (like sda) to (twi_sda_out)
126 _p
['name'] = "%s_%s" % (self
.pname(p
['name']), psuffix
)
127 _p
['action'] = psuffix
!= 'in'
128 self
.pins
.append(Pin(**_p
))
129 #will look like {'name': 'twi_sda_out', 'action': True}
130 # {'name': 'twi_sda_outen', 'action': True}
131 #{'name': 'twi_sda_in', 'action': False}
132 # NOTice - outen key is removed
134 _p
['name'] = self
.pname(p
['name'])
135 self
.pins
.append(Pin(**_p
))
137 # sample interface object:
139 uartinterface_decl = Interface('uart',
141 {'name': 'tx', 'action': True},
145 getifacetype is called multiple times in actual_pinmux.py
146 x = ifaces.getifacetype(temp), where temp is uart_rx, spi_mosi
147 Purpose is to identify is function : input/output/inout
149 def getifacetype(self
, name
):
150 for p
in self
.pinspecs
:
151 fname
= "%s_%s" % (self
.ifacename
, p
['name'])
152 #print "search", self.ifacename, name, fname
161 def pname(self
, name
):
162 """ generates the interface spec e.g. flexbus_ale
163 if there is only one flexbus interface, or
164 sd{0}_cmd if there are several. string format
165 function turns this into sd0_cmd, sd1_cmd as
166 appropriate. single mode stops the numerical extension.
169 return '%s_%s' % (self
.ifacename
, name
)
170 return '%s{0}_%s' % (self
.ifacename
, name
)
172 def busfmt(self
, *args
):
173 """ this function creates a bus "ganging" system based
174 on input from the {interfacename}.txt file.
175 only inout pins that are under the control of the
176 interface may be "ganged" together.
179 return '' # when self.ganged is None
182 for (k
, pnames
) in self
.ganged
.items():
183 name
= self
.pname('%senable' % k
).format(*args
)
184 decl
= 'Bit#(1) %s = 0;' % name
187 for p
in self
.pinspecs
:
188 if p
['name'] not in pnames
:
190 pname
= self
.pname(p
['name']).format(*args
)
191 if p
.get('outen') is True:
192 outname
= self
.ifacefmtoutfn(pname
)
193 ganged
.append("%s_outen" % outname
) # match wirefmt
195 gangedfmt
= '{%s} = duplicate(%s);'
196 res
.append(gangedfmt
% (',\n '.join(ganged
), name
))
197 return '\n'.join(res
) + '\n\n'
199 def wirefmt(self
, *args
):
200 res
= '\n'.join(map(self
.wirefmtpin
, self
.pins
)).format(*args
)
204 def ifacefmt(self
, *args
):
205 res
= '\n'.join(map(self
.ifacefmtdecpin
, self
.pins
)).format(*args
)
206 return '\n' + res
# pins is a list
208 def ifacefmtdecfn(self
, name
):
209 return name
# like: uart
211 def ifacefmtdecfn2(self
, name
):
212 return name
# like: uart
214 def ifacefmtdecfn3(self
, name
):
216 return "%s_outen" % name
#like uart_outen
218 def ifacefmtoutfn(self
, name
):
219 return "wr%s" % name
#like wruart
221 def ifacefmtinfn(self
, name
):
224 def wirefmtpin(self
, pin
):
225 return pin
.wirefmt(self
.ifacefmtoutfn
, self
.ifacefmtinfn
,
228 def ifacefmtdecpin(self
, pin
):
229 return pin
.ifacefmt(self
.ifacefmtdecfn
)
231 def ifacefmtpin(self
, pin
):
232 decfn
= self
.ifacefmtdecfn2
233 outfn
= self
.ifacefmtoutfn
234 #print pin, pin.outenmode
236 decfn
= self
.ifacefmtdecfn3
237 outfn
= self
.ifacefmtoutenfn
238 return pin
.ifacedef(outfn
, self
.ifacefmtinfn
,
241 def ifacedef(self
, *args
):
242 res
= '\n'.join(map(self
.ifacefmtpin
, self
.pins
))
243 res
= res
.format(*args
)
244 return '\n' + res
+ '\n'
247 class MuxInterface(Interface
):
249 def wirefmt(self
, *args
):
250 return muxwire
.format(*args
)
253 class IOInterface(Interface
):
255 def ifacefmtoutenfn(self
, name
):
256 return "cell{0}_mux_outen"
258 def ifacefmtoutfn(self
, name
):
259 """ for now strip off io{0}_ part """
260 return "cell{0}_mux_out"
262 def ifacefmtinfn(self
, name
):
263 return "cell{0}_mux_in"
265 def wirefmt(self
, *args
):
266 return generic_io
.format(*args
)
269 class Interfaces(UserDict
):
270 """ contains a list of interface definitions
273 def __init__(self
, pth
=None):
276 UserDict
.__init
__(self
, {})
279 ift
= 'interfaces.txt'
281 ift
= os
.path
.join(pth
, ift
)
282 with
open(ift
, 'r') as ifile
:
283 for ln
in ifile
.readlines():
286 name
= ln
[0] # will have uart
287 count
= int(ln
[1]) # will have count of uart
288 #spec looks like this:
290 [{'name': 'sda', 'outen': True},
291 {'name': 'scl', 'outen': True},
294 spec
, ganged
= self
.read_spec(pth
, name
)
295 iface
= Interface(name
, spec
, ganged
, count
== 1)
296 self
.ifaceadd(name
, count
, iface
)
298 def getifacetype(self
, fname
):
299 # finds the interface type, e.g sd_d0 returns "inout"
300 for iface
in self
.values():
301 typ
= iface
.getifacetype(fname
)
306 def ifaceadd(self
, name
, count
, iface
, at
=None):
308 at
= len(self
.ifacecount
)# ifacecount is a list
309 self
.ifacecount
.insert(at
, (name
, count
))# appends the list
310 # with (name,count) *at* times
313 # will check specific peripheral.txt files like spi.txt
314 def read_spec(self
, pth
, name
):
317 fname
= '%s.txt' % name
319 ift
= os
.path
.join(pth
, fname
)
320 with
open(ift
, 'r') as sfile
:
321 for ln
in sfile
.readlines():
325 d
= {'name': name
}# here we start to make the dictionary
327 d
['action'] = True # adding element to the dict
328 elif ln
[1] == 'inout':
332 if bus
not in ganged
:
334 ganged
[bus
].append(name
)
338 def ifacedef(self
, f
, *args
):
339 for (name
, count
) in self
.ifacecount
:
340 for i
in range(count
):
341 f
.write(self
.data
[name
].ifacedef(i
))
343 def busfmt(self
, f
, *args
):
344 f
.write("import BUtils::*;\n\n")
345 for (name
, count
) in self
.ifacecount
:
346 for i
in range(count
):
347 bf
= self
.data
[name
].busfmt(i
)
350 def ifacefmt(self
, f
, *args
):
352 // interface declaration between %s-{0} and pinmux'''
353 for (name
, count
) in self
.ifacecount
:
354 for i
in range(count
):
355 c
= comment
% name
.upper()
357 f
.write(self
.data
[name
].ifacefmt(i
))
359 def wirefmt(self
, f
, *args
):
360 comment
= '\n // following wires capture signals ' \
361 'to IO CELL if %s-{0} is\n' \
363 for (name
, count
) in self
.ifacecount
:
364 for i
in range(count
):
367 f
.write(self
.data
[name
].wirefmt(i
))
370 # ========= Interface declarations ================ #
372 mux_interface
= MuxInterface('cell', [{'name': 'mux', 'ready': False,
374 'bitspec': '{1}', 'action': True}])
376 io_interface
= IOInterface(
378 [{'name': 'cell_out', 'enabled': True, },
379 {'name': 'cell_outen', 'enabled': True, 'outenmode': True, },
380 {'name': 'cell_in', 'action': True, 'io': True}, ])
382 # == Peripheral Interface definitions == #
383 # these are the interface of the peripherals to the pin mux
384 # Outputs from the peripherals will be inputs to the pinmux
385 # module. Hence the change in direction for most pins
387 # ======================================= #
390 if __name__
== '__main__':
392 uartinterface_decl
= Interface('uart',
394 {'name': 'tx', 'action': True},
397 twiinterface_decl
= Interface('twi',
398 [{'name': 'sda', 'outen': True},
399 {'name': 'scl', 'outen': True},
402 def _pinmunge(p
, sep
, repl
, dedupe
=True):
403 """ munges the text so it's easier to compare.
404 splits by separator, strips out blanks, re-joins.
409 p
= filter(lambda x
: x
, p
) # filter out blanks
413 """ munges the text so it's easier to compare.
415 # first join lines by semicolons, strip out returns
417 p
= map(lambda x
: x
.replace('\n', ''), p
)
419 # now split first by brackets, then spaces (deduping on spaces)
420 p
= _pinmunge(p
, "(", " ( ", False)
421 p
= _pinmunge(p
, ")", " ) ", False)
422 p
= _pinmunge(p
, " ", " ")
428 for p1
, p2
in zip(l1
, l2
):
434 ifaces
= Interfaces()
436 ifaceuart
= ifaces
['uart']
437 print (ifaceuart
.ifacedef(0))
438 print (uartinterface_decl
.ifacedef(0))
439 assert ifaceuart
.ifacedef(0) == uartinterface_decl
.ifacedef(0)
441 ifacetwi
= ifaces
['twi']
442 print (ifacetwi
.ifacedef(0))
443 print (twiinterface_decl
.ifacedef(0))
444 assert ifacetwi
.ifacedef(0) == twiinterface_decl
.ifacedef(0)