4 from UserDict
import UserDict
6 from collections
import UserDict
8 from bsv
.wire_def
import generic_io
# special case
9 from bsv
.wire_def
import muxwire
# special case
10 from ifacebase
import InterfacesBase
11 from bsv
.peripheral_gen
import PFactory
12 slowfactory
= PFactory()
16 """ pin interface declaration.
17 * name is the name of the pin
18 * ready, enabled and io all create a (* .... *) prefix
19 * action changes it to an "in" if true
22 def __init__(self
, name
,
31 self
.enabled
= enabled
34 self
.bitspec
= bitspec
if bitspec
else 'Bit#(1)'
35 self
.outenmode
= outenmode
37 # bsv will look like this (method declaration):
39 (*always_ready,always_enabled*) method Bit#(1) io0_cell_outen;
40 (*always_ready,always_enabled,result="io"*) method
41 Action io0_inputval (Bit#(1) in);
44 def ifacefmt(self
, fmtfn
):
48 status
.append('always_ready')
50 status
.append('always_enabled')
52 status
.append('result="io"')
55 res
+= ','.join(status
)
60 name
= fmtfn(self
.name
)
64 res
+= ' (%s in)' % self
.bitspec
66 res
+= " %s " % self
.bitspec
71 # sample bsv method definition :
73 method Action cell0_mux(Bit#(2) in);
78 def ifacedef(self
, fmtoutfn
, fmtinfn
, fmtdecfn
):
81 fmtname
= fmtinfn(self
.name
)
83 res
+= fmtdecfn(self
.name
)
84 res
+= '(%s in);\n' % self
.bitspec
85 res
+= ' %s<=in;\n' % fmtname
88 fmtname
= fmtoutfn(self
.name
)
89 res
+= "%s=%s;" % (self
.name
, fmtname
)
91 # sample bsv wire (wire definiton):
93 Wire#(Bit#(2)) wrcell0_mux<-mkDWire(0);
96 def wirefmt(self
, fmtoutfn
, fmtinfn
, fmtdecfn
):
97 res
= ' Wire#(%s) ' % self
.bitspec
99 res
+= '%s' % fmtinfn(self
.name
)
101 res
+= '%s' % fmtoutfn(self
.name
)
102 res
+= "<-mkDWire(0);"
106 class Interface(object):
107 """ create an interface from a list of pinspecs.
108 each pinspec is a dictionary, see Pin class arguments
109 single indicates that there is only one of these, and
110 so the name must *not* be extended numerically (see pname)
112 # sample interface object:
114 twiinterface_decl = Interface('twi',
115 [{'name': 'sda', 'outen': True},
116 {'name': 'scl', 'outen': True},
120 def __init__(self
, ifacename
, pinspecs
, ganged
=None, single
=False):
121 self
.ifacename
= ifacename
122 self
.ganged
= ganged
or {}
123 self
.pins
= [] # a list of instances of class Pin
124 self
.pinspecs
= pinspecs
# a list of dictionary
127 slow
= slowfactory
.getcls(ifacename
)
136 if p
.get('outen') is True: # special case, generate 3 pins
138 for psuffix
in ['out', 'outen', 'in']:
139 # changing the name (like sda) to (twi_sda_out)
140 _p
['name'] = "%s_%s" % (self
.pname(p
['name']), psuffix
)
141 _p
['action'] = psuffix
!= 'in'
142 self
.pins
.append(Pin(**_p
))
143 # will look like {'name': 'twi_sda_out', 'action': True}
144 # {'name': 'twi_sda_outen', 'action': True}
145 #{'name': 'twi_sda_in', 'action': False}
146 # NOTice - outen key is removed
148 _p
['name'] = self
.pname(p
['name'])
149 self
.pins
.append(Pin(**_p
))
151 # sample interface object:
153 uartinterface_decl = Interface('uart',
155 {'name': 'tx', 'action': True},
159 getifacetype is called multiple times in actual_pinmux.py
160 x = ifaces.getifacetype(temp), where temp is uart_rx, spi_mosi
161 Purpose is to identify is function : input/output/inout
164 def getifacetype(self
, name
):
165 for p
in self
.pinspecs
:
166 fname
= "%s_%s" % (self
.ifacename
, p
['name'])
167 #print "search", self.ifacename, name, fname
176 def pname(self
, name
):
177 """ generates the interface spec e.g. flexbus_ale
178 if there is only one flexbus interface, or
179 sd{0}_cmd if there are several. string format
180 function turns this into sd0_cmd, sd1_cmd as
181 appropriate. single mode stops the numerical extension.
184 return '%s_%s' % (self
.ifacename
, name
)
185 return '%s{0}_%s' % (self
.ifacename
, name
)
187 def busfmt(self
, *args
):
188 """ this function creates a bus "ganging" system based
189 on input from the {interfacename}.txt file.
190 only inout pins that are under the control of the
191 interface may be "ganged" together.
194 return '' # when self.ganged is None
197 for (k
, pnames
) in self
.ganged
.items():
198 name
= self
.pname('%senable' % k
).format(*args
)
199 decl
= 'Bit#(1) %s = 0;' % name
202 for p
in self
.pinspecs
:
203 if p
['name'] not in pnames
:
205 pname
= self
.pname(p
['name']).format(*args
)
206 if p
.get('outen') is True:
207 outname
= self
.ifacefmtoutfn(pname
)
208 ganged
.append("%s_outen" % outname
) # match wirefmt
210 gangedfmt
= '{%s} = duplicate(%s);'
211 res
.append(gangedfmt
% (',\n '.join(ganged
), name
))
212 return '\n'.join(res
) + '\n\n'
214 def wirefmt(self
, *args
):
215 res
= '\n'.join(map(self
.wirefmtpin
, self
.pins
)).format(*args
)
219 def ifacefmt(self
, *args
):
220 res
= '\n'.join(map(self
.ifacefmtdecpin
, self
.pins
)).format(*args
)
221 return '\n' + res
# pins is a list
223 def ifacefmtdecfn(self
, name
):
224 return name
# like: uart
226 def ifacefmtdecfn2(self
, name
):
227 return name
# like: uart
229 def ifacefmtdecfn3(self
, name
):
231 return "%s_outen" % name
# like uart_outen
233 def ifacefmtoutfn(self
, name
):
234 return "wr%s" % name
# like wruart
236 def ifacefmtinfn(self
, name
):
239 def wirefmtpin(self
, pin
):
240 return pin
.wirefmt(self
.ifacefmtoutfn
, self
.ifacefmtinfn
,
243 def ifacefmtdecpin(self
, pin
):
244 return pin
.ifacefmt(self
.ifacefmtdecfn
)
246 def ifacefmtpin(self
, pin
):
247 decfn
= self
.ifacefmtdecfn2
248 outfn
= self
.ifacefmtoutfn
249 #print pin, pin.outenmode
251 decfn
= self
.ifacefmtdecfn3
252 outfn
= self
.ifacefmtoutenfn
253 return pin
.ifacedef(outfn
, self
.ifacefmtinfn
,
256 def ifacedef(self
, *args
):
257 res
= '\n'.join(map(self
.ifacefmtpin
, self
.pins
))
258 res
= res
.format(*args
)
259 return '\n' + res
+ '\n'
261 def slowimport(self
):
264 return self
.slow
.importfn().format()
266 def slowifdecl(self
, count
):
269 return self
.slow
.ifacedecl().format(count
, self
.ifacename
)
272 class MuxInterface(Interface
):
274 def wirefmt(self
, *args
):
275 return muxwire
.format(*args
)
278 class IOInterface(Interface
):
280 def ifacefmtoutenfn(self
, name
):
281 return "cell{0}_mux_outen"
283 def ifacefmtoutfn(self
, name
):
284 """ for now strip off io{0}_ part """
285 return "cell{0}_mux_out"
287 def ifacefmtinfn(self
, name
):
288 return "cell{0}_mux_in"
290 def wirefmt(self
, *args
):
291 return generic_io
.format(*args
)
294 class Interfaces(InterfacesBase
):
295 """ contains a list of interface definitions
298 def __init__(self
, pth
=None):
299 InterfacesBase
.__init
__(self
, Interface
, pth
)
301 def ifacedef(self
, f
, *args
):
302 for (name
, count
) in self
.ifacecount
:
303 for i
in range(count
):
304 f
.write(self
.data
[name
].ifacedef(i
))
306 def busfmt(self
, f
, *args
):
307 f
.write("import BUtils::*;\n\n")
308 for (name
, count
) in self
.ifacecount
:
309 for i
in range(count
):
310 bf
= self
.data
[name
].busfmt(i
)
313 def ifacefmt(self
, f
, *args
):
315 // interface declaration between %s-{0} and pinmux'''
316 for (name
, count
) in self
.ifacecount
:
317 for i
in range(count
):
318 c
= comment
% name
.upper()
320 f
.write(self
.data
[name
].ifacefmt(i
))
322 def wirefmt(self
, f
, *args
):
323 comment
= '\n // following wires capture signals ' \
324 'to IO CELL if %s-{0} is\n' \
326 for (name
, count
) in self
.ifacecount
:
327 for i
in range(count
):
330 f
.write(self
.data
[name
].wirefmt(i
))
332 def slowimport(self
, *args
):
334 for (name
, count
) in self
.ifacecount
:
335 ret
.append(self
.data
[name
].slowimport())
336 return '\n'.join(list(filter(None, ret
)))
338 def slowifdecl(self
, *args
):
340 for (name
, count
) in self
.ifacecount
:
341 for i
in range(count
):
342 ret
.append(self
.data
[name
].slowifdecl(i
))
343 return '\n'.join(list(filter(None, ret
)))
346 # ========= Interface declarations ================ #
348 mux_interface
= MuxInterface('cell',
349 [{'name': 'mux', 'ready': False, 'enabled': False,
350 'bitspec': '{1}', 'action': True}])
352 io_interface
= IOInterface(
354 [{'name': 'cell_out', 'enabled': True, },
355 {'name': 'cell_outen', 'enabled': True, 'outenmode': True, },
356 {'name': 'cell_in', 'action': True, 'io': True}, ])
358 # == Peripheral Interface definitions == #
359 # these are the interface of the peripherals to the pin mux
360 # Outputs from the peripherals will be inputs to the pinmux
361 # module. Hence the change in direction for most pins
363 # ======================================= #
366 if __name__
== '__main__':
368 uartinterface_decl
= Interface('uart',
370 {'name': 'tx', 'action': True},
373 twiinterface_decl
= Interface('twi',
374 [{'name': 'sda', 'outen': True},
375 {'name': 'scl', 'outen': True},
378 def _pinmunge(p
, sep
, repl
, dedupe
=True):
379 """ munges the text so it's easier to compare.
380 splits by separator, strips out blanks, re-joins.
385 p
= filter(lambda x
: x
, p
) # filter out blanks
389 """ munges the text so it's easier to compare.
391 # first join lines by semicolons, strip out returns
393 p
= map(lambda x
: x
.replace('\n', ''), p
)
395 # now split first by brackets, then spaces (deduping on spaces)
396 p
= _pinmunge(p
, "(", " ( ", False)
397 p
= _pinmunge(p
, ")", " ) ", False)
398 p
= _pinmunge(p
, " ", " ")
404 for p1
, p2
in zip(l1
, l2
):
410 ifaces
= Interfaces()
412 ifaceuart
= ifaces
['uart']
413 print (ifaceuart
.ifacedef(0))
414 print (uartinterface_decl
.ifacedef(0))
415 assert ifaceuart
.ifacedef(0) == uartinterface_decl
.ifacedef(0)
417 ifacetwi
= ifaces
['twi']
418 print (ifacetwi
.ifacedef(0))
419 print (twiinterface_decl
.ifacedef(0))
420 assert ifacetwi
.ifacedef(0) == twiinterface_decl
.ifacedef(0)