4 from UserDict
import UserDict
6 from collections
import UserDict
8 from bsv
.wire_def
import generic_io
# special case
9 from bsv
.wire_def
import muxwire
# special case
10 from ifacebase
import InterfacesBase
11 from bsv
.peripheral_gen
import PeripheralIface
12 from bsv
.peripheral_gen
import PeripheralInterfaces
16 """ pin interface declaration.
17 * name is the name of the pin
18 * ready, enabled and io all create a (* .... *) prefix
19 * action changes it to an "in" if true
22 def __init__(self
, name
,
35 self
.enabled
= enabled
38 self
.bitspec
= bitspec
if bitspec
else 'Bit#(1)'
39 self
.outenmode
= outenmode
41 # bsv will look like this (method declaration):
43 (*always_ready,always_enabled*) method Bit#(1) io0_cell_outen;
44 (*always_ready,always_enabled,result="io"*) method
45 Action io0_inputval (Bit#(1) in);
48 def ifacepfmt(self
, fmtfn
):
52 name
= fmtfn(self
.name_
)
57 res
+= "#(%s) %s;" % (self
.bitspec
, name
)
60 def ifacefmt(self
, fmtfn
):
64 status
.append('always_ready')
66 status
.append('always_enabled')
68 status
.append('result="io"')
71 res
+= ','.join(status
)
76 name
= fmtfn(self
.name
)
80 res
+= ' (%s in)' % self
.bitspec
82 res
+= " %s " % self
.bitspec
87 def ifacedef(self
, fmtoutfn
, fmtinfn
, fmtdecfn
):
90 fmtname
= fmtinfn(self
.name
)
92 res
+= fmtdecfn(self
.name
)
93 res
+= '(%s in);\n' % self
.bitspec
94 res
+= ' %s<=in;\n' % fmtname
97 fmtname
= fmtoutfn(self
.name
)
98 res
+= "%s=%s;" % (self
.name
, fmtname
)
100 # sample bsv method definition :
102 method Action cell0_mux(Bit#(2) in);
107 # sample bsv wire (wire definiton):
109 Wire#(Bit#(2)) wrcell0_mux<-mkDWire(0);
112 def wirefmt(self
, fmtoutfn
, fmtinfn
, fmtdecfn
):
113 res
= ' Wire#(%s) ' % self
.bitspec
115 res
+= '%s' % fmtinfn(self
.name
)
117 res
+= '%s' % fmtoutfn(self
.name
)
118 res
+= "<-mkDWire(0);"
121 def ifacedef2(self
, fmtoutfn
, fmtinfn
, fmtdecfn
):
123 fmtname
= fmtinfn(self
.name
)
124 res
= " interface %s = interface Put\n" % self
.name_
127 #res += fmtdecfn(self.name)
128 res
+= '(%s in);\n' % self
.bitspec
129 res
+= ' %s<=in;\n' % fmtname
130 res
+= ' endmethod\n'
131 res
+= ' endinterface;'
133 fmtname
= fmtoutfn(self
.name
)
134 res
= " interface %s = interface Get\n" % self
.name_
135 res
+= ' method ActionValue#'
136 res
+= '(%s) get;\n' % self
.bitspec
137 res
+= " return %s;\n" % (fmtname
)
138 res
+= ' endmethod\n'
139 res
+= ' endinterface;'
142 def ifacedef3(self
, fmtoutfn
, fmtinfn
, fmtdecfn
):
144 if self
.name
.endswith('outen'):
148 fmtname
= fmtinfn(self
.name
)
149 res
= " %s <= %s[%d];" % (fmtname
, name
, self
.idx
)
151 fmtname
= fmtoutfn(self
.name
)
152 res
= " tget[%d] = %s;" % (self
.idx
, fmtname
)
155 class Interface(PeripheralIface
):
156 """ create an interface from a list of pinspecs.
157 each pinspec is a dictionary, see Pin class arguments
158 single indicates that there is only one of these, and
159 so the name must *not* be extended numerically (see pname)
161 # sample interface object:
163 twiinterface_decl = Interface('twi',
164 [{'name': 'sda', 'outen': True},
165 {'name': 'scl', 'outen': True},
169 def __init__(self
, ifacename
, pinspecs
, ganged
=None, single
=False):
170 PeripheralIface
.__init
__(self
, ifacename
)
171 self
.ifacename
= ifacename
172 self
.ganged
= ganged
or {}
173 self
.pins
= [] # a list of instances of class Pin
174 self
.pinspecs
= pinspecs
# a list of dictionary
177 for idx
, p
in enumerate(pinspecs
):
182 if p
.get('outen') is True: # special case, generate 3 pins
184 for psuffix
in ['out', 'outen', 'in']:
185 # changing the name (like sda) to (twi_sda_out)
186 _p
['name_'] = "%s_%s" % (p
['name'], psuffix
)
187 _p
['name'] = "%s_%s" % (self
.pname(p
['name']), psuffix
)
188 _p
['action'] = psuffix
!= 'in'
190 self
.pins
.append(Pin(**_p
))
191 # will look like {'name': 'twi_sda_out', 'action': True}
192 # {'name': 'twi_sda_outen', 'action': True}
193 #{'name': 'twi_sda_in', 'action': False}
194 # NOTice - outen key is removed
197 if name
.isdigit(): # HACK! deals with EINT case
198 name
= self
.pname(name
)
201 _p
['name'] = self
.pname(p
['name'])
202 self
.pins
.append(Pin(**_p
))
204 # sample interface object:
206 uartinterface_decl = Interface('uart',
208 {'name': 'tx', 'action': True},
212 getifacetype is called multiple times in actual_pinmux.py
213 x = ifaces.getifacetype(temp), where temp is uart_rx, spi_mosi
214 Purpose is to identify is function : input/output/inout
217 def getifacetype(self
, name
):
218 for p
in self
.pinspecs
:
219 fname
= "%s_%s" % (self
.ifacename
, p
['name'])
220 # print "search", self.ifacename, name, fname
230 """ generates the interface spec e.g. flexbus_ale
231 if there is only one flexbus interface, or
232 sd{0}_cmd if there are several. string format
233 function turns this into sd0_cmd, sd1_cmd as
234 appropriate. single mode stops the numerical extension.
237 return self
.ifacename
238 return '%s{0}' % self
.ifacename
240 def pname(self
, name
):
241 """ generates the interface spec e.g. flexbus_ale
242 if there is only one flexbus interface, or
243 sd{0}_cmd if there are several. string format
244 function turns this into sd0_cmd, sd1_cmd as
245 appropriate. single mode stops the numerical extension.
247 return "%s_%s" % (self
.iname(), name
)
249 def busfmt(self
, *args
):
250 """ this function creates a bus "ganging" system based
251 on input from the {interfacename}.txt file.
252 only inout pins that are under the control of the
253 interface may be "ganged" together.
256 return '' # when self.ganged is None
259 for (k
, pnames
) in self
.ganged
.items():
260 name
= self
.pname('%senable' % k
).format(*args
)
261 decl
= 'Bit#(1) %s = 0;' % name
264 for p
in self
.pinspecs
:
265 if p
['name'] not in pnames
:
267 pname
= self
.pname(p
['name']).format(*args
)
268 if p
.get('outen') is True:
269 outname
= self
.ifacefmtoutfn(pname
)
270 ganged
.append("%s_outen" % outname
) # match wirefmt
272 gangedfmt
= '{%s} = duplicate(%s);'
273 res
.append(gangedfmt
% (',\n '.join(ganged
), name
))
274 return '\n'.join(res
) + '\n\n'
276 def wirefmt(self
, *args
):
277 res
= '\n'.join(map(self
.wirefmtpin
, self
.pins
)).format(*args
)
281 def ifacepfmt(self
, *args
):
282 res
= '\n'.join(map(self
.ifacepfmtdecpin
, self
.pins
)).format(*args
)
283 return '\n' + res
# pins is a list
285 def ifacefmt(self
, *args
):
286 res
= '\n'.join(map(self
.ifacefmtdecpin
, self
.pins
)).format(*args
)
287 return '\n' + res
# pins is a list
289 def ifacepfmtdecfn(self
, name
):
292 def ifacefmtdecfn(self
, name
):
293 return name
# like: uart
295 def ifacefmtdecfn2(self
, name
):
296 return name
# like: uart
298 def ifacefmtdecfn3(self
, name
):
300 return "%s_outen" % name
# like uart_outen
302 def ifacefmtoutfn(self
, name
):
303 return "wr%s" % name
# like wruart
305 def ifacefmtinfn(self
, name
):
308 def wirefmtpin(self
, pin
):
309 return pin
.wirefmt(self
.ifacefmtoutfn
, self
.ifacefmtinfn
,
312 def ifacepfmtdecpin(self
, pin
):
313 return pin
.ifacepfmt(self
.ifacepfmtdecfn
)
315 def ifacefmtdecpin(self
, pin
):
316 return pin
.ifacefmt(self
.ifacefmtdecfn
)
318 def ifacefmtpin(self
, pin
):
319 decfn
= self
.ifacefmtdecfn2
320 outfn
= self
.ifacefmtoutfn
321 # print pin, pin.outenmode
323 decfn
= self
.ifacefmtdecfn3
324 outfn
= self
.ifacefmtoutenfn
325 return pin
.ifacedef(outfn
, self
.ifacefmtinfn
,
328 def ifacedef2pin(self
, pin
):
329 decfn
= self
.ifacefmtdecfn2
330 outfn
= self
.ifacefmtoutfn
331 # print pin, pin.outenmode
333 decfn
= self
.ifacefmtdecfn3
334 outfn
= self
.ifacefmtoutenfn
335 return pin
.ifacedef2(outfn
, self
.ifacefmtinfn
,
338 def ifacedef(self
, *args
):
339 res
= '\n'.join(map(self
.ifacefmtpin
, self
.pins
))
340 res
= res
.format(*args
)
341 return '\n' + res
+ '\n'
343 def ifacedef2(self
, *args
):
344 res
= '\n'.join(map(self
.ifacedef2pin
, self
.pins
))
345 res
= res
.format(*args
)
346 return '\n' + res
+ '\n'
349 class MuxInterface(Interface
):
351 def wirefmt(self
, *args
):
352 return muxwire
.format(*args
)
355 class IOInterface(Interface
):
357 def ifacefmtoutenfn(self
, name
):
358 return "cell{0}_mux_outen"
360 def ifacefmtoutfn(self
, name
):
361 """ for now strip off io{0}_ part """
362 return "cell{0}_mux_out"
364 def ifacefmtinfn(self
, name
):
365 return "cell{0}_mux_in"
367 def wirefmt(self
, *args
):
368 return generic_io
.format(*args
)
370 class InterfaceGPIO(Interface
):
372 def ifacedef2(self
, *args
):
373 res
= '\n'.join(map(self
.ifacedef2pin
, self
.pins
))
374 res
= res
.format(*args
)
377 Vector#({0},Bit#(1)) tput;
378 Vector#({0},Bit#(1)) tputen;
379 Vector#({0},Bit#(1)) tget;
380 """.format(len(self
.pinspecs
))
382 interface gpio_out = interface Put#
383 method Action put(Vector#({0},Bit#(1)) in);
387 interface gpio_outen = interface Put#
388 method Action put(Vector#({0},Bit#(1)) in);
392 interface gpio_in = interface Get#
393 method ActionValue#(Vector#({0},Bit#(1))) get;
397 """.format(len(self
.pinspecs
))
398 return '\n' + tdecl
+ res
+ '\n' + template
+ '\n'
400 def ifacedef2pin(self
, pin
):
401 decfn
= self
.ifacefmtdecfn2
402 outfn
= self
.ifacefmtoutfn
403 # print pin, pin.outenmode
405 decfn
= self
.ifacefmtdecfn3
406 outfn
= self
.ifacefmtoutenfn
407 return pin
.ifacedef3(outfn
, self
.ifacefmtinfn
,
411 class Interfaces(InterfacesBase
, PeripheralInterfaces
):
412 """ contains a list of interface definitions
415 def __init__(self
, pth
=None):
416 InterfacesBase
.__init
__(self
, Interface
, pth
,
417 {'gpio': InterfaceGPIO
})
418 PeripheralInterfaces
.__init
__(self
)
420 def ifacedef(self
, f
, *args
):
421 for (name
, count
) in self
.ifacecount
:
422 for i
in range(count
):
423 f
.write(self
.data
[name
].ifacedef(i
))
425 def ifacedef2(self
, f
, *args
):
426 c
= " interface {0} = interface PeripheralSide{1}"
427 for (name
, count
) in self
.ifacecount
:
428 for i
in range(count
):
429 iname
= self
.data
[name
].iname().format(i
)
430 f
.write(c
.format(iname
, name
.upper()))
431 f
.write(self
.data
[name
].ifacedef2(i
))
432 f
.write(" endinterface;\n\n")
434 def busfmt(self
, f
, *args
):
435 f
.write("import BUtils::*;\n\n")
436 for (name
, count
) in self
.ifacecount
:
437 for i
in range(count
):
438 bf
= self
.data
[name
].busfmt(i
)
441 def ifacepfmt(self
, f
, *args
):
443 // interface declaration between {0} and pinmux
444 (*always_ready,always_enabled*)
445 interface PeripheralSide{0};'''
446 for (name
, count
) in self
.ifacecount
:
447 f
.write(comment
.format(name
.upper()))
448 f
.write(self
.data
[name
].ifacepfmt(0))
449 f
.write("\n endinterface\n")
451 def ifacefmt(self
, f
, *args
):
453 // interface declaration between %s-{0} and pinmux'''
454 for (name
, count
) in self
.ifacecount
:
455 for i
in range(count
):
456 c
= comment
% name
.upper()
458 f
.write(self
.data
[name
].ifacefmt(i
))
460 def ifacefmt2(self
, f
, *args
):
462 interface PeripheralSide{0} {1};'''
463 for (name
, count
) in self
.ifacecount
:
464 for i
in range(count
):
465 iname
= self
.data
[name
].iname().format(i
)
466 f
.write(comment
.format(name
.upper(), iname
))
468 def wirefmt(self
, f
, *args
):
469 comment
= '\n // following wires capture signals ' \
470 'to IO CELL if %s-{0} is\n' \
472 for (name
, count
) in self
.ifacecount
:
473 for i
in range(count
):
476 f
.write(self
.data
[name
].wirefmt(i
))
479 # ========= Interface declarations ================ #
481 mux_interface
= MuxInterface('cell',
482 [{'name': 'mux', 'ready': False, 'enabled': False,
483 'bitspec': '{1}', 'action': True}])
485 io_interface
= IOInterface(
487 [{'name': 'cell_out', 'enabled': True, },
488 {'name': 'cell_outen', 'enabled': True, 'outenmode': True, },
489 {'name': 'cell_in', 'action': True, 'io': True}, ])
491 # == Peripheral Interface definitions == #
492 # these are the interface of the peripherals to the pin mux
493 # Outputs from the peripherals will be inputs to the pinmux
494 # module. Hence the change in direction for most pins
496 # ======================================= #
499 if __name__
== '__main__':
501 uartinterface_decl
= Interface('uart',
503 {'name': 'tx', 'action': True},
506 twiinterface_decl
= Interface('twi',
507 [{'name': 'sda', 'outen': True},
508 {'name': 'scl', 'outen': True},
511 def _pinmunge(p
, sep
, repl
, dedupe
=True):
512 """ munges the text so it's easier to compare.
513 splits by separator, strips out blanks, re-joins.
518 p
= filter(lambda x
: x
, p
) # filter out blanks
522 """ munges the text so it's easier to compare.
524 # first join lines by semicolons, strip out returns
526 p
= map(lambda x
: x
.replace('\n', ''), p
)
528 # now split first by brackets, then spaces (deduping on spaces)
529 p
= _pinmunge(p
, "(", " ( ", False)
530 p
= _pinmunge(p
, ")", " ) ", False)
531 p
= _pinmunge(p
, " ", " ")
537 for p1
, p2
in zip(l1
, l2
):
543 ifaces
= Interfaces()
545 ifaceuart
= ifaces
['uart']
546 print (ifaceuart
.ifacedef(0))
547 print (uartinterface_decl
.ifacedef(0))
548 assert ifaceuart
.ifacedef(0) == uartinterface_decl
.ifacedef(0)
550 ifacetwi
= ifaces
['twi']
551 print (ifacetwi
.ifacedef(0))
552 print (twiinterface_decl
.ifacedef(0))
553 assert ifacetwi
.ifacedef(0) == twiinterface_decl
.ifacedef(0)