4 from UserDict
import UserDict
6 from collections
import UserDict
8 from bsv
.wire_def
import generic_io
# special case
9 from bsv
.wire_def
import muxwire
# special case
10 from ifacebase
import InterfacesBase
11 from bsv
.peripheral_gen
import PeripheralIface
12 from bsv
.peripheral_gen
import PeripheralInterfaces
16 """ pin interface declaration.
17 * name is the name of the pin
18 * ready, enabled and io all create a (* .... *) prefix
19 * action changes it to an "in" if true
22 def __init__(self
, name
,
33 self
.enabled
= enabled
36 self
.bitspec
= bitspec
if bitspec
else 'Bit#(1)'
37 self
.outenmode
= outenmode
39 # bsv will look like this (method declaration):
41 (*always_ready,always_enabled*) method Bit#(1) io0_cell_outen;
42 (*always_ready,always_enabled,result="io"*) method
43 Action io0_inputval (Bit#(1) in);
46 def ifacepfmt(self
, fmtfn
):
50 name
= fmtfn(self
.name_
)
55 res
+= "#(%s) %s;" % (self
.bitspec
, name
)
58 def ifacefmt(self
, fmtfn
):
62 status
.append('always_ready')
64 status
.append('always_enabled')
66 status
.append('result="io"')
69 res
+= ','.join(status
)
74 name
= fmtfn(self
.name
)
78 res
+= ' (%s in)' % self
.bitspec
80 res
+= " %s " % self
.bitspec
85 def ifacedef(self
, fmtoutfn
, fmtinfn
, fmtdecfn
):
88 fmtname
= fmtinfn(self
.name
)
90 res
+= fmtdecfn(self
.name
)
91 res
+= '(%s in);\n' % self
.bitspec
92 res
+= ' %s<=in;\n' % fmtname
95 fmtname
= fmtoutfn(self
.name
)
96 res
+= "%s=%s;" % (self
.name
, fmtname
)
98 # sample bsv method definition :
100 method Action cell0_mux(Bit#(2) in);
105 # sample bsv wire (wire definiton):
107 Wire#(Bit#(2)) wrcell0_mux<-mkDWire(0);
110 def wirefmt(self
, fmtoutfn
, fmtinfn
, fmtdecfn
):
111 res
= ' Wire#(%s) ' % self
.bitspec
113 res
+= '%s' % fmtinfn(self
.name
)
115 res
+= '%s' % fmtoutfn(self
.name
)
116 res
+= "<-mkDWire(0);"
119 def ifacedef2(self
, fmtoutfn
, fmtinfn
, fmtdecfn
):
121 fmtname
= fmtinfn(self
.name
)
122 res
= " interface %s = interface Put\n" % self
.name_
125 #res += fmtdecfn(self.name)
126 res
+= '(%s in);\n' % self
.bitspec
127 res
+= ' %s<=in;\n' % fmtname
128 res
+= ' endmethod\n'
129 res
+= ' endinterface;'
131 fmtname
= fmtoutfn(self
.name
)
132 res
= " interface %s = interface Get\n" % self
.name_
133 res
+= ' method ActionValue#'
134 res
+= '(%s) get;\n' % self
.bitspec
135 res
+= " return %s;\n" % (fmtname
)
136 res
+= ' endmethod\n'
137 res
+= ' endinterface;'
140 class Interface(PeripheralIface
):
141 """ create an interface from a list of pinspecs.
142 each pinspec is a dictionary, see Pin class arguments
143 single indicates that there is only one of these, and
144 so the name must *not* be extended numerically (see pname)
146 # sample interface object:
148 twiinterface_decl = Interface('twi',
149 [{'name': 'sda', 'outen': True},
150 {'name': 'scl', 'outen': True},
154 def __init__(self
, ifacename
, pinspecs
, ganged
=None, single
=False):
155 PeripheralIface
.__init
__(self
, ifacename
)
156 self
.ifacename
= ifacename
157 self
.ganged
= ganged
or {}
158 self
.pins
= [] # a list of instances of class Pin
159 self
.pinspecs
= pinspecs
# a list of dictionary
167 if p
.get('outen') is True: # special case, generate 3 pins
169 for psuffix
in ['out', 'outen', 'in']:
170 # changing the name (like sda) to (twi_sda_out)
171 _p
['name_'] = "%s_%s" % (p
['name'], psuffix
)
172 _p
['name'] = "%s_%s" % (self
.pname(p
['name']), psuffix
)
173 _p
['action'] = psuffix
!= 'in'
174 self
.pins
.append(Pin(**_p
))
175 # will look like {'name': 'twi_sda_out', 'action': True}
176 # {'name': 'twi_sda_outen', 'action': True}
177 #{'name': 'twi_sda_in', 'action': False}
178 # NOTice - outen key is removed
180 _p
['name_'] = p
['name']
181 _p
['name'] = self
.pname(p
['name'])
182 self
.pins
.append(Pin(**_p
))
184 # sample interface object:
186 uartinterface_decl = Interface('uart',
188 {'name': 'tx', 'action': True},
192 getifacetype is called multiple times in actual_pinmux.py
193 x = ifaces.getifacetype(temp), where temp is uart_rx, spi_mosi
194 Purpose is to identify is function : input/output/inout
197 def getifacetype(self
, name
):
198 for p
in self
.pinspecs
:
199 fname
= "%s_%s" % (self
.ifacename
, p
['name'])
200 # print "search", self.ifacename, name, fname
210 """ generates the interface spec e.g. flexbus_ale
211 if there is only one flexbus interface, or
212 sd{0}_cmd if there are several. string format
213 function turns this into sd0_cmd, sd1_cmd as
214 appropriate. single mode stops the numerical extension.
217 return self
.ifacename
218 return '%s{0}' % self
.ifacename
220 def pname(self
, name
):
221 """ generates the interface spec e.g. flexbus_ale
222 if there is only one flexbus interface, or
223 sd{0}_cmd if there are several. string format
224 function turns this into sd0_cmd, sd1_cmd as
225 appropriate. single mode stops the numerical extension.
227 return "%s_%s" % (self
.iname(), name
)
229 def busfmt(self
, *args
):
230 """ this function creates a bus "ganging" system based
231 on input from the {interfacename}.txt file.
232 only inout pins that are under the control of the
233 interface may be "ganged" together.
236 return '' # when self.ganged is None
239 for (k
, pnames
) in self
.ganged
.items():
240 name
= self
.pname('%senable' % k
).format(*args
)
241 decl
= 'Bit#(1) %s = 0;' % name
244 for p
in self
.pinspecs
:
245 if p
['name'] not in pnames
:
247 pname
= self
.pname(p
['name']).format(*args
)
248 if p
.get('outen') is True:
249 outname
= self
.ifacefmtoutfn(pname
)
250 ganged
.append("%s_outen" % outname
) # match wirefmt
252 gangedfmt
= '{%s} = duplicate(%s);'
253 res
.append(gangedfmt
% (',\n '.join(ganged
), name
))
254 return '\n'.join(res
) + '\n\n'
256 def wirefmt(self
, *args
):
257 res
= '\n'.join(map(self
.wirefmtpin
, self
.pins
)).format(*args
)
261 def ifacepfmt(self
, *args
):
262 res
= '\n'.join(map(self
.ifacepfmtdecpin
, self
.pins
)).format(*args
)
263 return '\n' + res
# pins is a list
265 def ifacefmt(self
, *args
):
266 res
= '\n'.join(map(self
.ifacefmtdecpin
, self
.pins
)).format(*args
)
267 return '\n' + res
# pins is a list
269 def ifacepfmtdecfn(self
, name
):
272 def ifacefmtdecfn(self
, name
):
273 return name
# like: uart
275 def ifacefmtdecfn2(self
, name
):
276 return name
# like: uart
278 def ifacefmtdecfn3(self
, name
):
280 return "%s_outen" % name
# like uart_outen
282 def ifacefmtoutfn(self
, name
):
283 return "wr%s" % name
# like wruart
285 def ifacefmtinfn(self
, name
):
288 def wirefmtpin(self
, pin
):
289 return pin
.wirefmt(self
.ifacefmtoutfn
, self
.ifacefmtinfn
,
292 def ifacepfmtdecpin(self
, pin
):
293 return pin
.ifacepfmt(self
.ifacepfmtdecfn
)
295 def ifacefmtdecpin(self
, pin
):
296 return pin
.ifacefmt(self
.ifacefmtdecfn
)
298 def ifacefmtpin(self
, pin
):
299 decfn
= self
.ifacefmtdecfn2
300 outfn
= self
.ifacefmtoutfn
301 # print pin, pin.outenmode
303 decfn
= self
.ifacefmtdecfn3
304 outfn
= self
.ifacefmtoutenfn
305 return pin
.ifacedef(outfn
, self
.ifacefmtinfn
,
308 def ifacedef2pin(self
, pin
):
309 decfn
= self
.ifacefmtdecfn2
310 outfn
= self
.ifacefmtoutfn
311 # print pin, pin.outenmode
313 decfn
= self
.ifacefmtdecfn3
314 outfn
= self
.ifacefmtoutenfn
315 return pin
.ifacedef2(outfn
, self
.ifacefmtinfn
,
318 def ifacedef(self
, *args
):
319 res
= '\n'.join(map(self
.ifacefmtpin
, self
.pins
))
320 res
= res
.format(*args
)
321 return '\n' + res
+ '\n'
323 def ifacedef2(self
, *args
):
324 res
= '\n'.join(map(self
.ifacedef2pin
, self
.pins
))
325 res
= res
.format(*args
)
326 return '\n' + res
+ '\n'
329 class MuxInterface(Interface
):
331 def wirefmt(self
, *args
):
332 return muxwire
.format(*args
)
335 class IOInterface(Interface
):
337 def ifacefmtoutenfn(self
, name
):
338 return "cell{0}_mux_outen"
340 def ifacefmtoutfn(self
, name
):
341 """ for now strip off io{0}_ part """
342 return "cell{0}_mux_out"
344 def ifacefmtinfn(self
, name
):
345 return "cell{0}_mux_in"
347 def wirefmt(self
, *args
):
348 return generic_io
.format(*args
)
351 class Interfaces(InterfacesBase
, PeripheralInterfaces
):
352 """ contains a list of interface definitions
355 def __init__(self
, pth
=None):
356 InterfacesBase
.__init
__(self
, Interface
, pth
)
357 PeripheralInterfaces
.__init
__(self
)
359 def ifacedef(self
, f
, *args
):
360 for (name
, count
) in self
.ifacecount
:
361 for i
in range(count
):
362 f
.write(self
.data
[name
].ifacedef(i
))
364 def ifacedef2(self
, f
, *args
):
365 c
= " interface {0} = interface PeripheralSide{1}"
366 for (name
, count
) in self
.ifacecount
:
367 for i
in range(count
):
368 iname
= self
.data
[name
].iname().format(i
)
369 f
.write(c
.format(iname
, name
.upper()))
370 f
.write(self
.data
[name
].ifacedef2(i
))
371 f
.write(" endinterface;\n\n")
373 def busfmt(self
, f
, *args
):
374 f
.write("import BUtils::*;\n\n")
375 for (name
, count
) in self
.ifacecount
:
376 for i
in range(count
):
377 bf
= self
.data
[name
].busfmt(i
)
380 def ifacepfmt(self
, f
, *args
):
382 // interface declaration between {0} and pinmux
383 (*always_ready,always_enabled*)
384 interface PeripheralSide{0};'''
385 for (name
, count
) in self
.ifacecount
:
386 f
.write(comment
.format(name
.upper()))
387 f
.write(self
.data
[name
].ifacepfmt(0))
388 f
.write("\n endinterface\n")
390 def ifacefmt(self
, f
, *args
):
392 // interface declaration between %s-{0} and pinmux'''
393 for (name
, count
) in self
.ifacecount
:
394 for i
in range(count
):
395 c
= comment
% name
.upper()
397 f
.write(self
.data
[name
].ifacefmt(i
))
399 def ifacefmt2(self
, f
, *args
):
401 interface PeripheralSide{0} {1};'''
402 for (name
, count
) in self
.ifacecount
:
403 for i
in range(count
):
404 iname
= self
.data
[name
].iname().format(i
)
405 f
.write(comment
.format(name
.upper(), iname
))
407 def wirefmt(self
, f
, *args
):
408 comment
= '\n // following wires capture signals ' \
409 'to IO CELL if %s-{0} is\n' \
411 for (name
, count
) in self
.ifacecount
:
412 for i
in range(count
):
415 f
.write(self
.data
[name
].wirefmt(i
))
418 # ========= Interface declarations ================ #
420 mux_interface
= MuxInterface('cell',
421 [{'name': 'mux', 'ready': False, 'enabled': False,
422 'bitspec': '{1}', 'action': True}])
424 io_interface
= IOInterface(
426 [{'name': 'cell_out', 'enabled': True, },
427 {'name': 'cell_outen', 'enabled': True, 'outenmode': True, },
428 {'name': 'cell_in', 'action': True, 'io': True}, ])
430 # == Peripheral Interface definitions == #
431 # these are the interface of the peripherals to the pin mux
432 # Outputs from the peripherals will be inputs to the pinmux
433 # module. Hence the change in direction for most pins
435 # ======================================= #
438 if __name__
== '__main__':
440 uartinterface_decl
= Interface('uart',
442 {'name': 'tx', 'action': True},
445 twiinterface_decl
= Interface('twi',
446 [{'name': 'sda', 'outen': True},
447 {'name': 'scl', 'outen': True},
450 def _pinmunge(p
, sep
, repl
, dedupe
=True):
451 """ munges the text so it's easier to compare.
452 splits by separator, strips out blanks, re-joins.
457 p
= filter(lambda x
: x
, p
) # filter out blanks
461 """ munges the text so it's easier to compare.
463 # first join lines by semicolons, strip out returns
465 p
= map(lambda x
: x
.replace('\n', ''), p
)
467 # now split first by brackets, then spaces (deduping on spaces)
468 p
= _pinmunge(p
, "(", " ( ", False)
469 p
= _pinmunge(p
, ")", " ) ", False)
470 p
= _pinmunge(p
, " ", " ")
476 for p1
, p2
in zip(l1
, l2
):
482 ifaces
= Interfaces()
484 ifaceuart
= ifaces
['uart']
485 print (ifaceuart
.ifacedef(0))
486 print (uartinterface_decl
.ifacedef(0))
487 assert ifaceuart
.ifacedef(0) == uartinterface_decl
.ifacedef(0)
489 ifacetwi
= ifaces
['twi']
490 print (ifacetwi
.ifacedef(0))
491 print (twiinterface_decl
.ifacedef(0))
492 assert ifacetwi
.ifacedef(0) == twiinterface_decl
.ifacedef(0)