rework interface bus to multi-bus
[pinmux.git] / src / bsv / interface_decl.py
1 import os.path
2
3 try:
4 from UserDict import UserDict
5 except ImportError:
6 from collections import UserDict
7
8 from bsv.wire_def import generic_io # special case
9 from bsv.wire_def import muxwire # special case
10 from ifacebase import InterfacesBase
11 from bsv.peripheral_gen import PeripheralIface
12 from bsv.peripheral_gen import PeripheralInterfaces
13
14
15 class Pin(object):
16 """ pin interface declaration.
17 * name is the name of the pin
18 * ready, enabled and io all create a (* .... *) prefix
19 * action changes it to an "in" if true
20 """
21
22 def __init__(self, name,
23 name_=None,
24 idx=None,
25 ready=True,
26 enabled=True,
27 io=False,
28 action=False,
29 bitspec=None,
30 outenmode=False):
31 self.name = name
32 self.name_ = name_
33 self.idx = idx
34 self.ready = ready
35 self.enabled = enabled
36 self.io = io
37 self.action = action
38 self.bitspec = bitspec if bitspec else 'Bit#(1)'
39 self.outenmode = outenmode
40
41 # bsv will look like this (method declaration):
42 """
43 (*always_ready,always_enabled*) method Bit#(1) io0_cell_outen;
44 (*always_ready,always_enabled,result="io"*) method
45 Action io0_inputval (Bit#(1) in);
46 """
47
48 def ifacepfmt(self, fmtfn):
49 res = ' '
50 status = []
51 res += "interface "
52 name = fmtfn(self.name_)
53 if self.action:
54 res += "Put"
55 else:
56 res += "Get"
57 res += "#(%s) %s;" % (self.bitspec, name)
58 return res
59
60 def ifacefmt(self, fmtfn):
61 res = ' '
62 status = []
63 if self.ready:
64 status.append('always_ready')
65 if self.enabled:
66 status.append('always_enabled')
67 if self.io:
68 status.append('result="io"')
69 if status:
70 res += '(*'
71 res += ','.join(status)
72 res += '*)'
73 res += " method "
74 if self.io:
75 res += "\n "
76 name = fmtfn(self.name)
77 if self.action:
78 res += " Action "
79 res += name
80 res += ' (%s in)' % self.bitspec
81 else:
82 res += " %s " % self.bitspec
83 res += name
84 res += ";"
85 return res
86
87 def ifacedef(self, fmtoutfn, fmtinfn, fmtdecfn):
88 res = ' method '
89 if self.action:
90 fmtname = fmtinfn(self.name)
91 res += "Action "
92 res += fmtdecfn(self.name)
93 res += '(%s in);\n' % self.bitspec
94 res += ' %s<=in;\n' % fmtname
95 res += ' endmethod'
96 else:
97 fmtname = fmtoutfn(self.name)
98 res += "%s=%s;" % (self.name, fmtname)
99 return res
100 # sample bsv method definition :
101 """
102 method Action cell0_mux(Bit#(2) in);
103 wrcell0_mux<=in;
104 endmethod
105 """
106
107 # sample bsv wire (wire definiton):
108 """
109 Wire#(Bit#(2)) wrcell0_mux<-mkDWire(0);
110 """
111
112 def wirefmt(self, fmtoutfn, fmtinfn, fmtdecfn):
113 res = ' Wire#(%s) ' % self.bitspec
114 if self.action:
115 res += '%s' % fmtinfn(self.name)
116 else:
117 res += '%s' % fmtoutfn(self.name)
118 res += "<-mkDWire(0);"
119 return res
120
121 def ifacedef2(self, fmtoutfn, fmtinfn, fmtdecfn):
122 if self.action:
123 fmtname = fmtinfn(self.name)
124 res = " interface %s = interface Put\n" % self.name_
125 res += ' method '
126 res += "Action put"
127 #res += fmtdecfn(self.name)
128 res += '(%s in);\n' % self.bitspec
129 res += ' %s<=in;\n' % fmtname
130 res += ' endmethod\n'
131 res += ' endinterface;'
132 else:
133 fmtname = fmtoutfn(self.name)
134 res = " interface %s = interface Get\n" % self.name_
135 res += ' method ActionValue#'
136 res += '(%s) get;\n' % self.bitspec
137 res += " return %s;\n" % (fmtname)
138 res += ' endmethod\n'
139 res += ' endinterface;'
140 return res
141
142 def ifacedef3(self, idx, fmtoutfn, fmtinfn, fmtdecfn):
143 if self.action:
144 fmtname = fmtinfn(self.name)
145 if self.name.endswith('outen'):
146 name = "tputen"
147 else:
148 name = "tput"
149 res = " %s <= in[%d];" % (fmtname, idx)
150 else:
151 fmtname = fmtoutfn(self.name)
152 res = " tget[%d] = %s;" % (idx, fmtname)
153 name = 'tget'
154 return (name, res)
155
156
157 class InterfaceFmt(object):
158
159 def ifacepfmtdecpin(self, pin):
160 return pin.ifacepfmt(self.ifacepfmtdecfn)
161
162 def ifacepfmtdecfn(self, name):
163 return name
164
165 class Interface(PeripheralIface, InterfaceFmt):
166 """ create an interface from a list of pinspecs.
167 each pinspec is a dictionary, see Pin class arguments
168 single indicates that there is only one of these, and
169 so the name must *not* be extended numerically (see pname)
170 """
171 # sample interface object:
172 """
173 twiinterface_decl = Interface('twi',
174 [{'name': 'sda', 'outen': True},
175 {'name': 'scl', 'outen': True},
176 ])
177 """
178
179 def __init__(self, ifacename, pinspecs, ganged=None, single=False):
180 PeripheralIface.__init__(self, ifacename)
181 InterfaceFmt.__init__(self)
182 self.ifacename = ifacename
183 self.ganged = ganged or {}
184 self.pins = [] # a list of instances of class Pin
185 self.pinspecs = pinspecs # a list of dictionary
186 self.single = single
187
188 for idx, p in enumerate(pinspecs):
189 _p = {}
190 _p.update(p)
191 if 'type' in _p:
192 del _p['type']
193 if p.get('outen') is True: # special case, generate 3 pins
194 del _p['outen']
195 for psuffix in ['out', 'outen', 'in']:
196 # changing the name (like sda) to (twi_sda_out)
197 _p['name_'] = "%s_%s" % (p['name'], psuffix)
198 _p['name'] = "%s_%s" % (self.pname(p['name']), psuffix)
199 _p['action'] = psuffix != 'in'
200 _p['idx'] = idx
201 self.pins.append(Pin(**_p))
202 # will look like {'name': 'twi_sda_out', 'action': True}
203 # {'name': 'twi_sda_outen', 'action': True}
204 #{'name': 'twi_sda_in', 'action': False}
205 # NOTice - outen key is removed
206 else:
207 name = p['name']
208 if name.isdigit(): # HACK! deals with EINT case
209 name = self.pname(name)
210 _p['name_'] = name
211 _p['idx'] = idx
212 _p['name'] = self.pname(p['name'])
213 self.pins.append(Pin(**_p))
214
215 # sample interface object:
216 """
217 uartinterface_decl = Interface('uart',
218 [{'name': 'rx'},
219 {'name': 'tx', 'action': True},
220 ])
221 """
222 """
223 getifacetype is called multiple times in actual_pinmux.py
224 x = ifaces.getifacetype(temp), where temp is uart_rx, spi_mosi
225 Purpose is to identify is function : input/output/inout
226 """
227
228 def getifacetype(self, name):
229 for p in self.pinspecs:
230 fname = "%s_%s" % (self.ifacename, p['name'])
231 # print "search", self.ifacename, name, fname
232 if fname == name:
233 if p.get('action'):
234 return 'out'
235 elif p.get('outen'):
236 return 'inout'
237 return 'input'
238 return None
239
240 def iname(self):
241 """ generates the interface spec e.g. flexbus_ale
242 if there is only one flexbus interface, or
243 sd{0}_cmd if there are several. string format
244 function turns this into sd0_cmd, sd1_cmd as
245 appropriate. single mode stops the numerical extension.
246 """
247 if self.single:
248 return self.ifacename
249 return '%s{0}' % self.ifacename
250
251 def pname(self, name):
252 """ generates the interface spec e.g. flexbus_ale
253 if there is only one flexbus interface, or
254 sd{0}_cmd if there are several. string format
255 function turns this into sd0_cmd, sd1_cmd as
256 appropriate. single mode stops the numerical extension.
257 """
258 return "%s_%s" % (self.iname(), name)
259
260 def busfmt(self, *args):
261 """ this function creates a bus "ganging" system based
262 on input from the {interfacename}.txt file.
263 only inout pins that are under the control of the
264 interface may be "ganged" together.
265 """
266 if not self.ganged:
267 return '' # when self.ganged is None
268 # print self.ganged
269 res = []
270 for (k, pnames) in self.ganged.items():
271 name = self.pname('%senable' % k).format(*args)
272 decl = 'Bit#(1) %s = 0;' % name
273 res.append(decl)
274 ganged = []
275 for p in self.pinspecs:
276 if p['name'] not in pnames:
277 continue
278 pname = self.pname(p['name']).format(*args)
279 if p.get('outen') is True:
280 outname = self.ifacefmtoutfn(pname)
281 ganged.append("%s_outen" % outname) # match wirefmt
282
283 gangedfmt = '{%s} = duplicate(%s);'
284 res.append(gangedfmt % (',\n '.join(ganged), name))
285 return '\n'.join(res) + '\n\n'
286
287 def wirefmt(self, *args):
288 res = '\n'.join(map(self.wirefmtpin, self.pins)).format(*args)
289 res += '\n'
290 return '\n' + res
291
292 def ifacepfmt(self, *args):
293 res = '\n'.join(map(self.ifacepfmtdecpin, self.pins)).format(*args)
294 return '\n' + res # pins is a list
295
296 def ifacefmt(self, *args):
297 res = '\n'.join(map(self.ifacefmtdecpin, self.pins)).format(*args)
298 return '\n' + res # pins is a list
299
300 def ifacefmtdecfn(self, name):
301 return name # like: uart
302
303 def ifacefmtdecfn2(self, name):
304 return name # like: uart
305
306 def ifacefmtdecfn3(self, name):
307 """ HACK! """
308 return "%s_outen" % name # like uart_outen
309
310 def ifacefmtoutfn(self, name):
311 return "wr%s" % name # like wruart
312
313 def ifacefmtinfn(self, name):
314 return "wr%s" % name
315
316 def wirefmtpin(self, pin):
317 return pin.wirefmt(self.ifacefmtoutfn, self.ifacefmtinfn,
318 self.ifacefmtdecfn2)
319
320 def ifacefmtdecpin(self, pin):
321 return pin.ifacefmt(self.ifacefmtdecfn)
322
323 def ifacefmtpin(self, pin):
324 decfn = self.ifacefmtdecfn2
325 outfn = self.ifacefmtoutfn
326 # print pin, pin.outenmode
327 if pin.outenmode:
328 decfn = self.ifacefmtdecfn3
329 outfn = self.ifacefmtoutenfn
330 return pin.ifacedef(outfn, self.ifacefmtinfn,
331 decfn)
332
333 def ifacedef2pin(self, pin):
334 decfn = self.ifacefmtdecfn2
335 outfn = self.ifacefmtoutfn
336 # print pin, pin.outenmode
337 if pin.outenmode:
338 decfn = self.ifacefmtdecfn3
339 outfn = self.ifacefmtoutenfn
340 return pin.ifacedef2(outfn, self.ifacefmtinfn,
341 decfn)
342
343 def ifacedef(self, *args):
344 res = '\n'.join(map(self.ifacefmtpin, self.pins))
345 res = res.format(*args)
346 return '\n' + res + '\n'
347
348 def ifacedef2(self, *args):
349 res = '\n'.join(map(self.ifacedef2pin, self.pins))
350 res = res.format(*args)
351 return '\n' + res + '\n'
352
353 def vectorifacedef2(self, pins, count, names, bitfmt, *args):
354 tput = []
355 tget = []
356 tputen = []
357 # XXX HACK! assume in, out and inout, create set of indices
358 # that are repeated three times.
359 plens = []
360 # ARG even worse hack for LCD *sigh*...
361 if names[1] is None and names[2] is None:
362 plens = range(len(pins))
363 else:
364 for i in range(0, len(pins), 3):
365 plens += [i / 3, i / 3, i / 3]
366 for (typ, txt) in map(self.ifacedef3pin, plens, pins):
367 if typ == 'tput':
368 tput.append(txt)
369 elif typ == 'tget':
370 tget.append(txt)
371 elif typ == 'tputen':
372 tputen.append(txt)
373 tput = '\n'.join(tput).format(*args)
374 tget = '\n'.join(tget).format(*args)
375 tputen = '\n'.join(tputen).format(*args)
376 bitfmt = bitfmt.format(count)
377 template = ["""\
378 interface {3} = interface Put#({0})
379 method Action put({2} in);
380 {1}
381 endmethod
382 endinterface;
383 """,
384 """\
385 interface {3} = interface Put#({0})
386 method Action put({2} in);
387 {1}
388 endmethod
389 endinterface;
390 """,
391 """\
392 interface {3} = interface Get#({0})
393 method ActionValue#({2}) get;
394 {2} tget;
395 {1}
396 return tget;
397 endmethod
398 endinterface;
399 """]
400 res = ''
401 tlist = [tput, tputen, tget]
402 for i, n in enumerate(names):
403 if n:
404 res += template[i].format(count, tlist[i], bitfmt, n)
405 return '\n' + res + '\n'
406
407
408 class MuxInterface(Interface):
409
410 def wirefmt(self, *args):
411 return muxwire.format(*args)
412
413
414 class IOInterface(Interface):
415
416 def ifacefmtoutenfn(self, name):
417 return "cell{0}_mux_outen"
418
419 def ifacefmtoutfn(self, name):
420 """ for now strip off io{0}_ part """
421 return "cell{0}_mux_out"
422
423 def ifacefmtinfn(self, name):
424 return "cell{0}_mux_in"
425
426 def wirefmt(self, *args):
427 return generic_io.format(*args)
428
429
430 class InterfaceBus(InterfaceFmt):
431
432 def __init__(self, pins, is_inout, namelist, bitspec, filterbus):
433 InterfaceFmt.__init__(self)
434 self.namelist = namelist
435 self.bitspec = bitspec
436 self.fbus = filterbus # filter identifying which are bus pins
437 self.pins_ = pins
438 self.is_inout = is_inout
439 self.buspins = filter(lambda x: x.name_.startswith(self.fbus),
440 self.pins_)
441 self.nonbuspins = filter(lambda x: not x.name_.startswith(self.fbus),
442 self.pins_)
443
444 def get_nonbuspins(self):
445 return self.nonbuspins
446
447 def get_buspins(self):
448 return self.buspins
449
450 def get_n_iopinsdiv(self):
451 return 3 if self.is_inout else 1
452
453 def ifacepfmt(self, *args):
454 pins = self.get_nonbuspins()
455 res = '\n'.join(map(self.ifacepfmtdecpin, pins)).format(*args)
456 res = res.format(*args)
457
458 pins = self.get_buspins()
459 plen = len(pins) / self.get_n_iopinsdiv()
460
461 res += '\n'
462 template = " interface {1}#(%s) {2};\n" % self.bitspec
463 for i, n in enumerate(self.namelist):
464 if not n:
465 continue
466 ftype = 'Get' if i == 2 else "Put"
467 res += template.format(plen, ftype, n)
468
469 return "\n" + res
470
471 def ifacedef2(self, *args):
472 pins = self.get_nonbuspins()
473 res = '\n'.join(map(self.ifacedef2pin, pins))
474 res = res.format(*args)
475
476 pins = self.get_buspins()
477 plen = len(pins) / self.get_n_iopinsdiv()
478 for pin in pins:
479 print "ifbus pins", pin.name_, plen
480 bitspec = self.bitspec.format(plen)
481 print self
482 return '\n' + res + self.vectorifacedef2(
483 pins, plen, self.namelist, bitspec, *args) + '\n'
484
485 def ifacedef3pin(self, idx, pin):
486 decfn = self.ifacefmtdecfn2
487 outfn = self.ifacefmtoutfn
488 # print pin, pin.outenmode
489 if pin.outenmode:
490 decfn = self.ifacefmtdecfn3
491 outfn = self.ifacefmtoutenfn
492 return pin.ifacedef3(idx, outfn, self.ifacefmtinfn,
493 decfn)
494
495
496 class InterfaceMultiBus(object):
497
498 def __init__(self, pins):
499 self.multibus_specs = []
500 self.nonbuspins = pins
501 self.nonb = self.add_bus(False, [], '', "xxxxxxxnofilter")
502
503 def add_bus(self, is_inout, namelist, bitspec, filterbus):
504 pins = self.nonbuspins
505 buspins = filter(lambda x: x.name_.startswith(filterbus), pins)
506 nbuspins = filter(lambda x: not x.name_.startswith(filterbus), pins)
507 self.nonbuspins = nbuspins
508 b = InterfaceBus(buspins, is_inout,
509 namelist, bitspec, filterbus)
510 print is_inout, namelist, filterbus, buspins
511 self.multibus_specs.append(b)
512 self.multibus_specs[0].pins_ = nbuspins
513 self.multibus_specs[0].nonbuspins = nbuspins
514
515 def ifacepfmt(self, *args):
516 res = Interface.ifacepfmt(self, *args)
517 return res
518 for b in self.multibus_specs:
519 res += b.ifacepfmt(*args)
520 return res
521
522 def ifacedef2(self, *args):
523 res = Interface.ifacedef2(self, *args)
524 return res
525 for b in self.multibus_specs:
526 res += b.ifacedef2(*args)
527 return res
528
529
530 class InterfaceLCD(InterfaceBus, Interface):
531
532 def __init__(self, *args):
533 Interface.__init__(self, *args)
534 InterfaceBus.__init__(self, self.pins, False, ['data_out', None, None],
535 "Bit#({0})", "out")
536
537 class InterfaceFlexBus(InterfaceMultiBus, Interface):
538
539 def __init__(self, ifacename, pinspecs, ganged=None, single=False):
540 Interface.__init__(self, ifacename, pinspecs, ganged, single)
541 InterfaceMultiBus.__init__(self, self.pins)
542 self.add_bus(True, ['ad_out', 'ad_out_en', 'ad_in'],
543 "Bit#({0})", "ad")
544 self.add_bus(True, ['bwe', None, None],
545 "Bit#({0})", "bwe")
546
547 def ifacedef2(self, *args):
548 return InterfaceMultiBus.ifacedef2(self, *args)
549
550 class InterfaceSD(InterfaceBus, Interface):
551
552 def __init__(self, *args):
553 Interface.__init__(self, *args)
554 InterfaceBus.__init__(self, self.pins, True, ['out', 'out_en', 'in'],
555 "Bit#({0})", "d")
556
557 class InterfaceNSPI(InterfaceBus, Interface):
558
559 def __init__(self, *args):
560 Interface.__init__(self, *args)
561 InterfaceBus.__init__(self, self.pins, True,
562 ['io_out', 'io_out_en', 'io_in'],
563 "Bit#({0})", "io")
564
565 class InterfaceEINT(Interface):
566 """ uses old-style (non-get/put) for now
567 """
568
569 def ifacepfmt(self, *args):
570 res = '\n'.join(map(self.ifacefmtdecpin, self.pins)).format(*args)
571 return '\n' + res # pins is a list
572
573 def ifacedef2(self, *args):
574 return self.ifacedef(*args)
575
576
577 class InterfaceGPIO(InterfaceBus, Interface):
578 """ note: the busfilter cuts out everything as the entire set of pins
579 is a bus, but it's less code. get_nonbuspins returns empty list.
580 """
581
582 def __init__(self, ifacename, pinspecs, ganged=None, single=False):
583 Interface.__init__(self, ifacename, pinspecs, ganged, single)
584 InterfaceBus.__init__(self, self.pins, True, ['out', 'out_en', 'in'],
585 "Vector#({0},Bit#(1))", ifacename[-1])
586
587 class Interfaces(InterfacesBase, PeripheralInterfaces):
588 """ contains a list of interface definitions
589 """
590
591 def __init__(self, pth=None):
592 InterfacesBase.__init__(self, Interface, pth,
593 {'gpio': InterfaceGPIO,
594 'spi': InterfaceNSPI,
595 'mspi': InterfaceNSPI,
596 'lcd': InterfaceLCD,
597 'sd': InterfaceSD,
598 'fb': InterfaceFlexBus,
599 'qspi': InterfaceNSPI,
600 'mqspi': InterfaceNSPI,
601 'eint': InterfaceEINT})
602 PeripheralInterfaces.__init__(self)
603
604 def ifacedef(self, f, *args):
605 for (name, count) in self.ifacecount:
606 for i in range(count):
607 f.write(self.data[name].ifacedef(i))
608
609 def ifacedef2(self, f, *args):
610 c = " interface {0} = interface PeripheralSide{1}"
611 for (name, count) in self.ifacecount:
612 for i in range(count):
613 iname = self.data[name].iname().format(i)
614 f.write(c.format(iname, name.upper()))
615 f.write(self.data[name].ifacedef2(i))
616 f.write(" endinterface;\n\n")
617
618 def busfmt(self, f, *args):
619 f.write("import BUtils::*;\n\n")
620 for (name, count) in self.ifacecount:
621 for i in range(count):
622 bf = self.data[name].busfmt(i)
623 f.write(bf)
624
625 def ifacepfmt(self, f, *args):
626 comment = '''
627 // interface declaration between {0} and pinmux
628 (*always_ready,always_enabled*)
629 interface PeripheralSide{0};'''
630 for (name, count) in self.ifacecount:
631 f.write(comment.format(name.upper()))
632 f.write(self.data[name].ifacepfmt(0))
633 f.write("\n endinterface\n")
634
635 def ifacefmt(self, f, *args):
636 comment = '''
637 // interface declaration between %s-{0} and pinmux'''
638 for (name, count) in self.ifacecount:
639 for i in range(count):
640 c = comment % name.upper()
641 f.write(c.format(i))
642 f.write(self.data[name].ifacefmt(i))
643
644 def ifacefmt2(self, f, *args):
645 comment = '''
646 interface PeripheralSide{0} {1};'''
647 for (name, count) in self.ifacecount:
648 for i in range(count):
649 iname = self.data[name].iname().format(i)
650 f.write(comment.format(name.upper(), iname))
651
652 def wirefmt(self, f, *args):
653 comment = '\n // following wires capture signals ' \
654 'to IO CELL if %s-{0} is\n' \
655 ' // allotted to it'
656 for (name, count) in self.ifacecount:
657 for i in range(count):
658 c = comment % name
659 f.write(c.format(i))
660 f.write(self.data[name].wirefmt(i))
661
662
663 # ========= Interface declarations ================ #
664
665 mux_interface = MuxInterface('cell',
666 [{'name': 'mux', 'ready': False, 'enabled': False,
667 'bitspec': '{1}', 'action': True}])
668
669 io_interface = IOInterface(
670 'io',
671 [{'name': 'cell_out', 'enabled': True, },
672 {'name': 'cell_outen', 'enabled': True, 'outenmode': True, },
673 {'name': 'cell_in', 'action': True, 'io': True}, ])
674
675 # == Peripheral Interface definitions == #
676 # these are the interface of the peripherals to the pin mux
677 # Outputs from the peripherals will be inputs to the pinmux
678 # module. Hence the change in direction for most pins
679
680 # ======================================= #
681
682 # basic test
683 if __name__ == '__main__':
684
685 uartinterface_decl = Interface('uart',
686 [{'name': 'rx'},
687 {'name': 'tx', 'action': True},
688 ])
689
690 twiinterface_decl = Interface('twi',
691 [{'name': 'sda', 'outen': True},
692 {'name': 'scl', 'outen': True},
693 ])
694
695 def _pinmunge(p, sep, repl, dedupe=True):
696 """ munges the text so it's easier to compare.
697 splits by separator, strips out blanks, re-joins.
698 """
699 p = p.strip()
700 p = p.split(sep)
701 if dedupe:
702 p = filter(lambda x: x, p) # filter out blanks
703 return repl.join(p)
704
705 def pinmunge(p):
706 """ munges the text so it's easier to compare.
707 """
708 # first join lines by semicolons, strip out returns
709 p = p.split(";")
710 p = map(lambda x: x.replace('\n', ''), p)
711 p = '\n'.join(p)
712 # now split first by brackets, then spaces (deduping on spaces)
713 p = _pinmunge(p, "(", " ( ", False)
714 p = _pinmunge(p, ")", " ) ", False)
715 p = _pinmunge(p, " ", " ")
716 return p
717
718 def zipcmp(l1, l2):
719 l1 = l1.split("\n")
720 l2 = l2.split("\n")
721 for p1, p2 in zip(l1, l2):
722 print (repr(p1))
723 print (repr(p2))
724 print ()
725 assert p1 == p2
726
727 ifaces = Interfaces()
728
729 ifaceuart = ifaces['uart']
730 print (ifaceuart.ifacedef(0))
731 print (uartinterface_decl.ifacedef(0))
732 assert ifaceuart.ifacedef(0) == uartinterface_decl.ifacedef(0)
733
734 ifacetwi = ifaces['twi']
735 print (ifacetwi.ifacedef(0))
736 print (twiinterface_decl.ifacedef(0))
737 assert ifacetwi.ifacedef(0) == twiinterface_decl.ifacedef(0)