src/bsv/peripheral_gen.py

   1 import types
   2 from copy import deepcopy
   3
   4
   5 class PBase(object):
   6     def __init__(self, name):
   7         self.name = name
   8
   9     def axibase(self, name, ifacenum):
  10         name = name.upper()
  11         return "%(name)s%(ifacenum)dBase" % locals()
  12
  13     def axiend(self, name, ifacenum):
  14         name = name.upper()
  15         return "%(name)s%(ifacenum)dEnd" % locals()
  16
  17     def axi_reg_def(self, start, name, ifacenum):
  18         name = name.upper()
  19         offs = self.num_axi_regs32() * 4 * 16
  20         end = start + offs - 1
  21         bname = self.axibase(name, ifacenum)
  22         bend = self.axiend(name, ifacenum)
  23         comment = "%d 32-bit regs" % self.num_axi_regs32()
  24         return ("    `define %(bname)s 'h%(start)08X\n"
  25                 "    `define %(bend)s  'h%(end)08X // %(comment)s" % locals(),
  26                 offs)
  27
  28     def axi_slave_name(self, name, ifacenum):
  29         name = name.upper()
  30         return "{0}{1}_slave_num".format(name, ifacenum)
  31
  32     def axi_slave_idx(self, idx, name, ifacenum):
  33         name = self.axi_slave_name(name, ifacenum)
  34         return ("typedef {0} {1};".format(idx, name), 1)
  35
  36     def axi_addr_map(self, name, ifacenum):
  37         bname = self.axibase(name, ifacenum)
  38         bend = self.axiend(name, ifacenum)
  39         name = self.axi_slave_name(name, ifacenum)
  40         return """\
  41         if(addr>=`{0} && addr<=`{1})
  42             return tuple2(True,fromInteger(valueOf({2})));
  43         else""".format(bname, bend, name)
  44
  45     def mk_pincon(self, name, count):
  46         # TODO: really should be using bsv.interface_decl.Interfaces
  47         # pin-naming rules.... logic here is hard-coded to duplicate
  48         # it (see Interface.__init__ outen)
  49         ret = []
  50         for p in self.peripheral.pinspecs:
  51             typ = p['type']
  52             pname = p['name']
  53             #n = "{0}{1}".format(self.name, self.mksuffix(name, count))
  54             n = name  # "{0}{1}".format(self.name, self.mksuffix(name, count))
  55             ret.append("    //%s %s" % (n, str(p)))
  56             sname = self.peripheral.pname(pname).format(count)
  57             ps = "pinmux.peripheral_side.%s" % sname
  58             if typ == 'out' or typ == 'inout':
  59                 ret.append("    rule con_%s%d_%s_out;" % (name, count, pname))
  60                 fname = self.pinname_out(pname)
  61                 if fname:
  62                     if p.get('outen'):
  63                         ps_ = ps + '_out'
  64                     else:
  65                         ps_ = ps
  66                     if not n.startswith('gpio'): # XXX EURGH! horrible hack
  67                       n_ = "{0}{1}".format(n, count)
  68                     else:
  69                       n_ = n
  70                     ret.append("      {0}({1}.{2});".format(ps_, n_, fname))
  71                 fname = None
  72                 if p.get('outen'):
  73                     fname = self.pinname_outen(pname)
  74                 if fname:
  75                     if isinstance(fname, str):
  76                         fname = "{0}{1}.{2}".format(n, count, fname)
  77                     fname = self.pinname_tweak(pname, 'outen', fname)
  78                     ret.append("      {0}_outen({1});".format(ps, fname))
  79                 ret.append("    endrule")
  80             if typ == 'in' or typ == 'inout':
  81                 fname = self.pinname_in(pname)
  82                 if fname:
  83                     if p.get('outen'):
  84                         ps_ = ps + '_in'
  85                     else:
  86                         ps_ = ps
  87                     ret.append(
  88                         "    rule con_%s%d_%s_in;" %
  89                         (name, count, pname))
  90                     n_ = "{0}{1}".format(n, count)
  91                     ret.append("      {1}.{2}({0});".format(ps_, n_, fname))
  92                     ret.append("    endrule")
  93         return '\n'.join(ret)
  94
  95     def mk_cellconn(self, *args):
  96         return ''
  97
  98     def mkslow_peripheral(self, size=0):
  99         return ''
 100
 101     def mksuffix(self, name, i):
 102         return i
 103
 104     def __mk_connection(self, con, aname):
 105         txt = "        mkConnection (slow_fabric.v_to_slaves\n" + \
 106             "                    [fromInteger(valueOf({1}))],\n" + \
 107             "                    {0});"
 108
 109         print "PBase __mk_connection", self.name, aname
 110         if not con:
 111             return ''
 112         return txt.format(con, aname)
 113
 114     def mk_connection(self, count, name=None):
 115         if name is None:
 116             name = self.name
 117         print "PBase mk_conn", self.name, count
 118         aname = self.axi_slave_name(name, count)
 119         #dname = self.mksuffix(name, count)
 120         #dname = "{0}{1}".format(name, dname)
 121         con = self._mk_connection(name, count).format(count, aname)
 122         return self.__mk_connection(con, aname)
 123
 124     def _mk_connection(self, name=None, count=0):
 125         return ''
 126
 127     def pinname_out(self, pname):
 128         return ''
 129
 130     def pinname_in(self, pname):
 131         return ''
 132
 133     def pinname_outen(self, pname):
 134         return ''
 135
 136     def pinname_tweak(self, pname, typ, txt):
 137         return txt
 138
 139
 140 class uart(PBase):
 141
 142     def slowimport(self):
 143         return "          import Uart_bs         :: *;\n" + \
 144                "          import RS232_modified::*;"
 145
 146     def slowifdecl(self):
 147         return "            interface RS232 uart{0}_coe;\n" + \
 148                "            method Bit#(1) uart{0}_intr;"
 149
 150     def num_axi_regs32(self):
 151         return 8
 152
 153     def mkslow_peripheral(self, size=0):
 154         return "        Ifc_Uart_bs uart{0} <- \n" + \
 155                "                mkUart_bs(clocked_by uart_clock,\n" + \
 156                "                    reset_by uart_reset, sp_clock, sp_reset);"
 157
 158     def _mk_connection(self, name=None, count=0):
 159         return "uart{0}.slave_axi_uart"
 160
 161     def pinname_out(self, pname):
 162         return {'tx': 'coe_rs232.sout'}.get(pname, '')
 163
 164     def pinname_in(self, pname):
 165         return {'rx': 'coe_rs232.sin'}.get(pname, '')
 166
 167
 168 class qquart(PBase):
 169
 170     def slowimport(self):
 171         return "          import Uart16550         :: *;"
 172
 173     def slowifdecl(self):
 174         return "            interface RS232_PHY_Ifc uart{0}_coe;\n" + \
 175                "            method Bit#(1) uart{0}_intr;"
 176
 177     def num_axi_regs32(self):
 178         return 8
 179
 180     def mkslow_peripheral(self, size=0):
 181         return "        Uart16550_AXI4_Lite_Ifc uart{0} <- \n" + \
 182                "                mkUart16550(clocked_by uart_clock,\n" + \
 183                "                    reset_by uart_reset, sp_clock, sp_reset);"
 184
 185     def _mk_connection(self, name=None, count=0):
 186         return "uart{0}.slave_axi_uart"
 187
 188     def pinname_out(self, pname):
 189         return {'tx': 'coe_rs232.sout'}.get(pname, '')
 190
 191     def pinname_in(self, pname):
 192         return {'rx': 'coe_rs232.sin'}.get(pname, '')
 193
 194
 195 class rs232(PBase):
 196
 197     def slowimport(self):
 198         return "        import Uart_bs::*;\n" + \
 199                "        import RS232_modified::*;"
 200
 201     def slowifdecl(self):
 202         return "            interface RS232 uart{0}_coe;"
 203
 204     def num_axi_regs32(self):
 205         return 2
 206
 207     def mkslow_peripheral(self, size=0):
 208         return "        //Ifc_Uart_bs uart{0} <-" + \
 209                "        //       mkUart_bs(clocked_by uart_clock,\n" + \
 210                "        //          reset_by uart_reset,sp_clock, sp_reset);" +\
 211                "        Ifc_Uart_bs uart{0} <-" + \
 212                "                mkUart_bs(clocked_by sp_clock,\n" + \
 213                "                    reset_by sp_reset, sp_clock, sp_reset);"
 214
 215     def _mk_connection(self, name=None, count=0):
 216         return "uart{0}.slave_axi_uart"
 217
 218     def pinname_out(self, pname):
 219         return {'tx': 'coe_rs232.sout'}.get(pname, '')
 220
 221     def pinname_in(self, pname):
 222         return {'rx': 'coe_rs232.sin'}.get(pname, '')
 223
 224
 225 class twi(PBase):
 226
 227     def slowimport(self):
 228         return "        import I2C_top           :: *;"
 229
 230     def slowifdecl(self):
 231         return "            interface I2C_out twi{0}_out;\n" + \
 232                "            method Bit#(1) twi{0}_isint;"
 233
 234     def num_axi_regs32(self):
 235         return 8
 236
 237     def mkslow_peripheral(self, size=0):
 238         return "        I2C_IFC twi{0} <- mkI2CController();"
 239
 240     def _mk_connection(self, name=None, count=0):
 241         return "twi{0}.slave_i2c_axi"
 242
 243     def pinname_out(self, pname):
 244         return {'sda': 'out.sda_out',
 245                 'scl': 'out.scl_out'}.get(pname, '')
 246
 247     def pinname_in(self, pname):
 248         return {'sda': 'out.sda_in',
 249                 'scl': 'out.scl_in'}.get(pname, '')
 250
 251     def pinname_outen(self, pname):
 252         return {'sda': 'out.sda_out_en',
 253                 'scl': 'out.scl_out_en'}.get(pname, '')
 254
 255     def pinname_tweak(self, pname, typ, txt):
 256         if typ == 'outen':
 257             return "pack({0})".format(txt)
 258         return txt
 259
 260
 261 class qspi(PBase):
 262
 263     def slowimport(self):
 264         return "        import qspi              :: *;"
 265
 266     def slowifdecl(self):
 267         return "            interface QSPI_out qspi{0}_out;\n" + \
 268                "            method Bit#(1) qspi{0}_isint;"
 269
 270     def num_axi_regs32(self):
 271         return 13
 272
 273     def mkslow_peripheral(self, size=0):
 274         return "        Ifc_qspi qspi{0} <-  mkqspi();"
 275
 276     def _mk_connection(self, name=None, count=0):
 277         return "qspi{0}.slave"
 278
 279     def pinname_out(self, pname):
 280         return {'ck': 'out.clk_o',
 281                 'nss': 'out.ncs_o',
 282                 'io0': 'out.io_o[0]',
 283                 'io1': 'out.io_o[1]',
 284                 'io2': 'out.io_o[2]',
 285                 'io3': 'out.io_o[3]',
 286                 }.get(pname, '')
 287
 288     def pinname_outen(self, pname):
 289         return {'ck': 1,
 290                 'nss': 1,
 291                 'io0': 'out.io_enable[0]',
 292                 'io1': 'out.io_enable[1]',
 293                 'io2': 'out.io_enable[2]',
 294                 'io3': 'out.io_enable[3]',
 295                 }.get(pname, '')
 296
 297     def mk_pincon(self, name, count):
 298         ret = [PBase.mk_pincon(self, name, count)]
 299         # special-case for gpio in, store in a temporary vector
 300         plen = len(self.peripheral.pinspecs)
 301         ret.append("    // XXX NSS and CLK are hard-coded master")
 302         ret.append("    // TODO: must add qspi slave-mode")
 303         ret.append("    // all ins done in one rule from 4-bitfield")
 304         ret.append("    rule con_%s%d_io_in;" % (name, count))
 305         ret.append("       {0}{1}.out.io_i({{".format(name, count))
 306         for i, p in enumerate(self.peripheral.pinspecs):
 307             typ = p['type']
 308             pname = p['name']
 309             if not pname.startswith('io'):
 310                 continue
 311             idx = pname[1:]
 312             n = name
 313             sname = self.peripheral.pname(pname).format(count)
 314             ps = "pinmux.peripheral_side.%s_in" % sname
 315             comma = '' if i == 5 else ','
 316             ret.append("            {0}{1}".format(ps, comma))
 317         ret.append("        });")
 318         ret.append("    endrule")
 319         return '\n'.join(ret)
 320
 321
 322 class pwm(PBase):
 323
 324     def slowimport(self):
 325         return "        import pwm::*;"
 326
 327     def slowifdecl(self):
 328         return "        interface PWMIO pwm{0}_io;"
 329
 330     def num_axi_regs32(self):
 331         return 4
 332
 333     def mkslow_peripheral(self, size=0):
 334         return "        Ifc_PWM_bus pwm{0} <- mkPWM_bus(sp_clock);"
 335
 336     def _mk_connection(self, name=None, count=0):
 337         return "pwm{0}.axi4_slave"
 338
 339     def pinname_out(self, pname):
 340         return {'out': 'pwm_io.pwm_o'}.get(pname, '')
 341
 342
 343 class gpio(PBase):
 344
 345     def slowimport(self):
 346         return "     import pinmux::*;\n" + \
 347                "     import mux::*;\n" + \
 348                "     import gpio::*;\n"
 349
 350     def slowifdecl(self):
 351         size = len(self.peripheral.pinspecs)
 352         return "        interface GPIO_config#(%d) pad_config{0};" % size
 353
 354     def num_axi_regs32(self):
 355         return 2
 356
 357     def axi_slave_idx(self, idx, name, ifacenum):
 358         """ generates AXI slave number definition, except
 359             GPIO also has a muxer per bank
 360         """
 361         name = name.upper()
 362         mname = 'mux' + name[4:]
 363         mname = mname.upper()
 364         print "AXIslavenum", name,  mname
 365         (ret, x) = PBase.axi_slave_idx(self, idx, name, ifacenum)
 366         (ret2, x) = PBase.axi_slave_idx(self, idx, mname, ifacenum)
 367         return ("%s\n%s" % (ret, ret2), 2)
 368
 369     def mkslow_peripheral(self, size=0):
 370         print "gpioslow", self.peripheral,  dir(self.peripheral)
 371         size = len(self.peripheral.pinspecs)
 372         return "        MUX#(%d) mux{0} <- mkmux();\n" % size + \
 373                "        GPIO#(%d) gpio{0} <- mkgpio();" % size
 374
 375     def mk_connection(self, count):
 376         print "GPIO mk_conn", self.name, count
 377         res = []
 378         dname = self.mksuffix(self.name, count)
 379         for i, n in enumerate(['gpio' + dname, 'mux' + dname]):
 380             res.append(PBase.mk_connection(self, count, n))
 381         return '\n'.join(res)
 382
 383     def _mk_connection(self, name=None, count=0):
 384         n = self.mksuffix(name, count)
 385         if name.startswith('gpio'):
 386             return "gpio{0}.axi_slave".format(n)
 387         if name.startswith('mux'):
 388             return "mux{0}.axi_slave".format(n)
 389
 390     def mksuffix(self, name, i):
 391         if name.startswith('mux'):
 392             return name[3:]
 393         return name[4:]
 394
 395     def mk_cellconn(self, cellnum, name, count):
 396         ret = []
 397         bank = self.mksuffix(name, count)
 398         txt = "       pinmux.mux_lines.cell{0}_mux(mux{1}.mux_config.mux[{2}]);"
 399         for p in self.peripheral.pinspecs:
 400             ret.append(txt.format(cellnum, bank, p['name'][1:]))
 401             cellnum += 1
 402         return ("\n".join(ret), cellnum)
 403
 404     def pinname_out(self, pname):
 405         return "func.gpio_out[{0}]".format(pname[1:])
 406
 407     def pinname_outen(self, pname):
 408         return {'sda': 'out.sda_outen',
 409                 'scl': 'out.scl_outen'}.get(pname, '')
 410
 411     def mk_pincon(self, name, count):
 412         ret = [PBase.mk_pincon(self, name, count)]
 413         # special-case for gpio in, store in a temporary vector
 414         plen = len(self.peripheral.pinspecs)
 415         ret.append("    rule con_%s%d_in;" % (name, count))
 416         ret.append("       Vector#({0},Bit#(1)) temp;".format(plen))
 417         for p in self.peripheral.pinspecs:
 418             typ = p['type']
 419             pname = p['name']
 420             idx = pname[1:]
 421             n = name
 422             sname = self.peripheral.pname(pname).format(count)
 423             ps = "pinmux.peripheral_side.%s_in" % sname
 424             ret.append("        temp[{0}]={1};".format(idx, ps))
 425         ret.append("        {0}.func.gpio_in(temp);".format(name))
 426         ret.append("    endrule")
 427         return '\n'.join(ret)
 428
 429
 430 axi_slave_declarations = """\
 431 typedef  0  SlowMaster;
 432 {0}
 433 typedef  TAdd#(LastGen_slave_num,`ifdef CLINT       1 `else 0 `endif )
 434               CLINT_slave_num;
 435 typedef  TAdd#(CLINT_slave_num  ,`ifdef PLIC        1 `else 0 `endif )
 436               Plic_slave_num;
 437 typedef  TAdd#(Plic_slave_num   ,`ifdef AXIEXP      1 `else 0 `endif )
 438               AxiExp1_slave_num;
 439 typedef TAdd#(AxiExp1_slave_num,1) Num_Slow_Slaves;
 440 """
 441
 442 pinmux_cellrule = """\
 443     rule connect_select_lines_pinmux;
 444 {0}
 445     endrule
 446 """
 447
 448
 449 class CallFn(object):
 450     def __init__(self, peripheral, name):
 451         self.peripheral = peripheral
 452         self.name = name
 453
 454     def __call__(self, *args):
 455         #print "__call__", self.name, self.peripheral.slow, args
 456         if not self.peripheral.slow:
 457             return ''
 458         return getattr(self.peripheral.slow, self.name)(*args[1:])
 459
 460
 461 class PeripheralIface(object):
 462     def __init__(self, ifacename):
 463         self.slow = None
 464         slow = slowfactory.getcls(ifacename)
 465         print "Iface", ifacename, slow
 466         if slow:
 467             self.slow = slow(ifacename)
 468             self.slow.peripheral = self
 469         for fname in ['slowimport', 'slowifdecl', 'mkslow_peripheral',
 470                       'mk_connection', 'mk_cellconn', 'mk_pincon']:
 471             fn = CallFn(self, fname)
 472             setattr(self, fname, types.MethodType(fn, self))
 473
 474         #print "PeripheralIface"
 475         #print dir(self)
 476
 477     def mksuffix(self, name, i):
 478         if self.slow is None:
 479             return i
 480         return self.slow.mksuffix(name, i)
 481
 482     def axi_reg_def(self, start, count):
 483         if not self.slow:
 484             return ('', 0)
 485         return self.slow.axi_reg_def(start, self.ifacename, count)
 486
 487     def axi_slave_idx(self, start, count):
 488         if not self.slow:
 489             return ('', 0)
 490         return self.slow.axi_slave_idx(start, self.ifacename, count)
 491
 492     def axi_addr_map(self, count):
 493         if not self.slow:
 494             return ''
 495         return self.slow.axi_addr_map(self.ifacename, count)
 496
 497
 498 class PeripheralInterfaces(object):
 499     def __init__(self):
 500         pass
 501
 502     def slowimport(self, *args):
 503         ret = []
 504         for (name, count) in self.ifacecount:
 505             #print "slowimport", name, self.data[name].slowimport
 506             ret.append(self.data[name].slowimport())
 507         return '\n'.join(list(filter(None, ret)))
 508
 509     def slowifdecl(self, *args):
 510         ret = []
 511         for (name, count) in self.ifacecount:
 512             for i in range(count):
 513                 ret.append(self.data[name].slowifdecl().format(i, name))
 514         return '\n'.join(list(filter(None, ret)))
 515
 516     def axi_reg_def(self, *args):
 517         ret = []
 518         start = 0x00011100  # start of AXI peripherals address
 519         for (name, count) in self.ifacecount:
 520             for i in range(count):
 521                 x = self.data[name].axi_reg_def(start, i)
 522                 #print ("ifc", name, x)
 523                 (rdef, offs) = x
 524                 ret.append(rdef)
 525                 start += offs
 526         return '\n'.join(list(filter(None, ret)))
 527
 528     def axi_slave_idx(self, *args):
 529         ret = []
 530         start = 0
 531         for (name, count) in self.ifacecount:
 532             for i in range(count):
 533                 (rdef, offs) = self.data[name].axi_slave_idx(start, i)
 534                 #print ("ifc", name, rdef, offs)
 535                 ret.append(rdef)
 536                 start += offs
 537         ret.append("typedef %d LastGen_slave_num;" % (start - 1))
 538         decls = '\n'.join(list(filter(None, ret)))
 539         return axi_slave_declarations.format(decls)
 540
 541     def axi_addr_map(self, *args):
 542         ret = []
 543         for (name, count) in self.ifacecount:
 544             for i in range(count):
 545                 ret.append(self.data[name].axi_addr_map(i))
 546         return '\n'.join(list(filter(None, ret)))
 547
 548     def mkslow_peripheral(self, *args):
 549         ret = []
 550         for (name, count) in self.ifacecount:
 551             for i in range(count):
 552                 print "mkslow", name, count
 553                 x = self.data[name].mkslow_peripheral()
 554                 print name, count, x
 555                 suffix = self.data[name].mksuffix(name, i)
 556                 ret.append(x.format(suffix))
 557         return '\n'.join(list(filter(None, ret)))
 558
 559     def mk_connection(self, *args):
 560         ret = []
 561         for (name, count) in self.ifacecount:
 562             for i in range(count):
 563                 print "mk_conn", name, i
 564                 txt = self.data[name].mk_connection(i)
 565                 if name == 'gpioa':
 566                     print "txt", txt
 567                     print self.data[name].mk_connection
 568                 ret.append(txt)
 569         return '\n'.join(list(filter(None, ret)))
 570
 571     def mk_cellconn(self):
 572         ret = []
 573         cellcount = 0
 574         for (name, count) in self.ifacecount:
 575             for i in range(count):
 576                 res = self.data[name].mk_cellconn(cellcount, name, i)
 577                 if not res:
 578                     continue
 579                 (txt, cellcount) = res
 580                 ret.append(txt)
 581         ret = '\n'.join(list(filter(None, ret)))
 582         return pinmux_cellrule.format(ret)
 583
 584     def mk_pincon(self):
 585         ret = []
 586         for (name, count) in self.ifacecount:
 587             for i in range(count):
 588                 txt = self.data[name].mk_pincon(name, i)
 589                 ret.append(txt)
 590         return '\n'.join(list(filter(None, ret)))
 591
 592
 593 class PFactory(object):
 594     def getcls(self, name):
 595         for k, v in {'uart': uart,
 596                      'rs232': rs232,
 597                      'twi': twi,
 598                      'qspi': qspi,
 599                      'pwm': pwm,
 600                      'gpio': gpio
 601                      }.items():
 602             if name.startswith(k):
 603                 return v
 604         return None
 605
 606
 607 slowfactory = PFactory()
 608
 609 if __name__ == '__main__':
 610     p = uart('uart')
 611     print p.slowimport()
 612     print p.slowifdecl()
 613     i = PeripheralIface('uart')
 614     print i, i.slow
 615     i = PeripheralIface('gpioa')
 616     print i, i.slow