src/bsv/peripheral_gen.py

   1 import types
   2 from copy import deepcopy
   3
   4
   5 class PBase(object):
   6     def __init__(self, name):
   7         self.name = name
   8
   9     def slowifdeclmux(self):
  10         return ''
  11
  12     def slowifinstance(self):
  13         return ''
  14
  15     def slowimport(self):
  16         return ''
  17
  18     def num_axi_regs32(self):
  19         return 0
  20
  21     def slowifdecl(self):
  22         return ''
  23
  24     def axibase(self, name, ifacenum):
  25         name = name.upper()
  26         return "%(name)s%(ifacenum)dBase" % locals()
  27
  28     def axiend(self, name, ifacenum):
  29         name = name.upper()
  30         return "%(name)s%(ifacenum)dEnd" % locals()
  31
  32     def axi_reg_def(self, start, name, ifacenum):
  33         name = name.upper()
  34         offs = self.num_axi_regs32() * 4 * 16
  35         if offs == 0:
  36             return ('', 0)
  37         end = start + offs - 1
  38         bname = self.axibase(name, ifacenum)
  39         bend = self.axiend(name, ifacenum)
  40         comment = "%d 32-bit regs" % self.num_axi_regs32()
  41         return ("    `define %(bname)s 'h%(start)08X\n"
  42                 "    `define %(bend)s  'h%(end)08X // %(comment)s" % locals(),
  43                 offs)
  44
  45     def axi_slave_name(self, name, ifacenum):
  46         name = name.upper()
  47         return "{0}{1}_slave_num".format(name, ifacenum)
  48
  49     def axi_slave_idx(self, idx, name, ifacenum):
  50         name = self.axi_slave_name(name, ifacenum)
  51         return ("typedef {0} {1};".format(idx, name), 1)
  52
  53     def axi_addr_map(self, name, ifacenum):
  54         bname = self.axibase(name, ifacenum)
  55         bend = self.axiend(name, ifacenum)
  56         name = self.axi_slave_name(name, ifacenum)
  57         return """\
  58         if(addr>=`{0} && addr<=`{1})
  59             return tuple2(True,fromInteger(valueOf({2})));
  60         else""".format(bname, bend, name)
  61
  62     def mk_pincon(self, name, count):
  63         # TODO: really should be using bsv.interface_decl.Interfaces
  64         # pin-naming rules.... logic here is hard-coded to duplicate
  65         # it (see Interface.__init__ outen)
  66         ret = []
  67         for p in self.peripheral.pinspecs:
  68             typ = p['type']
  69             pname = p['name']
  70             #n = "{0}{1}".format(self.name, self.mksuffix(name, count))
  71             n = name  # "{0}{1}".format(self.name, self.mksuffix(name, count))
  72             ret.append("    //%s %s" % (n, str(p)))
  73             sname = self.peripheral.pname(pname).format(count)
  74             ps = "pinmux.peripheral_side.%s" % sname
  75             if typ == 'out' or typ == 'inout':
  76                 ret.append("    rule con_%s%d_%s_out;" % (name, count, pname))
  77                 fname = self.pinname_out(pname)
  78                 if not n.startswith('gpio'):  # XXX EURGH! horrible hack
  79                     n_ = "{0}{1}".format(n, count)
  80                 else:
  81                     n_ = n
  82                 if fname:
  83                     if p.get('outen'):
  84                         ps_ = ps + '_out'
  85                     else:
  86                         ps_ = ps
  87                     ret.append("      {0}({1}.{2});".format(ps_, n_, fname))
  88                 fname = None
  89                 if p.get('outen'):
  90                     fname = self.pinname_outen(pname)
  91                 if fname:
  92                     if isinstance(fname, str):
  93                         fname = "{0}.{1}".format(n_, fname)
  94                     fname = self.pinname_tweak(pname, 'outen', fname)
  95                     ret.append("      {0}_outen({1});".format(ps, fname))
  96                 ret.append("    endrule")
  97             if typ == 'in' or typ == 'inout':
  98                 fname = self.pinname_in(pname)
  99                 if fname:
 100                     if p.get('outen'):
 101                         ps_ = ps + '_in'
 102                     else:
 103                         ps_ = ps
 104                     ret.append(
 105                         "    rule con_%s%d_%s_in;" %
 106                         (name, count, pname))
 107                     n_ = "{0}{1}".format(n, count)
 108                     n_ = '{0}.{1}'.format(n_, fname)
 109                     n_ = self.ifname_tweak(pname, 'in', n_)
 110                     ret.append("      {1}({0});".format(ps_, n_))
 111                     ret.append("    endrule")
 112         return '\n'.join(ret)
 113
 114     def mk_cellconn(self, *args):
 115         return ''
 116
 117     def mkslow_peripheral(self, size=0):
 118         return ''
 119
 120     def mksuffix(self, name, i):
 121         return i
 122
 123     def __mk_connection(self, con, aname):
 124         txt = "        mkConnection (slow_fabric.v_to_slaves\n" + \
 125             "                    [fromInteger(valueOf({1}))],\n" + \
 126             "                    {0});"
 127
 128         print "PBase __mk_connection", self.name, aname
 129         if not con:
 130             return ''
 131         return txt.format(con, aname)
 132
 133     def mk_connection(self, count, name=None):
 134         if name is None:
 135             name = self.name
 136         print "PBase mk_conn", self.name, count
 137         aname = self.axi_slave_name(name, count)
 138         #dname = self.mksuffix(name, count)
 139         #dname = "{0}{1}".format(name, dname)
 140         con = self._mk_connection(name, count).format(count, aname)
 141         return self.__mk_connection(con, aname)
 142
 143     def _mk_connection(self, name=None, count=0):
 144         return ''
 145
 146     def pinname_out(self, pname):
 147         return ''
 148
 149     def pinname_in(self, pname):
 150         return ''
 151
 152     def pinname_outen(self, pname):
 153         return ''
 154
 155     def ifname_tweak(self, pname, typ, txt):
 156         return txt
 157
 158     def pinname_tweak(self, pname, typ, txt):
 159         return txt
 160
 161
 162 class uart(PBase):
 163
 164     def slowimport(self):
 165         return "          import Uart_bs         :: *;\n" + \
 166                "          import RS232_modified::*;"
 167
 168     def slowifdecl(self):
 169         return "            interface RS232 uart{0}_coe;\n" + \
 170                "            method Bit#(1) uart{0}_intr;"
 171
 172     def num_axi_regs32(self):
 173         return 8
 174
 175     def mkslow_peripheral(self, size=0):
 176         return "        Ifc_Uart_bs uart{0} <- \n" + \
 177                "                mkUart_bs(clocked_by sp_clock,\n" + \
 178                "                    reset_by uart_reset, sp_clock, sp_reset);"
 179
 180     def _mk_connection(self, name=None, count=0):
 181         return "uart{0}.slave_axi_uart"
 182
 183     def pinname_out(self, pname):
 184         return {'tx': 'coe_rs232.sout'}.get(pname, '')
 185
 186     def pinname_in(self, pname):
 187         return {'rx': 'coe_rs232.sin'}.get(pname, '')
 188
 189
 190 class quart(PBase):
 191
 192     def slowimport(self):
 193         return "          import Uart16550         :: *;"
 194
 195     def slowifdecl(self):
 196         return "            interface RS232_PHY_Ifc quart{0}_coe;\n" + \
 197                "            method Bit#(1) quart{0}_intr;"
 198
 199     def num_axi_regs32(self):
 200         return 8
 201
 202     def mkslow_peripheral(self, size=0):
 203         return "        Uart16550_AXI4_Lite_Ifc quart{0} <- \n" + \
 204                "                mkUart16550(clocked_by sp_clock,\n" + \
 205                "                    reset_by uart_reset, sp_clock, sp_reset);"
 206
 207     def _mk_connection(self, name=None, count=0):
 208         return "quart{0}.slave_axi_uart"
 209
 210     def pinname_out(self, pname):
 211         return {'tx' : 'coe_rs232.modem_output_stx',
 212                 'rts': 'coe_rs232.modem_output_rts',
 213                }.get(pname, '')
 214
 215     def _pinname_in(self, pname):
 216         return {'rx': 'coe_rs232.modem_input.srx',
 217                 'cts': 'coe_rs232.modem_input.cts'
 218                }.get(pname, '')
 219
 220     def mk_pincon(self, name, count):
 221         ret = [PBase.mk_pincon(self, name, count)]
 222         size = len(self.peripheral.pinspecs)
 223         ret.append(eint_pincon_template.format(size))
 224         ret.append("    rule con_%s%d_io_in;" % (name, count))
 225         ret.append("       {0}{1}.coe_rs232.modem_input(".format(name, count))
 226         for idx, pname in enumerate(['rx', 'cts']):
 227             sname = self.peripheral.pname(pname).format(count)
 228             ps = "pinmux.peripheral_side.%s" % sname
 229             ret.append("            {0},".format(ps))
 230         ret.append("            1'b1,1'b0,1'b1")
 231         ret.append("        );")
 232         ret.append("    endrule")
 233
 234         return '\n'.join(ret)
 235
 236
 237 class rs232(PBase):
 238
 239     def slowimport(self):
 240         return "        import Uart_bs::*;\n" + \
 241                "        import RS232_modified::*;"
 242
 243     def slowifdecl(self):
 244         return "            interface RS232 uart{0}_coe;"
 245
 246     def num_axi_regs32(self):
 247         return 2
 248
 249     def mkslow_peripheral(self, size=0):
 250         return "        //Ifc_Uart_bs uart{0} <-" + \
 251                "        //       mkUart_bs(clocked_by uart_clock,\n" + \
 252                "        //          reset_by uart_reset,sp_clock, sp_reset);" +\
 253                "        Ifc_Uart_bs uart{0} <-" + \
 254                "                mkUart_bs(clocked_by sp_clock,\n" + \
 255                "                    reset_by sp_reset, sp_clock, sp_reset);"
 256
 257     def _mk_connection(self, name=None, count=0):
 258         return "uart{0}.slave_axi_uart"
 259
 260     def pinname_out(self, pname):
 261         return {'tx': 'coe_rs232.sout'}.get(pname, '')
 262
 263     def pinname_in(self, pname):
 264         return {'rx': 'coe_rs232.sin'}.get(pname, '')
 265
 266
 267 class twi(PBase):
 268
 269     def slowimport(self):
 270         return "        import I2C_top           :: *;"
 271
 272     def slowifdecl(self):
 273         return "            interface I2C_out twi{0}_out;\n" + \
 274                "            method Bit#(1) twi{0}_isint;"
 275
 276     def num_axi_regs32(self):
 277         return 8
 278
 279     def mkslow_peripheral(self, size=0):
 280         return "        I2C_IFC twi{0} <- mkI2CController();"
 281
 282     def _mk_connection(self, name=None, count=0):
 283         return "twi{0}.slave_i2c_axi"
 284
 285     def pinname_out(self, pname):
 286         return {'sda': 'out.sda_out',
 287                 'scl': 'out.scl_out'}.get(pname, '')
 288
 289     def pinname_in(self, pname):
 290         return {'sda': 'out.sda_in',
 291                 'scl': 'out.scl_in'}.get(pname, '')
 292
 293     def pinname_outen(self, pname):
 294         return {'sda': 'out.sda_out_en',
 295                 'scl': 'out.scl_out_en'}.get(pname, '')
 296
 297     def pinname_tweak(self, pname, typ, txt):
 298         if typ == 'outen':
 299             return "pack({0})".format(txt)
 300         return txt
 301
 302
 303 class eint(PBase):
 304
 305     def slowimport(self):
 306         size = len(self.peripheral.pinspecs)
 307         return "    `define NUM_EINTS %d" % size
 308
 309     def mkslow_peripheral(self, size=0):
 310         size = len(self.peripheral.pinspecs)
 311         return "        Wire#(Bit#(%d)) wr_interrupt <- mkWire();" % size
 312
 313     def axi_slave_name(self, name, ifacenum):
 314         return ''
 315
 316     def axi_slave_idx(self, idx, name, ifacenum):
 317         return ('', 0)
 318
 319     def axi_addr_map(self, name, ifacenum):
 320         return ''
 321
 322     def ifname_tweak(self, pname, typ, txt):
 323         if typ != 'in':
 324             return txt
 325         print "ifnameweak", pname, typ, txt
 326         return "wr_interrupt[{0}] <= ".format(pname)
 327
 328     def mk_pincon(self, name, count):
 329         ret = [PBase.mk_pincon(self, name, count)]
 330         size = len(self.peripheral.pinspecs)
 331         ret.append(eint_pincon_template.format(size))
 332         ret.append("    rule con_%s%d_io_in;" % (name, count))
 333         ret.append("    wr_interrupt <= ({")
 334         for idx, p in enumerate(self.peripheral.pinspecs):
 335             pname = p['name']
 336             sname = self.peripheral.pname(pname).format(count)
 337             ps = "pinmux.peripheral_side.%s" % sname
 338             comma = '' if idx == size - 1 else ','
 339             ret.append("             {0}{1}".format(ps, comma))
 340         ret.append("        });")
 341         ret.append("    endrule")
 342
 343         return '\n'.join(ret)
 344
 345
 346 eint_pincon_template = '''\
 347     // TODO: offset i by the number of eints already used
 348     for(Integer i=0;i<{0};i=i+ 1)begin
 349       rule connect_int_to_plic(wr_interrupt[i]==1);
 350                 ff_gateway_queue[i].enq(1);
 351                 plic.ifc_external_irq[i].irq_frm_gateway(True);
 352       endrule
 353     end
 354 '''
 355
 356
 357 class jtag(PBase):
 358
 359     def axi_slave_name(self, name, ifacenum):
 360         return ''
 361
 362     def axi_slave_idx(self, idx, name, ifacenum):
 363         return ('', 0)
 364
 365     def axi_addr_map(self, name, ifacenum):
 366         return ''
 367
 368     def slowifdeclmux(self):
 369         return "            method  Action jtag_ms (Bit#(1) in);\n" +  \
 370                "            method  Bit#(1) jtag_di;\n" + \
 371                "            method  Action jtag_do (Bit#(1) in);\n" + \
 372                "            method  Action jtag_ck (Bit#(1) in);"
 373
 374     def slowifinstance(self):
 375         return jtag_method_template # bit of a lazy hack this...
 376
 377 jtag_method_template = """\
 378     method  Action jtag_ms (Bit#(1) in);
 379       pinmux.peripheral_side.jtag_ms(in);
 380     endmethod
 381     method  Bit#(1) jtag_di=pinmux.peripheral_side.jtag_di;
 382     method  Action jtag_do (Bit#(1) in);
 383       pinmux.peripheral_side.jtag_do(in);
 384     endmethod
 385     method  Action jtag_ck (Bit#(1) in);
 386       pinmux.peripheral_side.jtag_ck(in);
 387     endmethod
 388 """
 389
 390 class sdmmc(PBase):
 391
 392     def slowimport(self):
 393         return "        import sdcard_dummy              :: *;"
 394
 395     def slowifdecl(self):
 396         return "            interface QSPI_out sd{0}_out;\n" + \
 397                "            method Bit#(1) sd{0}_isint;"
 398
 399     def num_axi_regs32(self):
 400         return 13
 401
 402     def mkslow_peripheral(self):
 403         return "        Ifc_sdcard_dummy sd{0} <-  mksdcard_dummy();"
 404
 405     def _mk_connection(self, name=None, count=0):
 406         return "sd{0}.slave"
 407
 408     def pinname_in(self, pname):
 409         return "%s_in" % pname
 410
 411     def pinname_out(self, pname):
 412         if pname.startswith('d'):
 413             return "%s_out" % pname
 414         return pname
 415
 416     def pinname_outen(self, pname):
 417         if pname.startswith('d'):
 418             return "%s_outen" % pname
 419
 420
 421 class spi(PBase):
 422
 423     def slowimport(self):
 424         return "        import qspi              :: *;"
 425
 426     def slowifdecl(self):
 427         return "            interface QSPI_out spi{0}_out;\n" + \
 428                "            method Bit#(1) spi{0}_isint;"
 429
 430     def num_axi_regs32(self):
 431         return 13
 432
 433     def mkslow_peripheral(self):
 434         return "        Ifc_qspi spi{0} <-  mkqspi();"
 435
 436     def _mk_connection(self, name=None, count=0):
 437         return "spi{0}.slave"
 438
 439     def pinname_out(self, pname):
 440         return {'clk': 'out.clk_o',
 441                 'nss': 'out.ncs_o',
 442                 'mosi': 'out.io_o[0]',
 443                 'miso': 'out.io_o[1]',
 444                 }.get(pname, '')
 445
 446     def pinname_outen(self, pname):
 447         return {'clk': 1,
 448                 'nss': 1,
 449                 'mosi': 'out.io_enable[0]',
 450                 'miso': 'out.io_enable[1]',
 451                 }.get(pname, '')
 452
 453     def mk_pincon(self, name, count):
 454         ret = [PBase.mk_pincon(self, name, count)]
 455         # special-case for gpio in, store in a temporary vector
 456         plen = len(self.peripheral.pinspecs)
 457         ret.append("    // XXX NSS and CLK are hard-coded master")
 458         ret.append("    // TODO: must add spi slave-mode")
 459         ret.append("    // all ins done in one rule from 4-bitfield")
 460         ret.append("    rule con_%s%d_io_in;" % (name, count))
 461         ret.append("       {0}{1}.out.io_i({{".format(name, count))
 462         for idx, pname in enumerate(['mosi', 'miso']):
 463             sname = self.peripheral.pname(pname).format(count)
 464             ps = "pinmux.peripheral_side.%s_in" % sname
 465             ret.append("            {0},".format(ps))
 466         ret.append("            1'b0,1'b0")
 467         ret.append("        });")
 468         ret.append("    endrule")
 469         return '\n'.join(ret)
 470
 471
 472 class qspi(PBase):
 473
 474     def slowimport(self):
 475         return "        import qspi              :: *;"
 476
 477     def slowifdecl(self):
 478         return "            interface QSPI_out qspi{0}_out;\n" + \
 479                "            method Bit#(1) qspi{0}_isint;"
 480
 481     def num_axi_regs32(self):
 482         return 13
 483
 484     def mkslow_peripheral(self, size=0):
 485         return "        Ifc_qspi qspi{0} <-  mkqspi();"
 486
 487     def _mk_connection(self, name=None, count=0):
 488         return "qspi{0}.slave"
 489
 490     def pinname_out(self, pname):
 491         return {'ck': 'out.clk_o',
 492                 'nss': 'out.ncs_o',
 493                 'io0': 'out.io_o[0]',
 494                 'io1': 'out.io_o[1]',
 495                 'io2': 'out.io_o[2]',
 496                 'io3': 'out.io_o[3]',
 497                 }.get(pname, '')
 498
 499     def pinname_outen(self, pname):
 500         return {'ck': 1,
 501                 'nss': 1,
 502                 'io0': 'out.io_enable[0]',
 503                 'io1': 'out.io_enable[1]',
 504                 'io2': 'out.io_enable[2]',
 505                 'io3': 'out.io_enable[3]',
 506                 }.get(pname, '')
 507
 508     def mk_pincon(self, name, count):
 509         ret = [PBase.mk_pincon(self, name, count)]
 510         # special-case for gpio in, store in a temporary vector
 511         plen = len(self.peripheral.pinspecs)
 512         ret.append("    // XXX NSS and CLK are hard-coded master")
 513         ret.append("    // TODO: must add qspi slave-mode")
 514         ret.append("    // all ins done in one rule from 4-bitfield")
 515         ret.append("    rule con_%s%d_io_in;" % (name, count))
 516         ret.append("       {0}{1}.out.io_i({{".format(name, count))
 517         for i, p in enumerate(self.peripheral.pinspecs):
 518             typ = p['type']
 519             pname = p['name']
 520             if not pname.startswith('io'):
 521                 continue
 522             idx = pname[1:]
 523             n = name
 524             sname = self.peripheral.pname(pname).format(count)
 525             ps = "pinmux.peripheral_side.%s_in" % sname
 526             comma = '' if i == 5 else ','
 527             ret.append("            {0}{1}".format(ps, comma))
 528         ret.append("        });")
 529         ret.append("    endrule")
 530         return '\n'.join(ret)
 531
 532
 533 class pwm(PBase):
 534
 535     def slowimport(self):
 536         return "        import pwm::*;"
 537
 538     def slowifdecl(self):
 539         return "        interface PWMIO pwm{0}_io;"
 540
 541     def num_axi_regs32(self):
 542         return 4
 543
 544     def mkslow_peripheral(self, size=0):
 545         return "        Ifc_PWM_bus pwm{0} <- mkPWM_bus(sp_clock);"
 546
 547     def _mk_connection(self, name=None, count=0):
 548         return "pwm{0}.axi4_slave"
 549
 550     def pinname_out(self, pname):
 551         return {'out': 'pwm_io.pwm_o'}.get(pname, '')
 552
 553
 554 class gpio(PBase):
 555
 556     def slowimport(self):
 557         return "     import pinmux::*;\n" + \
 558                "     import mux::*;\n" + \
 559                "     import gpio::*;\n"
 560
 561     def slowifdeclmux(self):
 562         size = len(self.peripheral.pinspecs)
 563         return "    interface GPIO_config#(%d) pad_config{0};" % size
 564
 565     def num_axi_regs32(self):
 566         return 2
 567
 568     def axi_slave_idx(self, idx, name, ifacenum):
 569         """ generates AXI slave number definition, except
 570             GPIO also has a muxer per bank
 571         """
 572         name = name.upper()
 573         mname = 'mux' + name[4:]
 574         mname = mname.upper()
 575         print "AXIslavenum", name, mname
 576         (ret, x) = PBase.axi_slave_idx(self, idx, name, ifacenum)
 577         (ret2, x) = PBase.axi_slave_idx(self, idx + 1, mname, ifacenum)
 578         return ("%s\n%s" % (ret, ret2), 2)
 579
 580     def mkslow_peripheral(self, size=0):
 581         print "gpioslow", self.peripheral, dir(self.peripheral)
 582         size = len(self.peripheral.pinspecs)
 583         return "        MUX#(%d) mux{0} <- mkmux();\n" % size + \
 584                "        GPIO#(%d) gpio{0} <- mkgpio();" % size
 585
 586     def mk_connection(self, count):
 587         print "GPIO mk_conn", self.name, count
 588         res = []
 589         dname = self.mksuffix(self.name, count)
 590         for i, n in enumerate(['gpio' + dname, 'mux' + dname]):
 591             res.append(PBase.mk_connection(self, count, n))
 592         return '\n'.join(res)
 593
 594     def _mk_connection(self, name=None, count=0):
 595         n = self.mksuffix(name, count)
 596         if name.startswith('gpio'):
 597             return "gpio{0}.axi_slave".format(n)
 598         if name.startswith('mux'):
 599             return "mux{0}.axi_slave".format(n)
 600
 601     def mksuffix(self, name, i):
 602         if name.startswith('mux'):
 603             return name[3:]
 604         return name[4:]
 605
 606     def mk_cellconn(self, cellnum, name, count):
 607         ret = []
 608         bank = self.mksuffix(name, count)
 609         txt = "       pinmux.mux_lines.cell{0}_mux(mux{1}.mux_config.mux[{2}]);"
 610         for p in self.peripheral.pinspecs:
 611             ret.append(txt.format(cellnum, bank, p['name'][1:]))
 612             cellnum += 1
 613         return ("\n".join(ret), cellnum)
 614
 615     def pinname_out(self, pname):
 616         return "func.gpio_out[{0}]".format(pname[1:])
 617
 618     def pinname_outen(self, pname):
 619         return "func.gpio_out_en[{0}]".format(pname[1:])
 620
 621     def mk_pincon(self, name, count):
 622         ret = [PBase.mk_pincon(self, name, count)]
 623         # special-case for gpio in, store in a temporary vector
 624         plen = len(self.peripheral.pinspecs)
 625         ret.append("    rule con_%s%d_in;" % (name, count))
 626         ret.append("       Vector#({0},Bit#(1)) temp;".format(plen))
 627         for p in self.peripheral.pinspecs:
 628             typ = p['type']
 629             pname = p['name']
 630             idx = pname[1:]
 631             n = name
 632             sname = self.peripheral.pname(pname).format(count)
 633             ps = "pinmux.peripheral_side.%s_in" % sname
 634             ret.append("        temp[{0}]={1};".format(idx, ps))
 635         ret.append("        {0}.func.gpio_in(temp);".format(name))
 636         ret.append("    endrule")
 637         return '\n'.join(ret)
 638
 639
 640 axi_slave_declarations = """\
 641 typedef  0  SlowMaster;
 642 {0}
 643 typedef  TAdd#(LastGen_slave_num,`ifdef CLINT       1 `else 0 `endif )
 644               CLINT_slave_num;
 645 typedef  TAdd#(CLINT_slave_num  ,`ifdef PLIC        1 `else 0 `endif )
 646               Plic_slave_num;
 647 typedef  TAdd#(Plic_slave_num   ,`ifdef AXIEXP      1 `else 0 `endif )
 648               AxiExp1_slave_num;
 649 typedef TAdd#(AxiExp1_slave_num,1) Num_Slow_Slaves;
 650 """
 651
 652 pinmux_cellrule = """\
 653     rule connect_select_lines_pinmux;
 654 {0}
 655     endrule
 656 """
 657
 658
 659 class CallFn(object):
 660     def __init__(self, peripheral, name):
 661         self.peripheral = peripheral
 662         self.name = name
 663
 664     def __call__(self, *args):
 665         #print "__call__", self.name, self.peripheral.slow, args
 666         if not self.peripheral.slow:
 667             return ''
 668         return getattr(self.peripheral.slow, self.name)(*args[1:])
 669
 670
 671 class PeripheralIface(object):
 672     def __init__(self, ifacename):
 673         self.slow = None
 674         slow = slowfactory.getcls(ifacename)
 675         print "Iface", ifacename, slow
 676         if slow:
 677             self.slow = slow(ifacename)
 678             self.slow.peripheral = self
 679         for fname in ['slowimport',
 680                       'slowifinstance', 'slowifdecl', 'slowifdeclmux',
 681                       'mkslow_peripheral',
 682                       'mk_connection', 'mk_cellconn', 'mk_pincon']:
 683             fn = CallFn(self, fname)
 684             setattr(self, fname, types.MethodType(fn, self))
 685
 686         #print "PeripheralIface"
 687         #print dir(self)
 688
 689     def mksuffix(self, name, i):
 690         if self.slow is None:
 691             return i
 692         return self.slow.mksuffix(name, i)
 693
 694     def axi_reg_def(self, start, count):
 695         if not self.slow:
 696             return ('', 0)
 697         return self.slow.axi_reg_def(start, self.ifacename, count)
 698
 699     def axi_slave_idx(self, start, count):
 700         if not self.slow:
 701             return ('', 0)
 702         return self.slow.axi_slave_idx(start, self.ifacename, count)
 703
 704     def axi_addr_map(self, count):
 705         if not self.slow:
 706             return ''
 707         return self.slow.axi_addr_map(self.ifacename, count)
 708
 709
 710 class PeripheralInterfaces(object):
 711     def __init__(self):
 712         pass
 713
 714     def slowimport(self, *args):
 715         ret = []
 716         for (name, count) in self.ifacecount:
 717             #print "slowimport", name, self.data[name].slowimport
 718             ret.append(self.data[name].slowimport())
 719         return '\n'.join(list(filter(None, ret)))
 720
 721     def slowifinstance(self, *args):
 722         ret = []
 723         for (name, count) in self.ifacecount:
 724             #print "slowimport", name, self.data[name].slowimport
 725             ret.append(self.data[name].slowifinstance())
 726         return '\n'.join(list(filter(None, ret)))
 727
 728     def slowifdeclmux(self, *args):
 729         ret = []
 730         for (name, count) in self.ifacecount:
 731             for i in range(count):
 732                 ret.append(self.data[name].slowifdeclmux().format(i, name))
 733         return '\n'.join(list(filter(None, ret)))
 734
 735     def slowifdecl(self, *args):
 736         ret = []
 737         for (name, count) in self.ifacecount:
 738             for i in range(count):
 739                 ret.append(self.data[name].slowifdecl().format(i, name))
 740         return '\n'.join(list(filter(None, ret)))
 741
 742     def axi_reg_def(self, *args):
 743         ret = []
 744         start = 0x00011100  # start of AXI peripherals address
 745         for (name, count) in self.ifacecount:
 746             for i in range(count):
 747                 x = self.data[name].axi_reg_def(start, i)
 748                 #print ("ifc", name, x)
 749                 (rdef, offs) = x
 750                 ret.append(rdef)
 751                 start += offs
 752         return '\n'.join(list(filter(None, ret)))
 753
 754     def axi_slave_idx(self, *args):
 755         ret = []
 756         start = 0
 757         for (name, count) in self.ifacecount:
 758             for i in range(count):
 759                 (rdef, offs) = self.data[name].axi_slave_idx(start, i)
 760                 #print ("ifc", name, rdef, offs)
 761                 ret.append(rdef)
 762                 start += offs
 763         ret.append("typedef %d LastGen_slave_num;" % (start - 1))
 764         decls = '\n'.join(list(filter(None, ret)))
 765         return axi_slave_declarations.format(decls)
 766
 767     def axi_addr_map(self, *args):
 768         ret = []
 769         for (name, count) in self.ifacecount:
 770             for i in range(count):
 771                 ret.append(self.data[name].axi_addr_map(i))
 772         return '\n'.join(list(filter(None, ret)))
 773
 774     def mkslow_peripheral(self, *args):
 775         ret = []
 776         for (name, count) in self.ifacecount:
 777             for i in range(count):
 778                 print "mkslow", name, count
 779                 x = self.data[name].mkslow_peripheral()
 780                 print name, count, x
 781                 suffix = self.data[name].mksuffix(name, i)
 782                 ret.append(x.format(suffix))
 783         return '\n'.join(list(filter(None, ret)))
 784
 785     def mk_connection(self, *args):
 786         ret = []
 787         for (name, count) in self.ifacecount:
 788             for i in range(count):
 789                 print "mk_conn", name, i
 790                 txt = self.data[name].mk_connection(i)
 791                 if name == 'gpioa':
 792                     print "txt", txt
 793                     print self.data[name].mk_connection
 794                 ret.append(txt)
 795         return '\n'.join(list(filter(None, ret)))
 796
 797     def mk_cellconn(self):
 798         ret = []
 799         cellcount = 0
 800         for (name, count) in self.ifacecount:
 801             for i in range(count):
 802                 res = self.data[name].mk_cellconn(cellcount, name, i)
 803                 if not res:
 804                     continue
 805                 (txt, cellcount) = res
 806                 ret.append(txt)
 807         ret = '\n'.join(list(filter(None, ret)))
 808         return pinmux_cellrule.format(ret)
 809
 810     def mk_pincon(self):
 811         ret = []
 812         for (name, count) in self.ifacecount:
 813             for i in range(count):
 814                 txt = self.data[name].mk_pincon(name, i)
 815                 ret.append(txt)
 816         return '\n'.join(list(filter(None, ret)))
 817
 818
 819 class PFactory(object):
 820     def getcls(self, name):
 821         for k, v in {'uart': uart,
 822                      'rs232': rs232,
 823                      'twi': twi,
 824                      'quart': quart,
 825                      'qspi': qspi,
 826                      'spi': spi,
 827                      'pwm': pwm,
 828                      'eint': eint,
 829                      'sd': sdmmc,
 830                      'jtag': jtag,
 831                      'gpio': gpio
 832                      }.items():
 833             if name.startswith(k):
 834                 return v
 835         return None
 836
 837
 838 slowfactory = PFactory()
 839
 840 if __name__ == '__main__':
 841     p = uart('uart')
 842     print p.slowimport()
 843     print p.slowifdecl()
 844     i = PeripheralIface('uart')
 845     print i, i.slow
 846     i = PeripheralIface('gpioa')
 847     print i, i.slow