2 from copy
import deepcopy
6 def __init__(self
, name
):
9 def axibase(self
, name
, ifacenum
):
11 return "%(name)s%(ifacenum)dBase" % locals()
13 def axiend(self
, name
, ifacenum
):
15 return "%(name)s%(ifacenum)dEnd" % locals()
17 def axi_reg_def(self
, start
, name
, ifacenum
):
19 offs
= self
.num_axi_regs32() * 4 * 16
20 end
= start
+ offs
- 1
21 bname
= self
.axibase(name
, ifacenum
)
22 bend
= self
.axiend(name
, ifacenum
)
23 comment
= "%d 32-bit regs" % self
.num_axi_regs32()
24 return (" `define %(bname)s 'h%(start)08X\n"
25 " `define %(bend)s 'h%(end)08X // %(comment)s" % locals(),
28 def axi_slave_name(self
, name
, ifacenum
):
30 return "{0}{1}_slave_num".format(name
, ifacenum
)
32 def axi_slave_idx(self
, idx
, name
, ifacenum
):
33 name
= self
.axi_slave_name(name
, ifacenum
)
34 return ("typedef {0} {1};".format(idx
, name
), 1)
36 def axi_addr_map(self
, name
, ifacenum
):
37 bname
= self
.axibase(name
, ifacenum
)
38 bend
= self
.axiend(name
, ifacenum
)
39 name
= self
.axi_slave_name(name
, ifacenum
)
41 if(addr>=`{0} && addr<=`{1})
42 return tuple2(True,fromInteger(valueOf({2})));
43 else""".format(bname
, bend
, name
)
45 def mk_pincon(self
, name
, count
):
46 # TODO: really should be using bsv.interface_decl.Interfaces
47 # pin-naming rules.... logic here is hard-coded to duplicate
48 # it (see Interface.__init__ outen)
50 for p
in self
.peripheral
.pinspecs
:
53 #n = "{0}{1}".format(self.name, self.mksuffix(name, count))
54 n
= name
# "{0}{1}".format(self.name, self.mksuffix(name, count))
55 ret
.append(" //%s %s" % (n
, str(p
)))
56 sname
= self
.peripheral
.pname(pname
).format(count
)
57 ps
= "pinmux.peripheral_side.%s" % sname
58 if typ
== 'out' or typ
== 'inout':
59 ret
.append(" rule con_%s%d_%s_out;" % (name
, count
, pname
))
60 fname
= self
.pinname_out(pname
)
66 n_
= "{0}{1}".format(n
, count
)
67 ret
.append(" {0}({1}.{2});".format(ps_
, n_
, fname
))
70 fname
= self
.pinname_outen(pname
)
72 if isinstance(fname
, str):
73 fname
= "{0}{1}.{2}".format(n
, count
, fname
)
74 fname
= self
.pinname_tweak(pname
, 'outen', fname
)
75 ret
.append(" {0}_outen({1});".format(ps
, fname
))
76 ret
.append(" endrule")
77 if typ
== 'in' or typ
== 'inout':
78 fname
= self
.pinname_in(pname
)
85 " rule con_%s%d_%s_in;" %
87 ret
.append(" {1}.{2}({0});".format(ps_
, n
, fname
))
88 ret
.append(" endrule")
91 def mk_cellconn(self
, *args
):
94 def mkslow_peripheral(self
, size
=0):
97 def mksuffix(self
, name
, i
):
100 def __mk_connection(self
, con
, aname
):
101 txt
= " mkConnection (slow_fabric.v_to_slaves\n" + \
102 " [fromInteger(valueOf({1}))],\n" + \
105 print "PBase __mk_connection", self
.name
, aname
108 return txt
.format(con
, aname
)
110 def mk_connection(self
, count
, name
=None):
113 print "PBase mk_conn", self
.name
, count
114 aname
= self
.axi_slave_name(name
, count
)
115 #dname = self.mksuffix(name, count)
116 #dname = "{0}{1}".format(name, dname)
117 con
= self
._mk
_connection
(name
, count
).format(count
, aname
)
118 return self
.__mk
_connection
(con
, aname
)
120 def _mk_connection(self
, name
=None, count
=0):
123 def pinname_out(self
, pname
):
126 def pinname_in(self
, pname
):
129 def pinname_outen(self
, pname
):
132 def pinname_tweak(self
, pname
, typ
, txt
):
138 def slowimport(self
):
139 return " import Uart16550 :: *;"
141 def slowifdecl(self
):
142 return " interface RS232_PHY_Ifc uart{0}_coe;\n" + \
143 " method Bit#(1) uart{0}_intr;"
145 def num_axi_regs32(self
):
148 def mkslow_peripheral(self
, size
=0):
149 return " Uart16550_AXI4_Lite_Ifc uart{0} <- \n" + \
150 " mkUart16550(clocked_by uart_clock,\n" + \
151 " reset_by uart_reset, sp_clock, sp_reset);"
153 def _mk_connection(self
, name
=None, count
=0):
154 return "uart{0}.slave_axi_uart"
156 def pinname_out(self
, pname
):
157 return {'tx': 'coe_rs232.sout'}.get(pname
, '')
159 def pinname_in(self
, pname
):
160 return {'rx': 'coe_rs232.sin'}.get(pname
, '')
165 def slowimport(self
):
166 return " import Uart_bs::*;\n" + \
167 " import RS232_modified::*;"
169 def slowifdecl(self
):
170 return " interface RS232 uart{0}_coe;"
172 def num_axi_regs32(self
):
175 def mkslow_peripheral(self
, size
=0):
176 return " //Ifc_Uart_bs uart{0} <-" + \
177 " // mkUart_bs(clocked_by uart_clock,\n" + \
178 " // reset_by uart_reset,sp_clock, sp_reset);" +\
179 " Ifc_Uart_bs uart{0} <-" + \
180 " mkUart_bs(clocked_by sp_clock,\n" + \
181 " reset_by sp_reset, sp_clock, sp_reset);"
183 def _mk_connection(self
, name
=None, count
=0):
184 return "uart{0}.slave_axi_uart"
186 def pinname_out(self
, pname
):
187 return {'tx': 'coe_rs232.sout'}.get(pname
, '')
189 def pinname_in(self
, pname
):
190 return {'rx': 'coe_rs232.sin'}.get(pname
, '')
195 def slowimport(self
):
196 return " import I2C_top :: *;"
198 def slowifdecl(self
):
199 return " interface I2C_out twi{0}_out;\n" + \
200 " method Bit#(1) twi{0}_isint;"
202 def num_axi_regs32(self
):
205 def mkslow_peripheral(self
, size
=0):
206 return " I2C_IFC twi{0} <- mkI2CController();"
208 def _mk_connection(self
, name
=None, count
=0):
209 return "twi{0}.slave_i2c_axi"
211 def pinname_out(self
, pname
):
212 return {'sda': 'out.sda_out',
213 'scl': 'out.scl_out'}.get(pname
, '')
215 def pinname_in(self
, pname
):
216 return {'sda': 'out.sda_in',
217 'scl': 'out.scl_in'}.get(pname
, '')
219 def pinname_outen(self
, pname
):
220 return {'sda': 'out.sda_outen',
221 'scl': 'out.scl_outen'}.get(pname
, '')
223 def pinname_tweak(self
, pname
, typ
, txt
):
225 return "pack({0})".format(txt
)
231 def slowimport(self
):
232 return " import qspi :: *;"
234 def slowifdecl(self
):
235 return " interface QSPI_out qspi{0}_out;\n" + \
236 " method Bit#(1) qspi{0}_isint;"
238 def num_axi_regs32(self
):
241 def mkslow_peripheral(self
, size
=0):
242 return " Ifc_qspi qspi{0} <- mkqspi();"
244 def _mk_connection(self
, name
=None, count
=0):
245 return "qspi{0}.slave"
247 def pinname_out(self
, pname
):
248 return {'ck': 'out.clk_o',
250 'io0': 'out.io_o[0]',
251 'io1': 'out.io_o[1]',
252 'io2': 'out.io_o[2]',
253 'io3': 'out.io_o[3]',
256 def pinname_outen(self
, pname
):
259 'io0': 'out.io_enable[0]',
260 'io1': 'out.io_enable[1]',
261 'io2': 'out.io_enable[2]',
262 'io3': 'out.io_enable[3]',
265 def mk_pincon(self
, name
, count
):
266 ret
= [PBase
.mk_pincon(self
, name
, count
)]
267 # special-case for gpio in, store in a temporary vector
268 plen
= len(self
.peripheral
.pinspecs
)
269 ret
.append(" // XXX NSS and CLK are hard-coded master")
270 ret
.append(" // TODO: must add qspi slave-mode")
271 ret
.append(" // all ins done in one rule from 4-bitfield")
272 ret
.append(" rule con_%s%d_io_in;" % (name
, count
))
273 ret
.append(" {0}{1}.out.io_i({{".format(name
, count
))
274 for p
in self
.peripheral
.pinspecs
:
277 if not pname
.startswith('io'):
281 sname
= self
.peripheral
.pname(pname
).format(count
)
282 ps
= "pinmux.peripheral_side.%s_in" % sname
283 ret
.append(" {0},".format(ps
))
285 ret
.append(" endrule")
286 return '\n'.join(ret
)
291 def slowimport(self
):
292 return " import pwm::*;"
294 def slowifdecl(self
):
295 return " interface PWMIO pwm{0}_o;"
297 def num_axi_regs32(self
):
300 def mkslow_peripheral(self
, size
=0):
301 return " Ifc_PWM_bus pwm{0}_bus <- mkPWM_bus(sp_clock);"
303 def _mk_connection(self
, name
=None, count
=0):
304 return "pwm{0}_bus.axi4_slave"
306 def pinname_out(self
, pname
):
307 return {'out': 'pwm_io.pwm_o'}.get(pname
, '')
312 def slowimport(self
):
313 return " import pinmux::*;\n" + \
314 " import mux::*;\n" + \
317 def slowifdecl(self
):
318 return " interface GPIO_config#({1}) pad_config{0};"
320 def num_axi_regs32(self
):
323 def axi_slave_idx(self
, idx
, name
, ifacenum
):
324 """ generates AXI slave number definition, except
325 GPIO also has a muxer per bank
328 (ret
, x
) = PBase
.axi_slave_idx(self
, idx
, name
, ifacenum
)
329 (ret2
, x
) = PBase
.axi_slave_idx(self
, idx
, "mux", ifacenum
)
330 return ("%s\n%s" % (ret
, ret2
), 2)
332 def mkslow_peripheral(self
, size
=0):
333 print "gpioslow", self
.peripheral
, dir(self
.peripheral
)
334 size
= len(self
.peripheral
.pinspecs
)
335 return " MUX#(%d) mux{0} <- mkmux();\n" % size
+ \
336 " GPIO#(%d) gpio{0} <- mkgpio();" % size
338 def mk_connection(self
, count
):
339 print "GPIO mk_conn", self
.name
, count
341 dname
= self
.mksuffix(self
.name
, count
)
342 for i
, n
in enumerate(['gpio' + dname
, 'mux' + dname
]):
343 res
.append(PBase
.mk_connection(self
, count
, n
))
344 return '\n'.join(res
)
346 def _mk_connection(self
, name
=None, count
=0):
347 n
= self
.mksuffix(name
, count
)
348 if name
.startswith('gpio'):
349 return "gpio{0}.axi_slave".format(n
)
350 if name
.startswith('mux'):
351 return "mux{0}.axi_slave".format(n
)
353 def mksuffix(self
, name
, i
):
354 if name
.startswith('mux'):
358 def mk_cellconn(self
, cellnum
, name
, count
):
360 bank
= self
.mksuffix(name
, count
)
361 txt
= " pinmux.mux_lines.cell{0}_mux(mux{1}.mux_config.mux[{2}]);"
362 for p
in self
.peripheral
.pinspecs
:
363 ret
.append(txt
.format(cellnum
, bank
, p
['name'][1:]))
365 return ("\n".join(ret
), cellnum
)
367 def pinname_out(self
, pname
):
368 return "func.gpio_out[{0}]".format(pname
[1:])
370 def pinname_outen(self
, pname
):
371 return {'sda': 'out.sda_outen',
372 'scl': 'out.scl_outen'}.get(pname
, '')
374 def mk_pincon(self
, name
, count
):
375 ret
= [PBase
.mk_pincon(self
, name
, count
)]
376 # special-case for gpio in, store in a temporary vector
377 plen
= len(self
.peripheral
.pinspecs
)
378 ret
.append(" rule con_%s%d_in;" % (name
, count
))
379 ret
.append(" Vector#({0},Bit#(1)) temp;".format(plen
))
380 for p
in self
.peripheral
.pinspecs
:
385 sname
= self
.peripheral
.pname(pname
).format(count
)
386 ps
= "pinmux.peripheral_side.%s_in" % sname
387 ret
.append(" temp[{0}]={1};".format(idx
, ps
))
388 ret
.append(" {0}.func.gpio_in(temp);".format(name
))
389 ret
.append(" endrule")
390 return '\n'.join(ret
)
393 axi_slave_declarations
= """\
394 typedef 0 SlowMaster;
396 typedef TAdd#(LastGen_slave_num,`ifdef CLINT 1 `else 0 `endif )
398 typedef TAdd#(CLINT_slave_num ,`ifdef PLIC 1 `else 0 `endif )
400 typedef TAdd#(Plic_slave_num ,`ifdef AXIEXP 1 `else 0 `endif )
402 typedef TAdd#(AxiExp1_slave_num,1) Num_Slow_Slaves;
405 pinmux_cellrule
= """\
406 rule connect_select_lines_pinmux;
412 class CallFn(object):
413 def __init__(self
, peripheral
, name
):
414 self
.peripheral
= peripheral
417 def __call__(self
, *args
):
418 #print "__call__", self.name, self.peripheral.slow, args
419 if not self
.peripheral
.slow
:
421 return getattr(self
.peripheral
.slow
, self
.name
)(*args
[1:])
424 class PeripheralIface(object):
425 def __init__(self
, ifacename
):
427 slow
= slowfactory
.getcls(ifacename
)
428 print "Iface", ifacename
, slow
430 self
.slow
= slow(ifacename
)
431 self
.slow
.peripheral
= self
432 for fname
in ['slowimport', 'slowifdecl', 'mkslow_peripheral',
433 'mk_connection', 'mk_cellconn', 'mk_pincon']:
434 fn
= CallFn(self
, fname
)
435 setattr(self
, fname
, types
.MethodType(fn
, self
))
437 #print "PeripheralIface"
440 def mksuffix(self
, name
, i
):
441 if self
.slow
is None:
443 return self
.slow
.mksuffix(name
, i
)
445 def axi_reg_def(self
, start
, count
):
448 return self
.slow
.axi_reg_def(start
, self
.ifacename
, count
)
450 def axi_slave_idx(self
, start
, count
):
453 return self
.slow
.axi_slave_idx(start
, self
.ifacename
, count
)
455 def axi_addr_map(self
, count
):
458 return self
.slow
.axi_addr_map(self
.ifacename
, count
)
461 class PeripheralInterfaces(object):
465 def slowimport(self
, *args
):
467 for (name
, count
) in self
.ifacecount
:
468 #print "slowimport", name, self.data[name].slowimport
469 ret
.append(self
.data
[name
].slowimport())
470 return '\n'.join(list(filter(None, ret
)))
472 def slowifdecl(self
, *args
):
474 for (name
, count
) in self
.ifacecount
:
475 for i
in range(count
):
476 ret
.append(self
.data
[name
].slowifdecl().format(i
, name
))
477 return '\n'.join(list(filter(None, ret
)))
479 def axi_reg_def(self
, *args
):
481 start
= 0x00011100 # start of AXI peripherals address
482 for (name
, count
) in self
.ifacecount
:
483 for i
in range(count
):
484 x
= self
.data
[name
].axi_reg_def(start
, i
)
485 #print ("ifc", name, x)
489 return '\n'.join(list(filter(None, ret
)))
491 def axi_slave_idx(self
, *args
):
494 for (name
, count
) in self
.ifacecount
:
495 for i
in range(count
):
496 (rdef
, offs
) = self
.data
[name
].axi_slave_idx(start
, i
)
497 #print ("ifc", name, rdef, offs)
500 ret
.append("typedef %d LastGen_slave_num;" % (start
- 1))
501 decls
= '\n'.join(list(filter(None, ret
)))
502 return axi_slave_declarations
.format(decls
)
504 def axi_addr_map(self
, *args
):
506 for (name
, count
) in self
.ifacecount
:
507 for i
in range(count
):
508 ret
.append(self
.data
[name
].axi_addr_map(i
))
509 return '\n'.join(list(filter(None, ret
)))
511 def mkslow_peripheral(self
, *args
):
513 for (name
, count
) in self
.ifacecount
:
514 for i
in range(count
):
515 print "mkslow", name
, count
516 x
= self
.data
[name
].mkslow_peripheral()
518 suffix
= self
.data
[name
].mksuffix(name
, i
)
519 ret
.append(x
.format(suffix
))
520 return '\n'.join(list(filter(None, ret
)))
522 def mk_connection(self
, *args
):
524 for (name
, count
) in self
.ifacecount
:
525 for i
in range(count
):
526 print "mk_conn", name
, i
527 txt
= self
.data
[name
].mk_connection(i
)
530 print self
.data
[name
].mk_connection
532 return '\n'.join(list(filter(None, ret
)))
534 def mk_cellconn(self
):
537 for (name
, count
) in self
.ifacecount
:
538 for i
in range(count
):
539 res
= self
.data
[name
].mk_cellconn(cellcount
, name
, i
)
542 (txt
, cellcount
) = res
544 ret
= '\n'.join(list(filter(None, ret
)))
545 return pinmux_cellrule
.format(ret
)
549 for (name
, count
) in self
.ifacecount
:
550 for i
in range(count
):
551 txt
= self
.data
[name
].mk_pincon(name
, i
)
553 return '\n'.join(list(filter(None, ret
)))
556 class PFactory(object):
557 def getcls(self
, name
):
558 for k
, v
in {'uart': uart
,
565 if name
.startswith(k
):
570 slowfactory
= PFactory()
572 if __name__
== '__main__':
576 i
= PeripheralIface('uart')
578 i
= PeripheralIface('gpioa')