src/bsv/peripheral_gen.py

   1 import types
   2 from copy import deepcopy
   3
   4
   5 class PBase(object):
   6     def __init__(self, name):
   7         self.name = name
   8
   9     def slowifdeclmux(self):
  10         return ''
  11
  12     def slowimport(self):
  13         return ''
  14
  15     def num_axi_regs32(self):
  16         return 0
  17
  18     def slowifdecl(self):
  19         return ''
  20
  21     def axibase(self, name, ifacenum):
  22         name = name.upper()
  23         return "%(name)s%(ifacenum)dBase" % locals()
  24
  25     def axiend(self, name, ifacenum):
  26         name = name.upper()
  27         return "%(name)s%(ifacenum)dEnd" % locals()
  28
  29     def axi_reg_def(self, start, name, ifacenum):
  30         name = name.upper()
  31         offs = self.num_axi_regs32() * 4 * 16
  32         if offs == 0:
  33             return ('', 0)
  34         end = start + offs - 1
  35         bname = self.axibase(name, ifacenum)
  36         bend = self.axiend(name, ifacenum)
  37         comment = "%d 32-bit regs" % self.num_axi_regs32()
  38         return ("    `define %(bname)s 'h%(start)08X\n"
  39                 "    `define %(bend)s  'h%(end)08X // %(comment)s" % locals(),
  40                 offs)
  41
  42     def axi_slave_name(self, name, ifacenum):
  43         name = name.upper()
  44         return "{0}{1}_slave_num".format(name, ifacenum)
  45
  46     def axi_slave_idx(self, idx, name, ifacenum):
  47         name = self.axi_slave_name(name, ifacenum)
  48         return ("typedef {0} {1};".format(idx, name), 1)
  49
  50     def axi_addr_map(self, name, ifacenum):
  51         bname = self.axibase(name, ifacenum)
  52         bend = self.axiend(name, ifacenum)
  53         name = self.axi_slave_name(name, ifacenum)
  54         return """\
  55         if(addr>=`{0} && addr<=`{1})
  56             return tuple2(True,fromInteger(valueOf({2})));
  57         else""".format(bname, bend, name)
  58
  59     def mk_pincon(self, name, count):
  60         # TODO: really should be using bsv.interface_decl.Interfaces
  61         # pin-naming rules.... logic here is hard-coded to duplicate
  62         # it (see Interface.__init__ outen)
  63         ret = []
  64         for p in self.peripheral.pinspecs:
  65             typ = p['type']
  66             pname = p['name']
  67             #n = "{0}{1}".format(self.name, self.mksuffix(name, count))
  68             n = name  # "{0}{1}".format(self.name, self.mksuffix(name, count))
  69             ret.append("    //%s %s" % (n, str(p)))
  70             sname = self.peripheral.pname(pname).format(count)
  71             ps = "pinmux.peripheral_side.%s" % sname
  72             if typ == 'out' or typ == 'inout':
  73                 ret.append("    rule con_%s%d_%s_out;" % (name, count, pname))
  74                 fname = self.pinname_out(pname)
  75                 if not n.startswith('gpio'):  # XXX EURGH! horrible hack
  76                     n_ = "{0}{1}".format(n, count)
  77                 else:
  78                     n_ = n
  79                 if fname:
  80                     if p.get('outen'):
  81                         ps_ = ps + '_out'
  82                     else:
  83                         ps_ = ps
  84                     ret.append("      {0}({1}.{2});".format(ps_, n_, fname))
  85                 fname = None
  86                 if p.get('outen'):
  87                     fname = self.pinname_outen(pname)
  88                 if fname:
  89                     if isinstance(fname, str):
  90                         fname = "{0}.{1}".format(n_, fname)
  91                     fname = self.pinname_tweak(pname, 'outen', fname)
  92                     ret.append("      {0}_outen({1});".format(ps, fname))
  93                 ret.append("    endrule")
  94             if typ == 'in' or typ == 'inout':
  95                 fname = self.pinname_in(pname)
  96                 if fname:
  97                     if p.get('outen'):
  98                         ps_ = ps + '_in'
  99                     else:
 100                         ps_ = ps
 101                     ret.append(
 102                         "    rule con_%s%d_%s_in;" %
 103                         (name, count, pname))
 104                     n_ = "{0}{1}".format(n, count)
 105                     n_ = '{0}.{1}'.format(n_, fname)
 106                     n_ = self.ifname_tweak(pname, 'in', n_)
 107                     ret.append("      {1}({0});".format(ps_, n_))
 108                     ret.append("    endrule")
 109         return '\n'.join(ret)
 110
 111     def mk_cellconn(self, *args):
 112         return ''
 113
 114     def mkslow_peripheral(self, size=0):
 115         return ''
 116
 117     def mksuffix(self, name, i):
 118         return i
 119
 120     def __mk_connection(self, con, aname):
 121         txt = "        mkConnection (slow_fabric.v_to_slaves\n" + \
 122             "                    [fromInteger(valueOf({1}))],\n" + \
 123             "                    {0});"
 124
 125         print "PBase __mk_connection", self.name, aname
 126         if not con:
 127             return ''
 128         return txt.format(con, aname)
 129
 130     def mk_connection(self, count, name=None):
 131         if name is None:
 132             name = self.name
 133         print "PBase mk_conn", self.name, count
 134         aname = self.axi_slave_name(name, count)
 135         #dname = self.mksuffix(name, count)
 136         #dname = "{0}{1}".format(name, dname)
 137         con = self._mk_connection(name, count).format(count, aname)
 138         return self.__mk_connection(con, aname)
 139
 140     def _mk_connection(self, name=None, count=0):
 141         return ''
 142
 143     def pinname_out(self, pname):
 144         return ''
 145
 146     def pinname_in(self, pname):
 147         return ''
 148
 149     def pinname_outen(self, pname):
 150         return ''
 151
 152     def ifname_tweak(self, pname, typ, txt):
 153         return txt
 154
 155     def pinname_tweak(self, pname, typ, txt):
 156         return txt
 157
 158
 159 class uart(PBase):
 160
 161     def slowimport(self):
 162         return "          import Uart_bs         :: *;\n" + \
 163                "          import RS232_modified::*;"
 164
 165     def slowifdecl(self):
 166         return "            interface RS232 uart{0}_coe;\n" + \
 167                "            method Bit#(1) uart{0}_intr;"
 168
 169     def num_axi_regs32(self):
 170         return 8
 171
 172     def mkslow_peripheral(self, size=0):
 173         return "        Ifc_Uart_bs uart{0} <- \n" + \
 174                "                mkUart_bs(clocked_by sp_clock,\n" + \
 175                "                    reset_by uart_reset, sp_clock, sp_reset);"
 176
 177     def _mk_connection(self, name=None, count=0):
 178         return "uart{0}.slave_axi_uart"
 179
 180     def pinname_out(self, pname):
 181         return {'tx': 'coe_rs232.sout'}.get(pname, '')
 182
 183     def pinname_in(self, pname):
 184         return {'rx': 'coe_rs232.sin'}.get(pname, '')
 185
 186
 187 class qquart(PBase):
 188
 189     def slowimport(self):
 190         return "          import Uart16550         :: *;"
 191
 192     def slowifdecl(self):
 193         return "            interface RS232_PHY_Ifc uart{0}_coe;\n" + \
 194                "            method Bit#(1) uart{0}_intr;"
 195
 196     def num_axi_regs32(self):
 197         return 8
 198
 199     def mkslow_peripheral(self, size=0):
 200         return "        Uart16550_AXI4_Lite_Ifc uart{0} <- \n" + \
 201                "                mkUart16550(clocked_by sp_clock,\n" + \
 202                "                    reset_by uart_reset, sp_clock, sp_reset);"
 203
 204     def _mk_connection(self, name=None, count=0):
 205         return "uart{0}.slave_axi_uart"
 206
 207     def pinname_out(self, pname):
 208         return {'tx': 'coe_rs232.sout'}.get(pname, '')
 209
 210     def pinname_in(self, pname):
 211         return {'rx': 'coe_rs232.sin'}.get(pname, '')
 212
 213
 214 class rs232(PBase):
 215
 216     def slowimport(self):
 217         return "        import Uart_bs::*;\n" + \
 218                "        import RS232_modified::*;"
 219
 220     def slowifdecl(self):
 221         return "            interface RS232 uart{0}_coe;"
 222
 223     def num_axi_regs32(self):
 224         return 2
 225
 226     def mkslow_peripheral(self, size=0):
 227         return "        //Ifc_Uart_bs uart{0} <-" + \
 228                "        //       mkUart_bs(clocked_by uart_clock,\n" + \
 229                "        //          reset_by uart_reset,sp_clock, sp_reset);" +\
 230                "        Ifc_Uart_bs uart{0} <-" + \
 231                "                mkUart_bs(clocked_by sp_clock,\n" + \
 232                "                    reset_by sp_reset, sp_clock, sp_reset);"
 233
 234     def _mk_connection(self, name=None, count=0):
 235         return "uart{0}.slave_axi_uart"
 236
 237     def pinname_out(self, pname):
 238         return {'tx': 'coe_rs232.sout'}.get(pname, '')
 239
 240     def pinname_in(self, pname):
 241         return {'rx': 'coe_rs232.sin'}.get(pname, '')
 242
 243
 244 class twi(PBase):
 245
 246     def slowimport(self):
 247         return "        import I2C_top           :: *;"
 248
 249     def slowifdecl(self):
 250         return "            interface I2C_out twi{0}_out;\n" + \
 251                "            method Bit#(1) twi{0}_isint;"
 252
 253     def num_axi_regs32(self):
 254         return 8
 255
 256     def mkslow_peripheral(self, size=0):
 257         return "        I2C_IFC twi{0} <- mkI2CController();"
 258
 259     def _mk_connection(self, name=None, count=0):
 260         return "twi{0}.slave_i2c_axi"
 261
 262     def pinname_out(self, pname):
 263         return {'sda': 'out.sda_out',
 264                 'scl': 'out.scl_out'}.get(pname, '')
 265
 266     def pinname_in(self, pname):
 267         return {'sda': 'out.sda_in',
 268                 'scl': 'out.scl_in'}.get(pname, '')
 269
 270     def pinname_outen(self, pname):
 271         return {'sda': 'out.sda_out_en',
 272                 'scl': 'out.scl_out_en'}.get(pname, '')
 273
 274     def pinname_tweak(self, pname, typ, txt):
 275         if typ == 'outen':
 276             return "pack({0})".format(txt)
 277         return txt
 278
 279
 280 class eint(PBase):
 281
 282     def slowimport(self):
 283         size = len(self.peripheral.pinspecs)
 284         return "    `define NUM_EINTS %d" % size
 285
 286     def mkslow_peripheral(self, size=0):
 287         size = len(self.peripheral.pinspecs)
 288         return "        Wire#(Bit#(%d)) wr_interrupt <- mkWire();" % size
 289
 290     def axi_slave_name(self, name, ifacenum):
 291         return ''
 292
 293     def axi_slave_idx(self, idx, name, ifacenum):
 294         return ('', 0)
 295
 296     def axi_addr_map(self, name, ifacenum):
 297         return ''
 298
 299     def ifname_tweak(self, pname, typ, txt):
 300         if typ != 'in':
 301             return txt
 302         print "ifnameweak", pname, typ, txt
 303         return "wr_interrupt[{0}] <= ".format(pname)
 304
 305     def mk_pincon(self, name, count):
 306         ret = [PBase.mk_pincon(self, name, count)]
 307         size = len(self.peripheral.pinspecs)
 308         ret.append(eint_pincon_template.format(size))
 309         ret.append("    rule con_%s%d_io_in;" % (name, count))
 310         ret.append("    wr_interrupt <= ({")
 311         for idx, p in enumerate(self.peripheral.pinspecs):
 312             pname = p['name']
 313             sname = self.peripheral.pname(pname).format(count)
 314             ps = "pinmux.peripheral_side.%s" % sname
 315             comma = '' if idx == size - 1 else ','
 316             ret.append("             {0}{1}".format(ps, comma))
 317         ret.append("        });")
 318         ret.append("    endrule")
 319
 320         return '\n'.join(ret)
 321
 322
 323 eint_pincon_template = '''\
 324     // TODO: offset i by the number of eints already used
 325     for(Integer i=0;i<{0};i=i+ 1)begin
 326       rule connect_int_to_plic(wr_interrupt[i]==1);
 327                 ff_gateway_queue[i].enq(1);
 328                 plic.ifc_external_irq[i].irq_frm_gateway(True);
 329       endrule
 330     end
 331 '''
 332
 333
 334 class sdmmc(PBase):
 335
 336     def slowimport(self):
 337         return "        import sdcard_dummy              :: *;"
 338
 339     def slowifdecl(self):
 340         return "            interface QSPI_out sd{0}_out;\n" + \
 341                "            method Bit#(1) sd{0}_isint;"
 342
 343     def num_axi_regs32(self):
 344         return 13
 345
 346     def mkslow_peripheral(self):
 347         return "        Ifc_sdcard_dummy sd{0} <-  mksdcard_dummy();"
 348
 349     def _mk_connection(self, name=None, count=0):
 350         return "sd{0}.slave"
 351
 352     def pinname_in(self, pname):
 353         return "%s_in" % pname
 354
 355     def pinname_out(self, pname):
 356         if pname.startswith('d'):
 357             return "%s_out" % pname
 358         return pname
 359
 360     def pinname_outen(self, pname):
 361         if pname.startswith('d'):
 362             return "%s_outen" % pname
 363
 364
 365 class spi(PBase):
 366
 367     def slowimport(self):
 368         return "        import qspi              :: *;"
 369
 370     def slowifdecl(self):
 371         return "            interface QSPI_out spi{0}_out;\n" + \
 372                "            method Bit#(1) spi{0}_isint;"
 373
 374     def num_axi_regs32(self):
 375         return 13
 376
 377     def mkslow_peripheral(self):
 378         return "        Ifc_qspi spi{0} <-  mkqspi();"
 379
 380     def _mk_connection(self, name=None, count=0):
 381         return "spi{0}.slave"
 382
 383     def pinname_out(self, pname):
 384         return {'clk': 'out.clk_o',
 385                 'nss': 'out.ncs_o',
 386                 'mosi': 'out.io_o[0]',
 387                 'miso': 'out.io_o[1]',
 388                 }.get(pname, '')
 389
 390     def pinname_outen(self, pname):
 391         return {'clk': 1,
 392                 'nss': 1,
 393                 'mosi': 'out.io_enable[0]',
 394                 'miso': 'out.io_enable[1]',
 395                 }.get(pname, '')
 396
 397     def mk_pincon(self, name, count):
 398         ret = [PBase.mk_pincon(self, name, count)]
 399         # special-case for gpio in, store in a temporary vector
 400         plen = len(self.peripheral.pinspecs)
 401         ret.append("    // XXX NSS and CLK are hard-coded master")
 402         ret.append("    // TODO: must add spi slave-mode")
 403         ret.append("    // all ins done in one rule from 4-bitfield")
 404         ret.append("    rule con_%s%d_io_in;" % (name, count))
 405         ret.append("       {0}{1}.out.io_i({{".format(name, count))
 406         for idx, pname in enumerate(['mosi', 'miso']):
 407             sname = self.peripheral.pname(pname).format(count)
 408             ps = "pinmux.peripheral_side.%s_in" % sname
 409             ret.append("            {0},".format(ps))
 410         ret.append("            1'b0,1'b0")
 411         ret.append("        });")
 412         ret.append("    endrule")
 413         return '\n'.join(ret)
 414
 415
 416 class qspi(PBase):
 417
 418     def slowimport(self):
 419         return "        import qspi              :: *;"
 420
 421     def slowifdecl(self):
 422         return "            interface QSPI_out qspi{0}_out;\n" + \
 423                "            method Bit#(1) qspi{0}_isint;"
 424
 425     def num_axi_regs32(self):
 426         return 13
 427
 428     def mkslow_peripheral(self, size=0):
 429         return "        Ifc_qspi qspi{0} <-  mkqspi();"
 430
 431     def _mk_connection(self, name=None, count=0):
 432         return "qspi{0}.slave"
 433
 434     def pinname_out(self, pname):
 435         return {'ck': 'out.clk_o',
 436                 'nss': 'out.ncs_o',
 437                 'io0': 'out.io_o[0]',
 438                 'io1': 'out.io_o[1]',
 439                 'io2': 'out.io_o[2]',
 440                 'io3': 'out.io_o[3]',
 441                 }.get(pname, '')
 442
 443     def pinname_outen(self, pname):
 444         return {'ck': 1,
 445                 'nss': 1,
 446                 'io0': 'out.io_enable[0]',
 447                 'io1': 'out.io_enable[1]',
 448                 'io2': 'out.io_enable[2]',
 449                 'io3': 'out.io_enable[3]',
 450                 }.get(pname, '')
 451
 452     def mk_pincon(self, name, count):
 453         ret = [PBase.mk_pincon(self, name, count)]
 454         # special-case for gpio in, store in a temporary vector
 455         plen = len(self.peripheral.pinspecs)
 456         ret.append("    // XXX NSS and CLK are hard-coded master")
 457         ret.append("    // TODO: must add qspi slave-mode")
 458         ret.append("    // all ins done in one rule from 4-bitfield")
 459         ret.append("    rule con_%s%d_io_in;" % (name, count))
 460         ret.append("       {0}{1}.out.io_i({{".format(name, count))
 461         for i, p in enumerate(self.peripheral.pinspecs):
 462             typ = p['type']
 463             pname = p['name']
 464             if not pname.startswith('io'):
 465                 continue
 466             idx = pname[1:]
 467             n = name
 468             sname = self.peripheral.pname(pname).format(count)
 469             ps = "pinmux.peripheral_side.%s_in" % sname
 470             comma = '' if i == 5 else ','
 471             ret.append("            {0}{1}".format(ps, comma))
 472         ret.append("        });")
 473         ret.append("    endrule")
 474         return '\n'.join(ret)
 475
 476
 477 class pwm(PBase):
 478
 479     def slowimport(self):
 480         return "        import pwm::*;"
 481
 482     def slowifdecl(self):
 483         return "        interface PWMIO pwm{0}_io;"
 484
 485     def num_axi_regs32(self):
 486         return 4
 487
 488     def mkslow_peripheral(self, size=0):
 489         return "        Ifc_PWM_bus pwm{0} <- mkPWM_bus(sp_clock);"
 490
 491     def _mk_connection(self, name=None, count=0):
 492         return "pwm{0}.axi4_slave"
 493
 494     def pinname_out(self, pname):
 495         return {'out': 'pwm_io.pwm_o'}.get(pname, '')
 496
 497
 498 class gpio(PBase):
 499
 500     def slowimport(self):
 501         return "     import pinmux::*;\n" + \
 502                "     import mux::*;\n" + \
 503                "     import gpio::*;\n"
 504
 505     def slowifdeclmux(self):
 506         size = len(self.peripheral.pinspecs)
 507         return "    interface GPIO_config#(%d) pad_config{0};" % size
 508
 509     def num_axi_regs32(self):
 510         return 2
 511
 512     def axi_slave_idx(self, idx, name, ifacenum):
 513         """ generates AXI slave number definition, except
 514             GPIO also has a muxer per bank
 515         """
 516         name = name.upper()
 517         mname = 'mux' + name[4:]
 518         mname = mname.upper()
 519         print "AXIslavenum", name, mname
 520         (ret, x) = PBase.axi_slave_idx(self, idx, name, ifacenum)
 521         (ret2, x) = PBase.axi_slave_idx(self, idx + 1, mname, ifacenum)
 522         return ("%s\n%s" % (ret, ret2), 2)
 523
 524     def mkslow_peripheral(self, size=0):
 525         print "gpioslow", self.peripheral, dir(self.peripheral)
 526         size = len(self.peripheral.pinspecs)
 527         return "        MUX#(%d) mux{0} <- mkmux();\n" % size + \
 528                "        GPIO#(%d) gpio{0} <- mkgpio();" % size
 529
 530     def mk_connection(self, count):
 531         print "GPIO mk_conn", self.name, count
 532         res = []
 533         dname = self.mksuffix(self.name, count)
 534         for i, n in enumerate(['gpio' + dname, 'mux' + dname]):
 535             res.append(PBase.mk_connection(self, count, n))
 536         return '\n'.join(res)
 537
 538     def _mk_connection(self, name=None, count=0):
 539         n = self.mksuffix(name, count)
 540         if name.startswith('gpio'):
 541             return "gpio{0}.axi_slave".format(n)
 542         if name.startswith('mux'):
 543             return "mux{0}.axi_slave".format(n)
 544
 545     def mksuffix(self, name, i):
 546         if name.startswith('mux'):
 547             return name[3:]
 548         return name[4:]
 549
 550     def mk_cellconn(self, cellnum, name, count):
 551         ret = []
 552         bank = self.mksuffix(name, count)
 553         txt = "       pinmux.mux_lines.cell{0}_mux(mux{1}.mux_config.mux[{2}]);"
 554         for p in self.peripheral.pinspecs:
 555             ret.append(txt.format(cellnum, bank, p['name'][1:]))
 556             cellnum += 1
 557         return ("\n".join(ret), cellnum)
 558
 559     def pinname_out(self, pname):
 560         return "func.gpio_out[{0}]".format(pname[1:])
 561
 562     def pinname_outen(self, pname):
 563         return "func.gpio_out_en[{0}]".format(pname[1:])
 564
 565     def mk_pincon(self, name, count):
 566         ret = [PBase.mk_pincon(self, name, count)]
 567         # special-case for gpio in, store in a temporary vector
 568         plen = len(self.peripheral.pinspecs)
 569         ret.append("    rule con_%s%d_in;" % (name, count))
 570         ret.append("       Vector#({0},Bit#(1)) temp;".format(plen))
 571         for p in self.peripheral.pinspecs:
 572             typ = p['type']
 573             pname = p['name']
 574             idx = pname[1:]
 575             n = name
 576             sname = self.peripheral.pname(pname).format(count)
 577             ps = "pinmux.peripheral_side.%s_in" % sname
 578             ret.append("        temp[{0}]={1};".format(idx, ps))
 579         ret.append("        {0}.func.gpio_in(temp);".format(name))
 580         ret.append("    endrule")
 581         return '\n'.join(ret)
 582
 583
 584 axi_slave_declarations = """\
 585 typedef  0  SlowMaster;
 586 {0}
 587 typedef  TAdd#(LastGen_slave_num,`ifdef CLINT       1 `else 0 `endif )
 588               CLINT_slave_num;
 589 typedef  TAdd#(CLINT_slave_num  ,`ifdef PLIC        1 `else 0 `endif )
 590               Plic_slave_num;
 591 typedef  TAdd#(Plic_slave_num   ,`ifdef AXIEXP      1 `else 0 `endif )
 592               AxiExp1_slave_num;
 593 typedef TAdd#(AxiExp1_slave_num,1) Num_Slow_Slaves;
 594 """
 595
 596 pinmux_cellrule = """\
 597     rule connect_select_lines_pinmux;
 598 {0}
 599     endrule
 600 """
 601
 602
 603 class CallFn(object):
 604     def __init__(self, peripheral, name):
 605         self.peripheral = peripheral
 606         self.name = name
 607
 608     def __call__(self, *args):
 609         #print "__call__", self.name, self.peripheral.slow, args
 610         if not self.peripheral.slow:
 611             return ''
 612         return getattr(self.peripheral.slow, self.name)(*args[1:])
 613
 614
 615 class PeripheralIface(object):
 616     def __init__(self, ifacename):
 617         self.slow = None
 618         slow = slowfactory.getcls(ifacename)
 619         print "Iface", ifacename, slow
 620         if slow:
 621             self.slow = slow(ifacename)
 622             self.slow.peripheral = self
 623         for fname in ['slowimport', 'slowifdecl', 'slowifdeclmux',
 624                       'mkslow_peripheral',
 625                       'mk_connection', 'mk_cellconn', 'mk_pincon']:
 626             fn = CallFn(self, fname)
 627             setattr(self, fname, types.MethodType(fn, self))
 628
 629         #print "PeripheralIface"
 630         #print dir(self)
 631
 632     def mksuffix(self, name, i):
 633         if self.slow is None:
 634             return i
 635         return self.slow.mksuffix(name, i)
 636
 637     def axi_reg_def(self, start, count):
 638         if not self.slow:
 639             return ('', 0)
 640         return self.slow.axi_reg_def(start, self.ifacename, count)
 641
 642     def axi_slave_idx(self, start, count):
 643         if not self.slow:
 644             return ('', 0)
 645         return self.slow.axi_slave_idx(start, self.ifacename, count)
 646
 647     def axi_addr_map(self, count):
 648         if not self.slow:
 649             return ''
 650         return self.slow.axi_addr_map(self.ifacename, count)
 651
 652
 653 class PeripheralInterfaces(object):
 654     def __init__(self):
 655         pass
 656
 657     def slowimport(self, *args):
 658         ret = []
 659         for (name, count) in self.ifacecount:
 660             #print "slowimport", name, self.data[name].slowimport
 661             ret.append(self.data[name].slowimport())
 662         return '\n'.join(list(filter(None, ret)))
 663
 664     def slowifdeclmux(self, *args):
 665         ret = []
 666         for (name, count) in self.ifacecount:
 667             for i in range(count):
 668                 ret.append(self.data[name].slowifdeclmux().format(i, name))
 669         return '\n'.join(list(filter(None, ret)))
 670
 671     def slowifdecl(self, *args):
 672         ret = []
 673         for (name, count) in self.ifacecount:
 674             for i in range(count):
 675                 ret.append(self.data[name].slowifdecl().format(i, name))
 676         return '\n'.join(list(filter(None, ret)))
 677
 678     def axi_reg_def(self, *args):
 679         ret = []
 680         start = 0x00011100  # start of AXI peripherals address
 681         for (name, count) in self.ifacecount:
 682             for i in range(count):
 683                 x = self.data[name].axi_reg_def(start, i)
 684                 #print ("ifc", name, x)
 685                 (rdef, offs) = x
 686                 ret.append(rdef)
 687                 start += offs
 688         return '\n'.join(list(filter(None, ret)))
 689
 690     def axi_slave_idx(self, *args):
 691         ret = []
 692         start = 0
 693         for (name, count) in self.ifacecount:
 694             for i in range(count):
 695                 (rdef, offs) = self.data[name].axi_slave_idx(start, i)
 696                 #print ("ifc", name, rdef, offs)
 697                 ret.append(rdef)
 698                 start += offs
 699         ret.append("typedef %d LastGen_slave_num;" % (start - 1))
 700         decls = '\n'.join(list(filter(None, ret)))
 701         return axi_slave_declarations.format(decls)
 702
 703     def axi_addr_map(self, *args):
 704         ret = []
 705         for (name, count) in self.ifacecount:
 706             for i in range(count):
 707                 ret.append(self.data[name].axi_addr_map(i))
 708         return '\n'.join(list(filter(None, ret)))
 709
 710     def mkslow_peripheral(self, *args):
 711         ret = []
 712         for (name, count) in self.ifacecount:
 713             for i in range(count):
 714                 print "mkslow", name, count
 715                 x = self.data[name].mkslow_peripheral()
 716                 print name, count, x
 717                 suffix = self.data[name].mksuffix(name, i)
 718                 ret.append(x.format(suffix))
 719         return '\n'.join(list(filter(None, ret)))
 720
 721     def mk_connection(self, *args):
 722         ret = []
 723         for (name, count) in self.ifacecount:
 724             for i in range(count):
 725                 print "mk_conn", name, i
 726                 txt = self.data[name].mk_connection(i)
 727                 if name == 'gpioa':
 728                     print "txt", txt
 729                     print self.data[name].mk_connection
 730                 ret.append(txt)
 731         return '\n'.join(list(filter(None, ret)))
 732
 733     def mk_cellconn(self):
 734         ret = []
 735         cellcount = 0
 736         for (name, count) in self.ifacecount:
 737             for i in range(count):
 738                 res = self.data[name].mk_cellconn(cellcount, name, i)
 739                 if not res:
 740                     continue
 741                 (txt, cellcount) = res
 742                 ret.append(txt)
 743         ret = '\n'.join(list(filter(None, ret)))
 744         return pinmux_cellrule.format(ret)
 745
 746     def mk_pincon(self):
 747         ret = []
 748         for (name, count) in self.ifacecount:
 749             for i in range(count):
 750                 txt = self.data[name].mk_pincon(name, i)
 751                 ret.append(txt)
 752         return '\n'.join(list(filter(None, ret)))
 753
 754
 755 class PFactory(object):
 756     def getcls(self, name):
 757         for k, v in {'uart': uart,
 758                      'rs232': rs232,
 759                      'twi': twi,
 760                      'qspi': qspi,
 761                      'spi': spi,
 762                      'pwm': pwm,
 763                      'eint': eint,
 764                      'sd': sdmmc,
 765                      'gpio': gpio
 766                      }.items():
 767             if name.startswith(k):
 768                 return v
 769         return None
 770
 771
 772 slowfactory = PFactory()
 773
 774 if __name__ == '__main__':
 775     p = uart('uart')
 776     print p.slowimport()
 777     print p.slowifdecl()
 778     i = PeripheralIface('uart')
 779     print i, i.slow
 780     i = PeripheralIface('gpioa')
 781     print i, i.slow