src/bsv/peripheral_gen.py

   1 import types
   2 from copy import deepcopy
   3
   4
   5 class PBase(object):
   6     def __init__(self, name):
   7         self.name = name
   8
   9     def slowifdeclmux(self):
  10         return ''
  11
  12     def slowifinstance(self):
  13         return ''
  14
  15     def slowimport(self):
  16         return ''
  17
  18     def num_axi_regs32(self):
  19         return 0
  20
  21     def slowifdecl(self):
  22         return ''
  23
  24     def axibase(self, name, ifacenum):
  25         name = name.upper()
  26         return "%(name)s%(ifacenum)dBase" % locals()
  27
  28     def axiend(self, name, ifacenum):
  29         name = name.upper()
  30         return "%(name)s%(ifacenum)dEnd" % locals()
  31
  32     def axi_reg_def(self, start, name, ifacenum):
  33         name = name.upper()
  34         offs = self.num_axi_regs32() * 4 * 16
  35         if offs == 0:
  36             return ('', 0)
  37         end = start + offs - 1
  38         bname = self.axibase(name, ifacenum)
  39         bend = self.axiend(name, ifacenum)
  40         comment = "%d 32-bit regs" % self.num_axi_regs32()
  41         return ("    `define %(bname)s 'h%(start)08X\n"
  42                 "    `define %(bend)s  'h%(end)08X // %(comment)s" % locals(),
  43                 offs)
  44
  45     def axi_slave_name(self, name, ifacenum):
  46         name = name.upper()
  47         return "{0}{1}_slave_num".format(name, ifacenum)
  48
  49     def axi_slave_idx(self, idx, name, ifacenum):
  50         name = self.axi_slave_name(name, ifacenum)
  51         return ("typedef {0} {1};".format(idx, name), 1)
  52
  53     def axi_addr_map(self, name, ifacenum):
  54         bname = self.axibase(name, ifacenum)
  55         bend = self.axiend(name, ifacenum)
  56         name = self.axi_slave_name(name, ifacenum)
  57         return """\
  58         if(addr>=`{0} && addr<=`{1})
  59             return tuple2(True,fromInteger(valueOf({2})));
  60         else""".format(bname, bend, name)
  61
  62     def mk_pincon(self, name, count):
  63         # TODO: really should be using bsv.interface_decl.Interfaces
  64         # pin-naming rules.... logic here is hard-coded to duplicate
  65         # it (see Interface.__init__ outen)
  66         ret = []
  67         for p in self.peripheral.pinspecs:
  68             typ = p['type']
  69             pname = p['name']
  70             #n = "{0}{1}".format(self.name, self.mksuffix(name, count))
  71             n = name  # "{0}{1}".format(self.name, self.mksuffix(name, count))
  72             ret.append("    //%s %s" % (n, str(p)))
  73             sname = self.peripheral.pname(pname).format(count)
  74             ps = "pinmux.peripheral_side.%s" % sname
  75             if typ == 'out' or typ == 'inout':
  76                 ret.append("    rule con_%s%d_%s_out;" % (name, count, pname))
  77                 fname = self.pinname_out(pname)
  78                 if not n.startswith('gpio'):  # XXX EURGH! horrible hack
  79                     n_ = "{0}{1}".format(n, count)
  80                 else:
  81                     n_ = n
  82                 if fname:
  83                     if p.get('outen'):
  84                         ps_ = ps + '_out'
  85                     else:
  86                         ps_ = ps
  87                     ret.append("      {0}({1}.{2});".format(ps_, n_, fname))
  88                 fname = None
  89                 if p.get('outen'):
  90                     fname = self.pinname_outen(pname)
  91                 if fname:
  92                     if isinstance(fname, str):
  93                         fname = "{0}.{1}".format(n_, fname)
  94                     fname = self.pinname_tweak(pname, 'outen', fname)
  95                     ret.append("      {0}_outen({1});".format(ps, fname))
  96                 ret.append("    endrule")
  97             if typ == 'in' or typ == 'inout':
  98                 fname = self.pinname_in(pname)
  99                 if fname:
 100                     if p.get('outen'):
 101                         ps_ = ps + '_in'
 102                     else:
 103                         ps_ = ps
 104                     ret.append(
 105                         "    rule con_%s%d_%s_in;" %
 106                         (name, count, pname))
 107                     n_ = "{0}{1}".format(n, count)
 108                     n_ = '{0}.{1}'.format(n_, fname)
 109                     n_ = self.ifname_tweak(pname, 'in', n_)
 110                     ret.append("      {1}({0});".format(ps_, n_))
 111                     ret.append("    endrule")
 112         return '\n'.join(ret)
 113
 114     def mk_cellconn(self, *args):
 115         return ''
 116
 117     def mkslow_peripheral(self, size=0):
 118         return ''
 119
 120     def mksuffix(self, name, i):
 121         return i
 122
 123     def __mk_connection(self, con, aname):
 124         txt = "        mkConnection (slow_fabric.v_to_slaves\n" + \
 125             "                    [fromInteger(valueOf({1}))],\n" + \
 126             "                    {0});"
 127
 128         print "PBase __mk_connection", self.name, aname
 129         if not con:
 130             return ''
 131         return txt.format(con, aname)
 132
 133     def mk_connection(self, count, name=None):
 134         if name is None:
 135             name = self.name
 136         print "PBase mk_conn", self.name, count
 137         aname = self.axi_slave_name(name, count)
 138         #dname = self.mksuffix(name, count)
 139         #dname = "{0}{1}".format(name, dname)
 140         con = self._mk_connection(name, count).format(count, aname)
 141         return self.__mk_connection(con, aname)
 142
 143     def _mk_connection(self, name=None, count=0):
 144         return ''
 145
 146     def pinname_out(self, pname):
 147         return ''
 148
 149     def pinname_in(self, pname):
 150         return ''
 151
 152     def pinname_outen(self, pname):
 153         return ''
 154
 155     def ifname_tweak(self, pname, typ, txt):
 156         return txt
 157
 158     def pinname_tweak(self, pname, typ, txt):
 159         return txt
 160
 161
 162 class uart(PBase):
 163
 164     def slowimport(self):
 165         return "          import Uart_bs         :: *;\n" + \
 166                "          import RS232_modified::*;"
 167
 168     def slowifdecl(self):
 169         return "            interface RS232 uart{0}_coe;\n" + \
 170                "            method Bit#(1) uart{0}_intr;"
 171
 172     def num_axi_regs32(self):
 173         return 8
 174
 175     def mkslow_peripheral(self, size=0):
 176         return "        Ifc_Uart_bs uart{0} <- \n" + \
 177                "                mkUart_bs(clocked_by sp_clock,\n" + \
 178                "                    reset_by uart_reset, sp_clock, sp_reset);"
 179
 180     def _mk_connection(self, name=None, count=0):
 181         return "uart{0}.slave_axi_uart"
 182
 183     def pinname_out(self, pname):
 184         return {'tx': 'coe_rs232.sout'}.get(pname, '')
 185
 186     def pinname_in(self, pname):
 187         return {'rx': 'coe_rs232.sin'}.get(pname, '')
 188
 189
 190 class qquart(PBase):
 191
 192     def slowimport(self):
 193         return "          import Uart16550         :: *;"
 194
 195     def slowifdecl(self):
 196         return "            interface RS232_PHY_Ifc uart{0}_coe;\n" + \
 197                "            method Bit#(1) uart{0}_intr;"
 198
 199     def num_axi_regs32(self):
 200         return 8
 201
 202     def mkslow_peripheral(self, size=0):
 203         return "        Uart16550_AXI4_Lite_Ifc uart{0} <- \n" + \
 204                "                mkUart16550(clocked_by sp_clock,\n" + \
 205                "                    reset_by uart_reset, sp_clock, sp_reset);"
 206
 207     def _mk_connection(self, name=None, count=0):
 208         return "uart{0}.slave_axi_uart"
 209
 210     def pinname_out(self, pname):
 211         return {'tx': 'coe_rs232.sout'}.get(pname, '')
 212
 213     def pinname_in(self, pname):
 214         return {'rx': 'coe_rs232.sin'}.get(pname, '')
 215
 216
 217 class rs232(PBase):
 218
 219     def slowimport(self):
 220         return "        import Uart_bs::*;\n" + \
 221                "        import RS232_modified::*;"
 222
 223     def slowifdecl(self):
 224         return "            interface RS232 uart{0}_coe;"
 225
 226     def num_axi_regs32(self):
 227         return 2
 228
 229     def mkslow_peripheral(self, size=0):
 230         return "        //Ifc_Uart_bs uart{0} <-" + \
 231                "        //       mkUart_bs(clocked_by uart_clock,\n" + \
 232                "        //          reset_by uart_reset,sp_clock, sp_reset);" +\
 233                "        Ifc_Uart_bs uart{0} <-" + \
 234                "                mkUart_bs(clocked_by sp_clock,\n" + \
 235                "                    reset_by sp_reset, sp_clock, sp_reset);"
 236
 237     def _mk_connection(self, name=None, count=0):
 238         return "uart{0}.slave_axi_uart"
 239
 240     def pinname_out(self, pname):
 241         return {'tx': 'coe_rs232.sout'}.get(pname, '')
 242
 243     def pinname_in(self, pname):
 244         return {'rx': 'coe_rs232.sin'}.get(pname, '')
 245
 246
 247 class twi(PBase):
 248
 249     def slowimport(self):
 250         return "        import I2C_top           :: *;"
 251
 252     def slowifdecl(self):
 253         return "            interface I2C_out twi{0}_out;\n" + \
 254                "            method Bit#(1) twi{0}_isint;"
 255
 256     def num_axi_regs32(self):
 257         return 8
 258
 259     def mkslow_peripheral(self, size=0):
 260         return "        I2C_IFC twi{0} <- mkI2CController();"
 261
 262     def _mk_connection(self, name=None, count=0):
 263         return "twi{0}.slave_i2c_axi"
 264
 265     def pinname_out(self, pname):
 266         return {'sda': 'out.sda_out',
 267                 'scl': 'out.scl_out'}.get(pname, '')
 268
 269     def pinname_in(self, pname):
 270         return {'sda': 'out.sda_in',
 271                 'scl': 'out.scl_in'}.get(pname, '')
 272
 273     def pinname_outen(self, pname):
 274         return {'sda': 'out.sda_out_en',
 275                 'scl': 'out.scl_out_en'}.get(pname, '')
 276
 277     def pinname_tweak(self, pname, typ, txt):
 278         if typ == 'outen':
 279             return "pack({0})".format(txt)
 280         return txt
 281
 282
 283 class eint(PBase):
 284
 285     def slowimport(self):
 286         size = len(self.peripheral.pinspecs)
 287         return "    `define NUM_EINTS %d" % size
 288
 289     def mkslow_peripheral(self, size=0):
 290         size = len(self.peripheral.pinspecs)
 291         return "        Wire#(Bit#(%d)) wr_interrupt <- mkWire();" % size
 292
 293     def axi_slave_name(self, name, ifacenum):
 294         return ''
 295
 296     def axi_slave_idx(self, idx, name, ifacenum):
 297         return ('', 0)
 298
 299     def axi_addr_map(self, name, ifacenum):
 300         return ''
 301
 302     def ifname_tweak(self, pname, typ, txt):
 303         if typ != 'in':
 304             return txt
 305         print "ifnameweak", pname, typ, txt
 306         return "wr_interrupt[{0}] <= ".format(pname)
 307
 308     def mk_pincon(self, name, count):
 309         ret = [PBase.mk_pincon(self, name, count)]
 310         size = len(self.peripheral.pinspecs)
 311         ret.append(eint_pincon_template.format(size))
 312         ret.append("    rule con_%s%d_io_in;" % (name, count))
 313         ret.append("    wr_interrupt <= ({")
 314         for idx, p in enumerate(self.peripheral.pinspecs):
 315             pname = p['name']
 316             sname = self.peripheral.pname(pname).format(count)
 317             ps = "pinmux.peripheral_side.%s" % sname
 318             comma = '' if idx == size - 1 else ','
 319             ret.append("             {0}{1}".format(ps, comma))
 320         ret.append("        });")
 321         ret.append("    endrule")
 322
 323         return '\n'.join(ret)
 324
 325
 326 eint_pincon_template = '''\
 327     // TODO: offset i by the number of eints already used
 328     for(Integer i=0;i<{0};i=i+ 1)begin
 329       rule connect_int_to_plic(wr_interrupt[i]==1);
 330                 ff_gateway_queue[i].enq(1);
 331                 plic.ifc_external_irq[i].irq_frm_gateway(True);
 332       endrule
 333     end
 334 '''
 335
 336
 337 class jtag(PBase):
 338
 339     def axi_slave_name(self, name, ifacenum):
 340         return ''
 341
 342     def axi_slave_idx(self, idx, name, ifacenum):
 343         return ('', 0)
 344
 345     def axi_addr_map(self, name, ifacenum):
 346         return ''
 347
 348     def slowifdeclmux(self):
 349         return "            method  Action jtag_ms (Bit#(1) in);\n" +  \
 350                "            method  Bit#(1) jtag_di;\n" + \
 351                "            method  Action jtag_do (Bit#(1) in);\n" + \
 352                "            method  Action jtag_ck (Bit#(1) in);"
 353
 354     def slowifinstance(self):
 355         return jtag_method_template # bit of a lazy hack this...
 356
 357 jtag_method_template = """\
 358     method  Action jtag_ms (Bit#(1) in);
 359       pinmux.peripheral_side.jtag_ms(in);
 360     endmethod
 361     method  Bit#(1) jtag_di=pinmux.peripheral_side.jtag_di;
 362     method  Action jtag_do (Bit#(1) in);
 363       pinmux.peripheral_side.jtag_do(in);
 364     endmethod
 365     method  Action jtag_ck (Bit#(1) in);
 366       pinmux.peripheral_side.jtag_ck(in);
 367     endmethod
 368 """
 369
 370 class sdmmc(PBase):
 371
 372     def slowimport(self):
 373         return "        import sdcard_dummy              :: *;"
 374
 375     def slowifdecl(self):
 376         return "            interface QSPI_out sd{0}_out;\n" + \
 377                "            method Bit#(1) sd{0}_isint;"
 378
 379     def num_axi_regs32(self):
 380         return 13
 381
 382     def mkslow_peripheral(self):
 383         return "        Ifc_sdcard_dummy sd{0} <-  mksdcard_dummy();"
 384
 385     def _mk_connection(self, name=None, count=0):
 386         return "sd{0}.slave"
 387
 388     def pinname_in(self, pname):
 389         return "%s_in" % pname
 390
 391     def pinname_out(self, pname):
 392         if pname.startswith('d'):
 393             return "%s_out" % pname
 394         return pname
 395
 396     def pinname_outen(self, pname):
 397         if pname.startswith('d'):
 398             return "%s_outen" % pname
 399
 400
 401 class spi(PBase):
 402
 403     def slowimport(self):
 404         return "        import qspi              :: *;"
 405
 406     def slowifdecl(self):
 407         return "            interface QSPI_out spi{0}_out;\n" + \
 408                "            method Bit#(1) spi{0}_isint;"
 409
 410     def num_axi_regs32(self):
 411         return 13
 412
 413     def mkslow_peripheral(self):
 414         return "        Ifc_qspi spi{0} <-  mkqspi();"
 415
 416     def _mk_connection(self, name=None, count=0):
 417         return "spi{0}.slave"
 418
 419     def pinname_out(self, pname):
 420         return {'clk': 'out.clk_o',
 421                 'nss': 'out.ncs_o',
 422                 'mosi': 'out.io_o[0]',
 423                 'miso': 'out.io_o[1]',
 424                 }.get(pname, '')
 425
 426     def pinname_outen(self, pname):
 427         return {'clk': 1,
 428                 'nss': 1,
 429                 'mosi': 'out.io_enable[0]',
 430                 'miso': 'out.io_enable[1]',
 431                 }.get(pname, '')
 432
 433     def mk_pincon(self, name, count):
 434         ret = [PBase.mk_pincon(self, name, count)]
 435         # special-case for gpio in, store in a temporary vector
 436         plen = len(self.peripheral.pinspecs)
 437         ret.append("    // XXX NSS and CLK are hard-coded master")
 438         ret.append("    // TODO: must add spi slave-mode")
 439         ret.append("    // all ins done in one rule from 4-bitfield")
 440         ret.append("    rule con_%s%d_io_in;" % (name, count))
 441         ret.append("       {0}{1}.out.io_i({{".format(name, count))
 442         for idx, pname in enumerate(['mosi', 'miso']):
 443             sname = self.peripheral.pname(pname).format(count)
 444             ps = "pinmux.peripheral_side.%s_in" % sname
 445             ret.append("            {0},".format(ps))
 446         ret.append("            1'b0,1'b0")
 447         ret.append("        });")
 448         ret.append("    endrule")
 449         return '\n'.join(ret)
 450
 451
 452 class qspi(PBase):
 453
 454     def slowimport(self):
 455         return "        import qspi              :: *;"
 456
 457     def slowifdecl(self):
 458         return "            interface QSPI_out qspi{0}_out;\n" + \
 459                "            method Bit#(1) qspi{0}_isint;"
 460
 461     def num_axi_regs32(self):
 462         return 13
 463
 464     def mkslow_peripheral(self, size=0):
 465         return "        Ifc_qspi qspi{0} <-  mkqspi();"
 466
 467     def _mk_connection(self, name=None, count=0):
 468         return "qspi{0}.slave"
 469
 470     def pinname_out(self, pname):
 471         return {'ck': 'out.clk_o',
 472                 'nss': 'out.ncs_o',
 473                 'io0': 'out.io_o[0]',
 474                 'io1': 'out.io_o[1]',
 475                 'io2': 'out.io_o[2]',
 476                 'io3': 'out.io_o[3]',
 477                 }.get(pname, '')
 478
 479     def pinname_outen(self, pname):
 480         return {'ck': 1,
 481                 'nss': 1,
 482                 'io0': 'out.io_enable[0]',
 483                 'io1': 'out.io_enable[1]',
 484                 'io2': 'out.io_enable[2]',
 485                 'io3': 'out.io_enable[3]',
 486                 }.get(pname, '')
 487
 488     def mk_pincon(self, name, count):
 489         ret = [PBase.mk_pincon(self, name, count)]
 490         # special-case for gpio in, store in a temporary vector
 491         plen = len(self.peripheral.pinspecs)
 492         ret.append("    // XXX NSS and CLK are hard-coded master")
 493         ret.append("    // TODO: must add qspi slave-mode")
 494         ret.append("    // all ins done in one rule from 4-bitfield")
 495         ret.append("    rule con_%s%d_io_in;" % (name, count))
 496         ret.append("       {0}{1}.out.io_i({{".format(name, count))
 497         for i, p in enumerate(self.peripheral.pinspecs):
 498             typ = p['type']
 499             pname = p['name']
 500             if not pname.startswith('io'):
 501                 continue
 502             idx = pname[1:]
 503             n = name
 504             sname = self.peripheral.pname(pname).format(count)
 505             ps = "pinmux.peripheral_side.%s_in" % sname
 506             comma = '' if i == 5 else ','
 507             ret.append("            {0}{1}".format(ps, comma))
 508         ret.append("        });")
 509         ret.append("    endrule")
 510         return '\n'.join(ret)
 511
 512
 513 class pwm(PBase):
 514
 515     def slowimport(self):
 516         return "        import pwm::*;"
 517
 518     def slowifdecl(self):
 519         return "        interface PWMIO pwm{0}_io;"
 520
 521     def num_axi_regs32(self):
 522         return 4
 523
 524     def mkslow_peripheral(self, size=0):
 525         return "        Ifc_PWM_bus pwm{0} <- mkPWM_bus(sp_clock);"
 526
 527     def _mk_connection(self, name=None, count=0):
 528         return "pwm{0}.axi4_slave"
 529
 530     def pinname_out(self, pname):
 531         return {'out': 'pwm_io.pwm_o'}.get(pname, '')
 532
 533
 534 class gpio(PBase):
 535
 536     def slowimport(self):
 537         return "     import pinmux::*;\n" + \
 538                "     import mux::*;\n" + \
 539                "     import gpio::*;\n"
 540
 541     def slowifdeclmux(self):
 542         size = len(self.peripheral.pinspecs)
 543         return "    interface GPIO_config#(%d) pad_config{0};" % size
 544
 545     def num_axi_regs32(self):
 546         return 2
 547
 548     def axi_slave_idx(self, idx, name, ifacenum):
 549         """ generates AXI slave number definition, except
 550             GPIO also has a muxer per bank
 551         """
 552         name = name.upper()
 553         mname = 'mux' + name[4:]
 554         mname = mname.upper()
 555         print "AXIslavenum", name, mname
 556         (ret, x) = PBase.axi_slave_idx(self, idx, name, ifacenum)
 557         (ret2, x) = PBase.axi_slave_idx(self, idx + 1, mname, ifacenum)
 558         return ("%s\n%s" % (ret, ret2), 2)
 559
 560     def mkslow_peripheral(self, size=0):
 561         print "gpioslow", self.peripheral, dir(self.peripheral)
 562         size = len(self.peripheral.pinspecs)
 563         return "        MUX#(%d) mux{0} <- mkmux();\n" % size + \
 564                "        GPIO#(%d) gpio{0} <- mkgpio();" % size
 565
 566     def mk_connection(self, count):
 567         print "GPIO mk_conn", self.name, count
 568         res = []
 569         dname = self.mksuffix(self.name, count)
 570         for i, n in enumerate(['gpio' + dname, 'mux' + dname]):
 571             res.append(PBase.mk_connection(self, count, n))
 572         return '\n'.join(res)
 573
 574     def _mk_connection(self, name=None, count=0):
 575         n = self.mksuffix(name, count)
 576         if name.startswith('gpio'):
 577             return "gpio{0}.axi_slave".format(n)
 578         if name.startswith('mux'):
 579             return "mux{0}.axi_slave".format(n)
 580
 581     def mksuffix(self, name, i):
 582         if name.startswith('mux'):
 583             return name[3:]
 584         return name[4:]
 585
 586     def mk_cellconn(self, cellnum, name, count):
 587         ret = []
 588         bank = self.mksuffix(name, count)
 589         txt = "       pinmux.mux_lines.cell{0}_mux(mux{1}.mux_config.mux[{2}]);"
 590         for p in self.peripheral.pinspecs:
 591             ret.append(txt.format(cellnum, bank, p['name'][1:]))
 592             cellnum += 1
 593         return ("\n".join(ret), cellnum)
 594
 595     def pinname_out(self, pname):
 596         return "func.gpio_out[{0}]".format(pname[1:])
 597
 598     def pinname_outen(self, pname):
 599         return "func.gpio_out_en[{0}]".format(pname[1:])
 600
 601     def mk_pincon(self, name, count):
 602         ret = [PBase.mk_pincon(self, name, count)]
 603         # special-case for gpio in, store in a temporary vector
 604         plen = len(self.peripheral.pinspecs)
 605         ret.append("    rule con_%s%d_in;" % (name, count))
 606         ret.append("       Vector#({0},Bit#(1)) temp;".format(plen))
 607         for p in self.peripheral.pinspecs:
 608             typ = p['type']
 609             pname = p['name']
 610             idx = pname[1:]
 611             n = name
 612             sname = self.peripheral.pname(pname).format(count)
 613             ps = "pinmux.peripheral_side.%s_in" % sname
 614             ret.append("        temp[{0}]={1};".format(idx, ps))
 615         ret.append("        {0}.func.gpio_in(temp);".format(name))
 616         ret.append("    endrule")
 617         return '\n'.join(ret)
 618
 619
 620 axi_slave_declarations = """\
 621 typedef  0  SlowMaster;
 622 {0}
 623 typedef  TAdd#(LastGen_slave_num,`ifdef CLINT       1 `else 0 `endif )
 624               CLINT_slave_num;
 625 typedef  TAdd#(CLINT_slave_num  ,`ifdef PLIC        1 `else 0 `endif )
 626               Plic_slave_num;
 627 typedef  TAdd#(Plic_slave_num   ,`ifdef AXIEXP      1 `else 0 `endif )
 628               AxiExp1_slave_num;
 629 typedef TAdd#(AxiExp1_slave_num,1) Num_Slow_Slaves;
 630 """
 631
 632 pinmux_cellrule = """\
 633     rule connect_select_lines_pinmux;
 634 {0}
 635     endrule
 636 """
 637
 638
 639 class CallFn(object):
 640     def __init__(self, peripheral, name):
 641         self.peripheral = peripheral
 642         self.name = name
 643
 644     def __call__(self, *args):
 645         #print "__call__", self.name, self.peripheral.slow, args
 646         if not self.peripheral.slow:
 647             return ''
 648         return getattr(self.peripheral.slow, self.name)(*args[1:])
 649
 650
 651 class PeripheralIface(object):
 652     def __init__(self, ifacename):
 653         self.slow = None
 654         slow = slowfactory.getcls(ifacename)
 655         print "Iface", ifacename, slow
 656         if slow:
 657             self.slow = slow(ifacename)
 658             self.slow.peripheral = self
 659         for fname in ['slowimport',
 660                       'slowifinstance', 'slowifdecl', 'slowifdeclmux',
 661                       'mkslow_peripheral',
 662                       'mk_connection', 'mk_cellconn', 'mk_pincon']:
 663             fn = CallFn(self, fname)
 664             setattr(self, fname, types.MethodType(fn, self))
 665
 666         #print "PeripheralIface"
 667         #print dir(self)
 668
 669     def mksuffix(self, name, i):
 670         if self.slow is None:
 671             return i
 672         return self.slow.mksuffix(name, i)
 673
 674     def axi_reg_def(self, start, count):
 675         if not self.slow:
 676             return ('', 0)
 677         return self.slow.axi_reg_def(start, self.ifacename, count)
 678
 679     def axi_slave_idx(self, start, count):
 680         if not self.slow:
 681             return ('', 0)
 682         return self.slow.axi_slave_idx(start, self.ifacename, count)
 683
 684     def axi_addr_map(self, count):
 685         if not self.slow:
 686             return ''
 687         return self.slow.axi_addr_map(self.ifacename, count)
 688
 689
 690 class PeripheralInterfaces(object):
 691     def __init__(self):
 692         pass
 693
 694     def slowimport(self, *args):
 695         ret = []
 696         for (name, count) in self.ifacecount:
 697             #print "slowimport", name, self.data[name].slowimport
 698             ret.append(self.data[name].slowimport())
 699         return '\n'.join(list(filter(None, ret)))
 700
 701     def slowifinstance(self, *args):
 702         ret = []
 703         for (name, count) in self.ifacecount:
 704             #print "slowimport", name, self.data[name].slowimport
 705             ret.append(self.data[name].slowifinstance())
 706         return '\n'.join(list(filter(None, ret)))
 707
 708     def slowifdeclmux(self, *args):
 709         ret = []
 710         for (name, count) in self.ifacecount:
 711             for i in range(count):
 712                 ret.append(self.data[name].slowifdeclmux().format(i, name))
 713         return '\n'.join(list(filter(None, ret)))
 714
 715     def slowifdecl(self, *args):
 716         ret = []
 717         for (name, count) in self.ifacecount:
 718             for i in range(count):
 719                 ret.append(self.data[name].slowifdecl().format(i, name))
 720         return '\n'.join(list(filter(None, ret)))
 721
 722     def axi_reg_def(self, *args):
 723         ret = []
 724         start = 0x00011100  # start of AXI peripherals address
 725         for (name, count) in self.ifacecount:
 726             for i in range(count):
 727                 x = self.data[name].axi_reg_def(start, i)
 728                 #print ("ifc", name, x)
 729                 (rdef, offs) = x
 730                 ret.append(rdef)
 731                 start += offs
 732         return '\n'.join(list(filter(None, ret)))
 733
 734     def axi_slave_idx(self, *args):
 735         ret = []
 736         start = 0
 737         for (name, count) in self.ifacecount:
 738             for i in range(count):
 739                 (rdef, offs) = self.data[name].axi_slave_idx(start, i)
 740                 #print ("ifc", name, rdef, offs)
 741                 ret.append(rdef)
 742                 start += offs
 743         ret.append("typedef %d LastGen_slave_num;" % (start - 1))
 744         decls = '\n'.join(list(filter(None, ret)))
 745         return axi_slave_declarations.format(decls)
 746
 747     def axi_addr_map(self, *args):
 748         ret = []
 749         for (name, count) in self.ifacecount:
 750             for i in range(count):
 751                 ret.append(self.data[name].axi_addr_map(i))
 752         return '\n'.join(list(filter(None, ret)))
 753
 754     def mkslow_peripheral(self, *args):
 755         ret = []
 756         for (name, count) in self.ifacecount:
 757             for i in range(count):
 758                 print "mkslow", name, count
 759                 x = self.data[name].mkslow_peripheral()
 760                 print name, count, x
 761                 suffix = self.data[name].mksuffix(name, i)
 762                 ret.append(x.format(suffix))
 763         return '\n'.join(list(filter(None, ret)))
 764
 765     def mk_connection(self, *args):
 766         ret = []
 767         for (name, count) in self.ifacecount:
 768             for i in range(count):
 769                 print "mk_conn", name, i
 770                 txt = self.data[name].mk_connection(i)
 771                 if name == 'gpioa':
 772                     print "txt", txt
 773                     print self.data[name].mk_connection
 774                 ret.append(txt)
 775         return '\n'.join(list(filter(None, ret)))
 776
 777     def mk_cellconn(self):
 778         ret = []
 779         cellcount = 0
 780         for (name, count) in self.ifacecount:
 781             for i in range(count):
 782                 res = self.data[name].mk_cellconn(cellcount, name, i)
 783                 if not res:
 784                     continue
 785                 (txt, cellcount) = res
 786                 ret.append(txt)
 787         ret = '\n'.join(list(filter(None, ret)))
 788         return pinmux_cellrule.format(ret)
 789
 790     def mk_pincon(self):
 791         ret = []
 792         for (name, count) in self.ifacecount:
 793             for i in range(count):
 794                 txt = self.data[name].mk_pincon(name, i)
 795                 ret.append(txt)
 796         return '\n'.join(list(filter(None, ret)))
 797
 798
 799 class PFactory(object):
 800     def getcls(self, name):
 801         for k, v in {'uart': uart,
 802                      'rs232': rs232,
 803                      'twi': twi,
 804                      'qspi': qspi,
 805                      'spi': spi,
 806                      'pwm': pwm,
 807                      'eint': eint,
 808                      'sd': sdmmc,
 809                      'jtag': jtag,
 810                      'gpio': gpio
 811                      }.items():
 812             if name.startswith(k):
 813                 return v
 814         return None
 815
 816
 817 slowfactory = PFactory()
 818
 819 if __name__ == '__main__':
 820     p = uart('uart')
 821     print p.slowimport()
 822     print p.slowifdecl()
 823     i = PeripheralIface('uart')
 824     print i, i.slow
 825     i = PeripheralIface('gpioa')
 826     print i, i.slow