src/bsv/peripheral_gen/base.py

   1 import types
   2
   3 def li(txt, indent):
   4     indent = ' ' * indent
   5     istxt = False
   6     if isinstance(txt, str):
   7         istxt = True
   8         txt = txt.split('\n')
   9     res = []
  10     for line in txt:
  11         line = line.split('\n')
  12         res += line
  13     txt = res
  14     res = []
  15     for line in txt:
  16         res.append(indent + line)
  17     if istxt:
  18         res = '\n'.join(res)
  19     return res
  20
  21
  22 class PBase(object):
  23     def __init__(self, name):
  24         self.name = name
  25
  26     def extifdecl(self, name, count):
  27         sname = self.get_iname(count)
  28         return "interface PeripheralSide%s %s;" % (name.upper(), sname)
  29
  30     def has_axi_master(self):
  31         return False
  32
  33     def irq_name(self):
  34         return ""
  35
  36     def mk_dma_irq(self, name, count):
  37         if not self.irq_name():
  38             return ''
  39         sname = self.get_iname(count)
  40         return "{0}_interrupt".format(sname)
  41
  42     def mk_dma_rule(self, name, count):
  43         irqname = self.mk_dma_irq(name, count)
  44         if not irqname:
  45             return ''
  46         pirqname = self.irq_name().format(count)
  47         template = "   {0}_interrupt.send(\n" + \
  48                    "           slow_peripherals.{1});"
  49         return template.format(irqname, pirqname)
  50
  51     def get_clock_reset(self, name, count):
  52         return "slow_clock,slow_reset"
  53
  54     def mk_dma_sync(self, name, count):
  55         irqname = self.mk_dma_irq(name, count)
  56         if not irqname:
  57             return ''
  58         sname = self.peripheral.iname().format(count)
  59         template = "SyncBitIfc#(Bit#(1)) {0} <-\n" + \
  60                    "           <-mkSyncBitToCC({1});"
  61         return template.format(irqname, self.get_clock_reset(name, count))
  62
  63     def mk_dma_connect(self, name, count):
  64         irqname = self.mk_dma_irq(name, count)
  65         if not irqname:
  66             return ''
  67         return "{0}.read".format(irqname)
  68
  69     def fastifdecl(self, name, count):
  70         return ''
  71
  72     def slowifdeclmux(self, name, count):
  73         return ''
  74
  75     def slowimport(self):
  76         return ''
  77
  78     def num_axi_regs32(self):
  79         return 0
  80
  81     def slowifdecl(self):
  82         return ''
  83
  84     def get_iname(self, inum):
  85         return "{0}{1}".format(self.name, self.mksuffix(self.name, inum))
  86
  87     def axibase(self, name, ifacenum):
  88         name = name.upper()
  89         return "%(name)s%(ifacenum)dBase" % locals()
  90
  91     def axiend(self, name, ifacenum):
  92         name = name.upper()
  93         return "%(name)s%(ifacenum)dEnd" % locals()
  94
  95     def axi_reg_def(self, start, name, ifacenum):
  96         name = name.upper()
  97         offs = self.num_axi_regs32() * 4 * 16
  98         if offs == 0:
  99             return ('', 0)
 100         end = start + offs - 1
 101         bname = self.axibase(name, ifacenum)
 102         bend = self.axiend(name, ifacenum)
 103         comment = "%d 32-bit regs" % self.num_axi_regs32()
 104         return ("    `define %(bname)s 'h%(start)08X\n"
 105                 "    `define %(bend)s  'h%(end)08X // %(comment)s" % locals(),
 106                 offs)
 107
 108     def axi_master_name(self, name, ifacenum, typ=''):
 109         name = name.upper()
 110         return "{0}{1}_master_num".format(name, ifacenum)
 111
 112     def axi_slave_name(self, name, ifacenum, typ=''):
 113         name = name.upper()
 114         return "{0}{1}_{2}slave_num".format(name, ifacenum, typ)
 115
 116     def axi_master_idx(self, idx, name, ifacenum, typ):
 117         name = self.axi_master_name(name, ifacenum, typ)
 118         return ("typedef {0} {1};".format(idx, name), 1)
 119
 120     def axi_slave_idx(self, idx, name, ifacenum, typ):
 121         name = self.axi_slave_name(name, ifacenum, typ)
 122         return ("typedef {0} {1};".format(idx, name), 1)
 123
 124     def axi_addr_map(self, name, ifacenum):
 125         bname = self.axibase(name, ifacenum)
 126         bend = self.axiend(name, ifacenum)
 127         name = self.axi_slave_name(name, ifacenum)
 128         template = """\
 129 if(addr>=`{0} && addr<=`{1})
 130     return tuple2(True,fromInteger(valueOf({2})));
 131 else"""
 132         return template.format(bname, bend, name)
 133
 134     def mk_pincon(self, name, count):
 135         # TODO: really should be using bsv.interface_decl.Interfaces
 136         # pin-naming rules.... logic here is hard-coded to duplicate
 137         # it (see Interface.__init__ outen)
 138         ret = []
 139         for p in self.peripheral.pinspecs:
 140             typ = p['type']
 141             pname = p['name']
 142             #n = "{0}{1}".format(self.name, self.mksuffix(name, count))
 143             n = name  # "{0}{1}".format(self.name, self.mksuffix(name, count))
 144             ret.append("//%s %s" % (n, str(p)))
 145             sname = self.peripheral.iname().format(count)
 146             sname = "{0}.{1}".format(sname, pname)
 147             ps = "pinmux.peripheral_side.%s" % sname
 148             if typ == 'out' or typ == 'inout':
 149                 fname = self.pinname_out(pname)
 150                 if not n.startswith('gpio'):  # XXX EURGH! horrible hack
 151                     n_ = "{0}{1}".format(n, count)
 152                 else:
 153                     n_ = n
 154                 if fname:
 155                     if p.get('outen'):
 156                         ps_ = ps + '_out'
 157                     else:
 158                         ps_ = ps
 159                     ret.append("mkConnection({0},\n\t\t\t{1}.{2});"
 160                                .format(ps_, n_, fname))
 161                 fname = None
 162                 if p.get('outen'):
 163                     fname = self.pinname_outen(pname)
 164                 if fname:
 165                     if isinstance(fname, str):
 166                         fname = "{0}.{1}".format(n_, fname)
 167                     fname = self.pinname_tweak(pname, 'outen', fname)
 168                     ret.append("mkConnection({0}_outen,\n\t\t\t{1});"
 169                                .format(ps, fname))
 170             if typ == 'in' or typ == 'inout':
 171                 fname = self.pinname_in(pname)
 172                 if fname:
 173                     if p.get('outen'):
 174                         ps_ = ps + '_in'
 175                     else:
 176                         ps_ = ps
 177                     n_ = "{0}{1}".format(n, count)
 178                     n_ = '{0}.{1}'.format(n_, fname)
 179                     n_ = self.ifname_tweak(pname, 'in', n_)
 180                     ret.append("mkConnection({1}, {0});".format(ps_, n_))
 181         return '\n'.join(ret)
 182
 183     def mk_cellconn(self, *args):
 184         return ''
 185
 186     def mkfast_peripheral(self, size=0):
 187         return ''
 188
 189     def mkslow_peripheral(self, size=0):
 190         return ''
 191
 192     def mksuffix(self, name, i):
 193         return i
 194
 195     def __mk_connection(self, con, aname, fabricname):
 196         txt = "mkConnection ({2}.v_to_slaves\n" + \
 197               "            [fromInteger(valueOf({1}))],\n" + \
 198               "            {0});"
 199
 200         print "PBase __mk_connection", self.name, aname
 201         if not con:
 202             return ''
 203         return txt.format(con, aname, fabricname)
 204
 205     def __mk_master_connection(self, con, aname):
 206         txt = "mkConnection (slow_fabric.v_to_slaves\n" + \
 207               "            [fromInteger(valueOf({1}))],\n" + \
 208               "            {0});"
 209
 210         print "PBase __mk_connection", self.name, aname
 211         if not con:
 212             return ''
 213         return txt.format(con, aname)
 214
 215     def mk_connection(self, count, fabricname, typ, name=None):
 216         if name is None:
 217             name = self.name
 218         print "PBase mk_conn", self.name, count
 219         aname = self.axi_slave_name(name, count, typ)
 220         #dname = self.mksuffix(name, count)
 221         #dname = "{0}{1}".format(name, dname)
 222         con = self._mk_connection(name, count).format(count, aname)
 223         return self.__mk_connection(con, aname, fabricname)
 224
 225     def _mk_connection(self, name=None, count=0):
 226         return ''
 227
 228     def pinname_out(self, pname):
 229         return ''
 230
 231     def pinname_in(self, pname):
 232         return ''
 233
 234     def pinname_outen(self, pname):
 235         return ''
 236
 237     def ifname_tweak(self, pname, typ, txt):
 238         return txt
 239
 240     def pinname_tweak(self, pname, typ, txt):
 241         return txt
 242
 243     def num_irqs(self):
 244         return 0
 245
 246     def mk_plic(self, inum, irq_offs):
 247         res = []
 248         print "mk_plic", self.name, inum, irq_offs
 249         niq = self.num_irqs()
 250         if niq == 0:
 251             return ('', irq_offs)
 252         name = self.get_iname(inum)
 253         res.append("// PLIC rules for {0}".format(name))
 254         for idx in range(niq):
 255             plic_obj = self.plic_object(name, idx)
 256             print "plic_obj", name, idx, plic_obj
 257             plic = mkplic_rule.format(name, plic_obj, irq_offs)
 258             res.append(plic)
 259             irq_offs += 1  # increment to next irq
 260         return ('\n'.join(res), irq_offs)
 261
 262     def mk_ext_ifacedef(self, iname, inum):
 263         return ''
 264
 265     def extfastifinstance(self, name, count):
 266         return ''
 267
 268     def _extifinstance(self, name, count, suffix, prefix, samename=False):
 269         pname = self.get_iname(count)
 270         if samename:
 271             sname = pname
 272         else:
 273             sname = self.peripheral.iname().format(count)
 274         template = "interface {0}{3} = {2}{1};"
 275         return template.format(pname, sname, prefix, suffix)
 276
 277     def extifinstance2(self, name, count):
 278         return ''
 279
 280     def extifinstance(self, name, count):
 281         return self._extifinstance(name, count, "",
 282                                             "pinmux.peripheral_side.")
 283
 284
 285 mkplic_rule = """\
 286 rule rl_connect_{0}_to_plic_{2};
 287    if({1} == 1'b1) begin
 288        ff_gateway_queue[{2}].enq(1);
 289        plic.ifc_external_irq[{2}].irq_frm_gateway(True);
 290    end
 291 endrule
 292 """
 293
 294 axi_master_declarations= """\
 295 typedef 0 Dmem_master_num;
 296 typedef 1 Imem_master_num;
 297 {0}
 298 typedef TAdd#(LastGen_master_num, `ifdef Debug 1 `else 0 `endif )
 299                 Debug_master_num;
 300 typedef TAdd#(Debug_master_num, `ifdef DMA 1 `else 0 `endif )
 301                 DMA_master_num;
 302 typedef TAdd#(DMA_master_num,1)
 303                 Num_Masters;
 304 """
 305
 306 axi_fastslave_declarations = """\
 307 {0}
 308 typedef  TAdd#(LastGen_fastslave_num,1)      Sdram_cfg_slave_num;
 309 typedef  TAdd#(Sdram_slave_num   ,`ifdef SDRAM      1 `else 0 `endif )
 310                       Sdram_cfg_slave_num;
 311 typedef TAdd#(Sdram_cfg_slave_num,`ifdef BOOTROM    1 `else 0 `endif )
 312                 BootRom_slave_num   ;
 313 typedef TAdd#(BootRom_slave_num  ,`ifdef Debug      1 `else 0 `endif )
 314                 Debug_slave_num ;
 315 typedef  TAdd#(Debug_slave_num   , `ifdef TCMemory  1 `else 0 `endif )
 316                 TCM_slave_num;
 317 typedef  TAdd#(TCM_slave_num     ,`ifdef DMA            1 `else 0 `endif )
 318                 Dma_slave_num;
 319 typedef  TAdd#(Dma_slave_num      ,1 )      SlowPeripheral_slave_num;
 320 typedef  TAdd#(SlowPeripheral_slave_num,`ifdef VME  1 `else 0 `endif )
 321                 VME_slave_num;
 322 typedef  TAdd#(VME_slave_num,`ifdef FlexBus 1 `else 0 `endif )
 323                 FlexBus_slave_num;
 324 typedef TAdd#(FlexBus_slave_num,1)
 325                 Num_Slaves;
 326
 327 """
 328
 329 axi_slave_declarations = """\
 330 typedef  0  SlowMaster;
 331 {0}
 332 typedef  TAdd#(LastGen_slave_num,`ifdef CLINT       1 `else 0 `endif )
 333               CLINT_slave_num;
 334 typedef  TAdd#(CLINT_slave_num  ,`ifdef PLIC        1 `else 0 `endif )
 335               Plic_slave_num;
 336 typedef  TAdd#(Plic_slave_num   ,`ifdef AXIEXP      1 `else 0 `endif )
 337               AxiExp1_slave_num;
 338 typedef TAdd#(AxiExp1_slave_num,1) Num_Slow_Slaves;
 339 """
 340
 341 pinmux_cellrule = """\
 342 rule connect_select_lines_pinmux;
 343 {0}
 344 endrule
 345 """
 346
 347
 348 class CallFn(object):
 349     def __init__(self, peripheral, name):
 350         self.peripheral = peripheral
 351         self.name = name
 352
 353     def __call__(self, *args):
 354         #print "__call__", self.name, self.peripheral.slow, args
 355         if not self.peripheral.slow:
 356             return ''
 357         return getattr(self.peripheral.slow, self.name)(*args[1:])
 358
 359
 360 class PeripheralIface(object):
 361     def __init__(self, ifacename):
 362         self.slow = None
 363         slow = slowfactory.getcls(ifacename)
 364         print "Iface", ifacename, slow
 365         if slow:
 366             self.slow = slow(ifacename)
 367             self.slow.peripheral = self
 368         for fname in ['slowimport',
 369                       'extfastifinstance',
 370                       'extifinstance2', 'extifinstance', 'extifdecl',
 371                       'slowifdecl', 'slowifdeclmux',
 372                       'fastifdecl',
 373                       'mkslow_peripheral',
 374                       'mk_dma_sync', 'mk_dma_connect', 'mk_dma_rule',
 375                       'mkfast_peripheral',
 376                       'mk_plic', 'mk_ext_ifacedef',
 377                       'mk_connection', 'mk_cellconn', 'mk_pincon']:
 378             fn = CallFn(self, fname)
 379             setattr(self, fname, types.MethodType(fn, self))
 380
 381         #print "PeripheralIface"
 382         #print dir(self)
 383
 384     def mksuffix(self, name, i):
 385         if self.slow is None:
 386             return i
 387         return self.slow.mksuffix(name, i)
 388
 389     def axi_reg_def(self, start, count):
 390         if not self.slow:
 391             return ('', 0)
 392         return self.slow.axi_reg_def(start, self.ifacename, count)
 393
 394     def axi_master_idx(self, start, count, typ):
 395         if not self.slow or not self.slow.has_axi_master():
 396             return ('', 0)
 397         return self.slow.axi_master_idx(start, self.ifacename, count, typ)
 398
 399     def axi_slave_idx(self, start, count, typ):
 400         if not self.slow:
 401             return ('', 0)
 402         return self.slow.axi_slave_idx(start, self.ifacename, count, typ)
 403
 404     def axi_addr_map(self, count):
 405         if not self.slow:
 406             return ''
 407         return self.slow.axi_addr_map(self.ifacename, count)
 408
 409
 410 class PeripheralInterfaces(object):
 411     def __init__(self):
 412         self.fastbusmode = False
 413
 414     def slowimport(self, *args):
 415         ret = []
 416         for (name, count) in self.ifacecount:
 417             #print "slowimport", name, self.data[name].slowimport
 418             ret.append(self.data[name].slowimport())
 419         return '\n'.join(li(list(filter(None, ret)), 4))
 420
 421     def extfastifinstance(self, *args):
 422         ret = []
 423         for (name, count) in self.ifacecount:
 424             for i in range(count):
 425                 iname = self.data[name].iname().format(i)
 426                 print "extfast", iname, self.is_on_fastbus(name, i)
 427                 if self.is_on_fastbus(name, i):
 428                     continue
 429                 ret.append(self.data[name].extfastifinstance(name, i))
 430         return '\n'.join(li(list(filter(None, ret)), 8))
 431
 432     def extifinstance2(self, *args):
 433         ret = []
 434         for (name, count) in self.ifacecount:
 435             for i in range(count):
 436                 iname = self.data[name].iname().format(i)
 437                 ret.append(self.data[name].extifinstance2(name, i))
 438         return '\n'.join(li(list(filter(None, ret)), 8))
 439
 440     def extifinstance(self, *args):
 441         ret = []
 442         for (name, count) in self.ifacecount:
 443             for i in range(count):
 444                 iname = self.data[name].iname().format(i)
 445                 if not self.is_on_fastbus(name, i):
 446                     continue
 447                 ret.append(self.data[name].extifinstance(name, i))
 448         return '\n'.join(li(list(filter(None, ret)), 8))
 449
 450     def extifdecl(self, *args):
 451         ret = []
 452         for (name, count) in self.ifacecount:
 453             for i in range(count):
 454                 if not self.is_on_fastbus(name, i):
 455                     continue
 456                 ret.append(self.data[name].extifdecl(name, i))
 457         return '\n'.join(li(list(filter(None, ret)), 8))
 458
 459     def slowifdeclmux(self, *args):
 460         ret = []
 461         for (name, count) in self.ifacecount:
 462             for i in range(count):
 463                 ret.append(self.data[name].slowifdeclmux(name, i))
 464         return '\n'.join(li(list(filter(None, ret)), 8))
 465
 466     def fastifdecl(self, *args):
 467         ret = []
 468         for (name, count) in self.ifacecount:
 469             for i in range(count):
 470                 print "fastifdecl", name, i, self.is_on_fastbus(name, i)
 471                 if self.is_on_fastbus(name, i):
 472                     continue
 473                 ret.append(self.data[name].fastifdecl(name, i))
 474         return '\n'.join(li(list(filter(None, ret)), 4))
 475
 476     def slowifdecl(self, *args):
 477         ret = []
 478         for (name, count) in self.ifacecount:
 479             for i in range(count):
 480                 if self.is_on_fastbus(name, i):
 481                     continue
 482                 ret.append(self.data[name].slowifdecl().format(i, name))
 483         return '\n'.join(list(filter(None, ret)))
 484
 485     def axi_reg_def(self, *args):
 486         ret = []
 487         start = 0x00011100  # start of AXI peripherals address
 488         for (name, count) in self.ifacecount:
 489             for i in range(count):
 490                 if self.is_on_fastbus(name, i):
 491                     continue
 492                 x = self.data[name].axi_reg_def(start, i)
 493                 #print ("ifc", name, x)
 494                 (rdef, offs) = x
 495                 ret.append(rdef)
 496                 start += offs
 497         return '\n'.join(list(filter(None, ret)))
 498
 499     def _axi_num_idx(self, start, template, typ, idxtype, *args):
 500         ret = []
 501         for (name, count) in self.ifacecount:
 502             for i in range(count):
 503                 if self.is_on_fastbus(name, i):
 504                     continue
 505                 if typ == 'master':
 506                     fn = self.data[name].axi_master_idx
 507                 else:
 508                     fn = self.data[name].axi_slave_idx
 509                 (rdef, offs) = fn(start, i, idxtype)
 510                 #print ("ifc", name, rdef, offs)
 511                 ret.append(rdef)
 512                 start += offs
 513         ret.append("typedef %d LastGen_%s_num;" % (start - 1, typ))
 514         decls = '\n'.join(list(filter(None, ret)))
 515         return template.format(decls)
 516
 517     def axi_slave_idx(self, *args):
 518         return self._axi_num_idx(0, axi_slave_declarations, 'slave',
 519                                  '', *args)
 520
 521     def axi_fastslave_idx(self, *args):
 522         return self._axi_num_idx(0, axi_fastslave_declarations, 'fastslave',
 523                                  'fast', *args)
 524
 525     def axi_master_idx(self, *args):
 526         return self._axi_num_idx(2, axi_master_declarations, 'master',
 527                                  'master', *args)
 528
 529     def axi_fastslave_idx(self, *args):
 530         return self._axi_num_idx(0, axi_fastslave_declarations, 'fastslave',
 531                                  'fast', *args)
 532
 533     def axi_addr_map(self, *args):
 534         ret = []
 535         for (name, count) in self.ifacecount:
 536             for i in range(count):
 537                 if self.is_on_fastbus(name, i):
 538                     continue
 539                 ret.append(self.data[name].axi_addr_map(i))
 540         return '\n'.join(li(list(filter(None, ret)), 8))
 541
 542     def mkfast_peripheral(self, *args):
 543         ret = []
 544         for (name, count) in self.ifacecount:
 545             for i in range(count):
 546                 if self.is_on_fastbus(name, i):
 547                     continue
 548                 #print "mkfast", name, count
 549                 x = self.data[name].mkfast_peripheral()
 550                 print name, count, x
 551                 suffix = self.data[name].mksuffix(name, i)
 552                 ret.append(x.format(suffix))
 553         return '\n'.join(li(list(filter(None, ret)), 8))
 554
 555     def mkslow_peripheral(self, *args):
 556         ret = []
 557         for (name, count) in self.ifacecount:
 558             for i in range(count):
 559                 if self.is_on_fastbus(name, i):
 560                     continue
 561                 #print "mkslow", name, count
 562                 x = self.data[name].mkslow_peripheral()
 563                 print name, count, x
 564                 suffix = self.data[name].mksuffix(name, i)
 565                 ret.append(x.format(suffix))
 566         return '\n'.join(li(list(filter(None, ret)), 8))
 567
 568     def mk_fast_connection(self, *args):
 569         ret = []
 570         for (name, count) in self.ifacecount:
 571             for i in range(count):
 572                 if self.is_on_fastbus(name, i):
 573                     continue
 574                 txt = self.data[name].mk_connection(i, "fabric", "fast")
 575                 if name == 'gpioa':
 576                     print "txt", txt
 577                     print self.data[name].mk_connection
 578                 ret.append(txt)
 579         return '\n'.join(li(list(filter(None, ret)), 4))
 580
 581     def mk_connection(self, *args):
 582         ret = []
 583         for (name, count) in self.ifacecount:
 584             for i in range(count):
 585                 if self.is_on_fastbus(name, i):
 586                     continue
 587                 txt = self.data[name].mk_connection(i, "slow_fabric", "")
 588                 if name == 'gpioa':
 589                     print "txt", txt
 590                     print self.data[name].mk_connection
 591                 ret.append(txt)
 592         return '\n'.join(li(list(filter(None, ret)), 8))
 593
 594     def mk_cellconn(self):
 595         ret = []
 596         cellcount = 0
 597         for (name, count) in self.ifacecount:
 598             for i in range(count):
 599                 if self.is_on_fastbus(name, i):
 600                     continue
 601                 res = self.data[name].mk_cellconn(cellcount, name, i)
 602                 if not res:
 603                     continue
 604                 (txt, cellcount) = res
 605                 ret.append(txt)
 606         ret = li('\n'.join(list(filter(None, ret))), 4)
 607         return li(pinmux_cellrule.format(ret), 4)
 608
 609     def mk_pincon(self):
 610         ret = []
 611         for (name, count) in self.ifacecount:
 612             for i in range(count):
 613                 if self.is_on_fastbus(name, i):
 614                     continue
 615                 txt = self.data[name].mk_pincon(name, i)
 616                 ret.append(txt)
 617         return '\n'.join(li(list(filter(None, ret)), 4))
 618
 619     def mk_dma_irq(self):
 620         ret = []
 621         sync = []
 622         rules = []
 623         cnct = []
 624
 625         self.dma_count = 0
 626
 627         for (name, count) in self.ifacecount:
 628             ifacerules = []
 629             for i in range(count):
 630                 if not self.is_on_fastbus(name, i):
 631                     continue
 632                 txt = self.data[name].mk_dma_sync(name, i)
 633                 if txt:
 634                     self.dma_count += 1
 635                 sync.append(txt)
 636                 txt = self.data[name].mk_dma_rule(name, i)
 637                 ifacerules.append(txt)
 638                 txt = self.data[name].mk_dma_connect(name, i)
 639                 cnct.append(txt)
 640             ifacerules = list(filter(None, ifacerules))
 641             if ifacerules:
 642                 txt = "rule synchronize_%s_interrupts;" % name
 643                 rules.append(txt)
 644                 rules += ifacerules
 645                 rules.append("endrule")
 646
 647         cnct = list(filter(None, cnct))
 648         ct = self.dma_count
 649         _cnct    = ["rule rl_connect_interrupt_to_DMA;",
 650                     "  Bit #(%d) lv_interrupt_to_DMA={" % ct]
 651         spc = "                      "
 652         spcsep = ",\n" + spc
 653         cnct = _cnct + [spc + spcsep.join(cnct)]
 654         cnct.append("   };")
 655         cnct.append("   dma.interrupt_from_peripherals(\n" + \
 656                     "       lv_interrupt_to_DMA);")
 657         cnct.append("endrule;")
 658
 659         ret = list(filter(None, sync + rules + cnct))
 660         ret = li(ret, 15)
 661         return '\n'.join(ret)
 662
 663     def num_dmachannels(self):
 664         return "`define NUM_DMACHANNELS {0}".format(self.dma_count)
 665
 666     def mk_ext_ifacedef(self):
 667         ret = []
 668         for (name, count) in self.ifacecount:
 669             for i in range(count):
 670                 if self.is_on_fastbus(name, i):
 671                     continue
 672                 txt = self.data[name].mk_ext_ifacedef(name, i)
 673                 ret.append(txt)
 674         return '\n'.join(li(list(filter(None, ret)), 8))
 675
 676     def mk_plic(self):
 677         ret = []
 678         irq_offs = 8  # XXX: DMA scovers 0-7?
 679         for (name, count) in self.ifacecount:
 680             for i in range(count):
 681                 if self.is_on_fastbus(name, i):
 682                     continue
 683                 res = self.data[name].mk_plic(i, irq_offs)
 684                 if not res:
 685                     continue
 686                 (txt, irq_offs) = res
 687                 ret.append(txt)
 688         self.num_slow_irqs = irq_offs
 689         return '\n'.join(li(list(filter(None, ret)), 4))
 690
 691     def mk_sloirqsdef(self):
 692         return "    `define NUM_SLOW_IRQS {0}".format(self.num_slow_irqs)
 693
 694     def is_on_fastbus(self, name, i):
 695         #print "fastbus mode", self.fastbusmode, name, i
 696         iname = self.data[name].iname().format(i)
 697         if self.fastbusmode:
 698             return iname not in self.fastbus
 699         return iname in self.fastbus
 700
 701
 702 class PFactory(object):
 703     def getcls(self, name):
 704         from uart import uart
 705         from quart import quart
 706         from sdmmc import sdmmc
 707         from pwm import pwm
 708         from eint import eint
 709         from rs232 import rs232
 710         from twi import twi
 711         from eint import eint
 712         from jtag import jtag
 713         from spi import spi, mspi
 714         from qspi import qspi, mqspi
 715         from gpio import gpio
 716         from rgbttl import rgbttl
 717
 718         for k, v in {'uart': uart,
 719                      'rs232': rs232,
 720                      'twi': twi,
 721                      'quart': quart,
 722                      'mqspi': mqspi,
 723                      'mspi': mspi,
 724                      'qspi': qspi,
 725                      'spi': spi,
 726                      'pwm': pwm,
 727                      'eint': eint,
 728                      'sd': sdmmc,
 729                      'jtag': jtag,
 730                      'lcd': rgbttl,
 731                      'gpio': gpio
 732                      }.items():
 733             if name.startswith(k):
 734                 return v
 735         return None
 736
 737
 738 slowfactory = PFactory()
 739
 740 if __name__ == '__main__':
 741     p = uart('uart')
 742     print p.slowimport()
 743     print p.slowifdecl()
 744     i = PeripheralIface('uart')
 745     print i, i.slow
 746     i = PeripheralIface('gpioa')
 747     print i, i.slow