7 if isinstance(txt
, str):
12 line
= line
.split('\n')
17 res
.append(indent
+ line
)
24 def __init__(self
, name
):
27 def extifdecl(self
, name
, count
):
28 sname
= self
.get_iname(count
)
29 return "interface PeripheralSide%s %s;" % (name
.upper(), sname
)
31 def has_axi_master(self
):
37 def mk_dma_irq(self
, name
, count
):
38 if not self
.irq_name():
40 sname
= self
.get_iname(count
)
41 return "{0}_interrupt".format(sname
)
43 def mk_dma_rule(self
, name
, count
):
44 irqname
= self
.mk_dma_irq(name
, count
)
47 pirqname
= self
.irq_name().format(count
)
48 template
= " {0}.send(\n" + \
49 " slow_peripherals.{1});"
50 return template
.format(irqname
, pirqname
)
52 def get_clock_reset(self
, name
, count
):
53 return "slow_clock,slow_reset"
55 def mk_dma_sync(self
, name
, count
):
56 irqname
= self
.mk_dma_irq(name
, count
)
59 sname
= self
.peripheral
.iname().format(count
)
60 template
= "SyncBitIfc#(Bit#(1)) {0} <-\n" + \
61 " <-mkSyncBitToCC({1});"
62 return template
.format(irqname
, self
.get_clock_reset(name
, count
))
64 def mk_dma_connect(self
, name
, count
):
65 irqname
= self
.mk_dma_irq(name
, count
)
68 return "{0}.read".format(irqname
)
70 def fastifdecl(self
, name
, count
):
73 def slowifdeclmux(self
, name
, count
):
79 def get_mmap_configs(self
):
81 for cfg
in self
.peripheral
.configs
:
82 res
.append(cfg
.get('mmap', None))
83 return res
[0] # XXX HACK! assume all configs same for each peripheral!
85 def get_mmap_cfg_name(self
, idx
):
86 cfg
= self
.get_mmap_configs()
88 nregs
= self
.num_axi_regs32()
89 if isinstance(nregs
, int) or len(nregs
) == 1:
94 def num_axi_regs32cfg(self
):
95 cfg
= self
.get_mmap_configs()
97 return self
.num_axi_regs32()
103 def num_axi_regs32(self
):
106 def slowifdecl(self
):
109 def get_iname(self
, inum
):
110 return "{0}{1}".format(self
.name
, self
.mksuffix(self
.name
, inum
))
112 def axibase(self
, name
, ifacenum
, idx
):
114 return "%(name)s%(ifacenum)d%(idx)sBase" % locals()
116 def axiend(self
, name
, ifacenum
, idx
):
118 return "%(name)s%(ifacenum)d%(idx)sEnd" % locals()
120 def _axi_reg_def(self
, idx
, numregs
, start
, name
, ifacenum
):
122 offs
= numregs
* 4 * 16
125 end
= start
+ offs
- 1
126 bname
= self
.axibase(name
, ifacenum
, idx
)
127 bend
= self
.axiend(name
, ifacenum
, idx
)
128 comment
= "%d 32-bit regs" % numregs
129 return (" `define %(bname)s 'h%(start)08X\n"
130 " `define %(bend)s 'h%(end)08X // %(comment)s" % locals(),
133 def axi_reg_def(self
, start
, name
, ifacenum
):
134 offs
= self
.num_axi_regs32cfg()
137 if not isinstance(offs
, list):
142 for (idx
, nregs
) in enumerate(offs
):
143 cfg
= self
.get_mmap_cfg_name(idx
)
144 (txt
, off
) = self
._axi
_reg
_def
(cfg
, nregs
, start
, name
, ifacenum
)
148 return ('\n'.join(res
), offstotal
)
150 def axi_master_name(self
, name
, ifacenum
, typ
=''):
152 return "{0}{1}_master_num".format(name
, ifacenum
)
154 def axi_slave_name(self
, idx
, name
, ifacenum
, typ
=''):
156 return "{0}{1}{3}_{2}slave_num".format(name
, ifacenum
, typ
, idx
)
158 def axi_master_idx(self
, idx
, name
, ifacenum
, typ
):
159 name
= self
.axi_master_name(name
, ifacenum
, typ
)
160 return ("typedef {0} {1};".format(idx
, name
), 1)
162 def axi_slave_idx(self
, idx
, name
, ifacenum
, typ
):
163 offs
= self
.num_axi_regs32()
166 if not isinstance(offs
, list):
169 for (i
, nregs
) in enumerate(offs
):
170 cfg
= self
.get_mmap_cfg_name(i
)
171 name_
= self
.axi_slave_name(cfg
, name
, ifacenum
, typ
)
172 res
.append("typedef {0} {1};".format(idx
+i
, name_
))
173 return ('\n'.join(res
), len(offs
))
175 def axi_fastaddr_map(self
, name
, ifacenum
):
176 return self
.axi_addr_map(name
, ifacenum
, 'fast')
178 def _axi_addr_map(self
, idx
, name
, ifacenum
, typ
=""):
179 bname
= self
.axibase(name
, ifacenum
, idx
)
180 bend
= self
.axiend(name
, ifacenum
, idx
)
181 name
= self
.axi_slave_name(idx
, name
, ifacenum
, typ
)
183 if(addr>=`{0} && addr<=`{1})
184 return tuple2(True,fromInteger(valueOf({2})));
186 return template
.format(bname
, bend
, name
)
188 def axi_addr_map(self
, name
, ifacenum
, typ
=""):
189 offs
= self
.num_axi_regs32()
192 if not isinstance(offs
, list):
195 for (idx
, nregs
) in enumerate(offs
):
196 cfg
= self
.get_mmap_cfg_name(idx
)
197 res
.append(self
._axi
_addr
_map
(cfg
, name
, ifacenum
, typ
))
198 return '\n'.join(res
)
200 def _mk_pincon(self
, name
, count
, ptyp
):
201 # TODO: really should be using bsv.interface_decl.Interfaces
202 # pin-naming rules.... logic here is hard-coded to duplicate
203 # it (see Interface.__init__ outen)
205 for p
in self
.peripheral
.pinspecs
:
208 #n = "{0}{1}".format(self.name, self.mksuffix(name, count))
209 n
= name
# "{0}{1}".format(self.name, self.mksuffix(name, count))
210 ret
.append("//%s %s" % (n
, str(p
)))
212 sname
= self
.get_iname(count
)
213 sname
= "{0}.{1}".format(sname
, pname
)
214 ps
= "slow_peripherals.%s" % sname
216 sname
= self
.peripheral
.iname().format(count
)
217 sname
= "{0}.{1}".format(sname
, pname
)
218 ps
= "pinmux.peripheral_side.%s" % sname
219 if typ
== 'out' or typ
== 'inout':
220 fname
= self
.pinname_out(pname
)
221 if not n
.startswith('gpio'): # XXX EURGH! horrible hack
222 n_
= "{0}{1}".format(n
, count
)
230 cn
= self
._mk
_actual
_connection
('out', name
,
232 pname
, ps_
, n_
, fname
)
236 fname
= self
.pinname_outen(pname
)
238 if isinstance(fname
, str):
239 fname
= "{0}.{1}".format(n_
, fname
)
240 fname
= self
.pinname_tweak(pname
, 'outen', fname
)
241 cn
= self
._mk
_actual
_connection
('outen', name
,
245 if typ
== 'in' or typ
== 'inout':
246 fname
= self
.pinname_in(pname
)
252 n_
= "{0}{1}".format(n
, count
)
253 n_
= '{0}.{1}'.format(n_
, fname
)
254 n_
= self
.ifname_tweak(pname
, 'in', n_
)
255 cn
= self
._mk
_actual
_connection
('in', name
,
257 pname
, ps_
, n_
, fname
)
259 return '\n'.join(ret
)
261 def _mk_vpincon(self
, name
, count
, ptyp
, typ
, pname
, stype
=None):
265 ret
.append("//%s %s %s %s %s" % (name
, ptyp
, typ
, pname
, stype
))
267 sname
= self
.get_iname(count
)
268 ps
= "slow_peripherals.%s" % sname
270 sname
= self
.peripheral
.iname().format(count
)
271 ps
= "pinmux.peripheral_side.%s" % sname
272 n
= self
.get_iname(count
)
274 n
= "{0}.{1}".format(n
, stype
)
275 ps_
= "{0}.{1}".format(ps
, pname
)
276 ret
+= self
._mk
_actual
_connection
(typ
, name
, count
, typ
,
277 pname
, ps_
, n
, stype
)
278 return '\n'.join(ret
)
280 def _mk_actual_connection(self
, ctype
, name
, count
, typ
,
281 pname
, ps
, n
, fname
):
283 ck
= self
.get_clock_reset(name
, count
)
285 if ck
== PBase
.get_clock_reset(self
, name
, count
):
286 ret
.append("mkConnection({0},\n\t\t\t{1}.{2});"
287 .format(ps
, n
, fname
))
289 n2
= "{0}{1}".format(name
, count
)
290 sync
= '{0}_{1}_sync'.format(n2
, pname
)
291 ret
.append("mkConnection({0},\n\t\t\t{1}.get);"
293 ret
.append("mkConnection({0}.put,\n\t\t\t{1}.{2});"
294 .format(sync
, n
, fname
))
295 elif ctype
== 'outen':
296 ret
.append("mkConnection({0}_outen,\n\t\t\t{1});"
299 if ck
== PBase
.get_clock_reset(self
, name
, count
):
300 ret
.append("mkConnection({1},\n\t\t\t{0});".format(
303 n2
= "{0}{1}".format(name
, count
)
304 sync
= '{0}_{1}_sync'.format(n2
, pname
)
305 ret
.append("mkConnection({1}.put,\n\t\t\t{0});".format(
307 ret
.append("mkConnection({1},\n\t\t\t{0}.get);".format(
312 def _mk_clk_con(self
, name
, count
, ctype
):
314 ck
= self
.get_clock_reset(name
, count
)
315 if ck
== PBase
.get_clock_reset(self
, name
, count
):
318 spc
= self
.get_clk_spc(ctype
)
321 ck
= self
.get_clk_spc(ctype
)
323 Ifc_sync#({0}) {1}_sync <-mksyncconnection(
325 for p
in self
.peripheral
.pinspecs
:
329 if typ
== 'out' or typ
== 'inout':
330 fname
= self
.pinname_out(pname
)
333 if not n
.startswith('gpio'): # XXX EURGH! horrible hack
334 n_
= "{0}{1}".format(n
, count
)
337 n_
= '{0}_{1}'.format(n_
, pname
)
338 ret
.append(template
.format("Bit#(1)", n_
, ck
, spc
))
339 if typ
== 'in' or typ
== 'inout':
340 fname
= self
.pinname_in(pname
)
343 #fname = self.pinname_in(pname)
344 n_
= "{0}{1}".format(n
, count
)
345 n_
= '{0}_{1}'.format(n_
, pname
)
346 #n_ = self.ifname_tweak(pname, 'in', n_)
347 ret
.append(template
.format("Bit#(1)", n_
, spc
, ck
))
348 return '\n'.join(ret
)
350 def get_clk_spc(self
, ctype
):
352 return "sp_clock, sp_reset"
354 return "core_clock, core_reset"
356 def _mk_clk_vcon(self
, name
, count
, ctype
, typ
, pname
, bitspec
):
357 ck
= self
.get_clock_reset(name
, count
)
358 if ck
== PBase
.get_clock_reset(self
, name
, count
):
361 spc
= self
.get_clk_spc(ctype
)
364 ck
= self
.get_clk_spc(ctype
)
366 Ifc_sync#({0}) {1}_sync <-mksyncconnection(
369 n_
= "{0}{1}".format(name
, count
)
370 n_
= '{0}_{1}'.format(n_
, pname
)
371 if typ
== 'in' or typ
== 'inout':
373 return template
.format(bitspec
, n_
, ck
, spc
)
376 def mk_cellconn(self
, *args
):
379 def mkfast_peripheral(self
, size
=0):
382 def mkslow_peripheral(self
, size
=0):
385 def mksuffix(self
, name
, i
):
388 def __mk_connection(self
, con
, aname
, count
, fabricname
):
389 txt
= "mkConnection ({2}.v_to_slaves\n" + \
390 " [fromInteger(valueOf({1}))],\n" + \
393 print "PBase __mk_connection", self
.name
, aname
396 con
= con
.format(count
, aname
)
397 return txt
.format(con
, aname
, fabricname
)
399 def __mk_master_connection(self
, con
, aname
, count
, fabricname
):
400 txt
= "mkConnection ({0}, {2}.v_from_masters\n" + \
401 " [fromInteger(valueOf({1}))]);\n"
403 print "PBase __mk_master_connection", self
.name
, aname
406 con
= con
.format(count
, aname
)
407 return txt
.format(con
, aname
, fabricname
)
409 def mk_master_connection(self
, count
, fabricname
, typ
, name
=None):
410 if not self
.has_axi_master():
414 print "PBase mk_master_conn", self
.name
, count
415 aname
= self
.axi_master_name(name
, count
, typ
)
417 connections
= self
._mk
_connection
(name
, count
, True)
418 if not isinstance(connections
, list):
419 connections
= [connections
]
420 for con
in connections
:
421 ret
.append(self
.__mk
_master
_connection
(con
, aname
, count
,
423 return '\n'.join(ret
)
425 def mk_connection(self
, count
, fabricname
, typ
, name
=None):
428 print "PBase mk_conn", self
.name
, count
430 connections
= self
._mk
_connection
(name
, count
)
431 if not isinstance(connections
, list):
432 connections
= [connections
]
433 for (idx
, con
) in enumerate(connections
):
434 if len(connections
) == 1:
438 aname
= self
.axi_slave_name(idx
, name
, count
, typ
)
439 ret
.append(self
.__mk
_connection
(con
, aname
, count
, fabricname
))
440 return '\n'.join(ret
)
442 def _mk_connection(self
, name
=None, count
=0):
445 def pinname_out(self
, pname
):
448 def pinname_in(self
, pname
):
451 def pinname_outen(self
, pname
):
454 def ifname_tweak(self
, pname
, typ
, txt
):
457 def pinname_tweak(self
, pname
, typ
, txt
):
463 def mk_plic(self
, inum
, irq_offs
):
465 print "mk_plic", self
.name
, inum
, irq_offs
466 niq
= self
.num_irqs()
468 return ('', irq_offs
)
469 name
= self
.get_iname(inum
)
470 res
.append("// PLIC rules for {0}".format(name
))
471 for idx
in range(niq
):
472 plic_obj
= self
.plic_object(name
, idx
)
473 print "plic_obj", name
, idx
, plic_obj
474 plic
= mkplic_rule
.format(name
, plic_obj
, irq_offs
)
476 irq_offs
+= 1 # increment to next irq
477 return ('\n'.join(res
), irq_offs
)
479 def mk_ext_ifacedef(self
, iname
, inum
):
482 def extfastifinstance(self
, name
, count
):
485 def _extifinstance(self
, name
, count
, suffix
, prefix
, samename
=False,
489 pname
= self
.get_iname(count
)
493 sname
= self
.peripheral
.iname().format(count
)
494 template
= "interface {0}{3} = {2}{1}{4};"
495 return template
.format(pname
, sname
, prefix
, suffix
, ifsuffix
)
497 def extifinstance2(self
, name
, count
):
500 def extifinstance(self
, name
, count
):
501 return self
._extifinstance
(name
, count
, "",
502 "pinmux.peripheral_side.")
506 rule rl_connect_{0}_to_plic_{2};
507 if({1} == 1'b1) begin
508 ff_gateway_queue[{2}].enq(1);
509 plic.ifc_external_irq[{2}].irq_frm_gateway(True);
514 axi_master_declarations
= """\
515 typedef 0 Dmem_master_num;
516 typedef 1 Imem_master_num;
518 typedef TAdd#(LastGen_master_num, `ifdef Debug 1 `else 0 `endif )
520 typedef TAdd#(Debug_master_num, `ifdef DMA 1 `else 0 `endif )
522 typedef TAdd#(DMA_master_num,1)
526 axi_fastslave_declarations
= """\
528 typedef TAdd#(LastGen_fastslave_num,1) Sdram_slave_num;
529 typedef TAdd#(Sdram_slave_num ,`ifdef SDRAM 1 `else 0 `endif )
531 typedef TAdd#(Sdram_cfg_slave_num,`ifdef BOOTROM 1 `else 0 `endif )
533 typedef TAdd#(BootRom_slave_num ,`ifdef Debug 1 `else 0 `endif )
535 typedef TAdd#(Debug_slave_num , `ifdef TCMemory 1 `else 0 `endif )
537 typedef TAdd#(TCM_slave_num ,`ifdef DMA 1 `else 0 `endif )
539 typedef TAdd#(Dma_slave_num ,1 ) SlowPeripheral_slave_num;
540 typedef TAdd#(SlowPeripheral_slave_num,`ifdef VME 1 `else 0 `endif )
542 typedef TAdd#(VME_slave_num,1) Num_Fast_Slaves;
545 axi_slave_declarations
= """\
546 typedef 0 SlowMaster;
548 typedef TAdd#(LastGen_slave_num,`ifdef CLINT 1 `else 0 `endif )
550 typedef TAdd#(CLINT_slave_num ,`ifdef PLIC 1 `else 0 `endif )
552 typedef TAdd#(Plic_slave_num ,`ifdef AXIEXP 1 `else 0 `endif )
554 typedef TAdd#(AxiExp1_slave_num,1) Num_Slow_Slaves;
557 pinmux_cellrule
= """\
558 rule connect_select_lines_pinmux;
564 class CallFn(object):
565 def __init__(self
, peripheral
, name
):
566 self
.peripheral
= peripheral
569 def __call__(self
, *args
):
570 #print "__call__", self.name, self.peripheral.slow, args
571 if not self
.peripheral
.slow
:
573 return getattr(self
.peripheral
.slow
, self
.name
)(*args
[1:])
576 class PeripheralIface(object):
577 def __init__(self
, ifacename
):
579 slow
= slowfactory
.getcls(ifacename
)
580 print "Iface", ifacename
, slow
582 self
.slow
= slow(ifacename
)
583 self
.slow
.peripheral
= self
584 for fname
in ['slowimport',
586 'extifinstance2', 'extifinstance', 'extifdecl',
587 'slowifdecl', 'slowifdeclmux',
590 'mk_dma_sync', 'mk_dma_connect', 'mk_dma_rule',
592 'mk_plic', 'mk_ext_ifacedef',
593 '_mk_clk_con', 'mk_ext_ifacedef',
594 'mk_connection', 'mk_master_connection',
595 'mk_cellconn', '_mk_pincon']:
596 fn
= CallFn(self
, fname
)
597 setattr(self
, fname
, types
.MethodType(fn
, self
))
599 #print "PeripheralIface"
602 def mksuffix(self
, name
, i
):
603 if self
.slow
is None:
605 return self
.slow
.mksuffix(name
, i
)
607 def axi_reg_def(self
, start
, count
):
610 return self
.slow
.axi_reg_def(start
, self
.ifacename
, count
)
612 def axi_master_idx(self
, start
, count
, typ
):
613 if not self
.slow
or not self
.slow
.has_axi_master():
615 return self
.slow
.axi_master_idx(start
, self
.ifacename
, count
, typ
)
617 def axi_slave_idx(self
, start
, count
, typ
):
620 return self
.slow
.axi_slave_idx(start
, self
.ifacename
, count
, typ
)
622 def axi_fastaddr_map(self
, count
):
625 return self
.slow
.axi_fastaddr_map(self
.ifacename
, count
)
627 def axi_addr_map(self
, count
):
630 return self
.slow
.axi_addr_map(self
.ifacename
, count
)
633 class PeripheralInterfaces(object):
635 self
.fastbusmode
= False
637 def slowimport(self
, *args
):
639 for (name
, count
) in self
.ifacecount
:
640 #print "slowimport", name, self.data[name].slowimport
641 ret
.append(self
.data
[name
].slowimport())
642 return '\n'.join(li(list(filter(None, ret
)), 4))
644 def extfastifinstance(self
, *args
):
646 for (name
, count
) in self
.ifacecount
:
647 for i
in range(count
):
648 iname
= self
.data
[name
].iname().format(i
)
649 print "extfast", iname
, self
.is_on_fastbus(name
, i
)
650 if self
.is_on_fastbus(name
, i
):
652 ret
.append(self
.data
[name
].extfastifinstance(name
, i
))
653 return '\n'.join(li(list(filter(None, ret
)), 8))
655 def extifinstance2(self
, *args
):
657 for (name
, count
) in self
.ifacecount
:
658 for i
in range(count
):
659 iname
= self
.data
[name
].iname().format(i
)
660 ret
.append(self
.data
[name
].extifinstance2(name
, i
))
661 return '\n'.join(li(list(filter(None, ret
)), 8))
663 def extifinstance(self
, *args
):
665 for (name
, count
) in self
.ifacecount
:
666 for i
in range(count
):
667 iname
= self
.data
[name
].iname().format(i
)
668 if not self
.is_on_fastbus(name
, i
):
670 ret
.append(self
.data
[name
].extifinstance(name
, i
))
671 return '\n'.join(li(list(filter(None, ret
)), 8))
673 def extifdecl(self
, *args
):
675 for (name
, count
) in self
.ifacecount
:
676 for i
in range(count
):
677 if not self
.is_on_fastbus(name
, i
):
679 ret
.append(self
.data
[name
].extifdecl(name
, i
))
680 return '\n'.join(li(list(filter(None, ret
)), 8))
682 def slowifdeclmux(self
, *args
):
684 for (name
, count
) in self
.ifacecount
:
685 for i
in range(count
):
686 ret
.append(self
.data
[name
].slowifdeclmux(name
, i
))
687 return '\n'.join(li(list(filter(None, ret
)), 8))
689 def fastifdecl(self
, *args
):
691 for (name
, count
) in self
.ifacecount
:
692 for i
in range(count
):
693 print "fastifdecl", name
, i
, self
.is_on_fastbus(name
, i
)
694 if self
.is_on_fastbus(name
, i
):
696 ret
.append(self
.data
[name
].fastifdecl(name
, i
))
697 return '\n'.join(li(list(filter(None, ret
)), 4))
699 def slowifdecl(self
, *args
):
701 for (name
, count
) in self
.ifacecount
:
702 for i
in range(count
):
703 if self
.is_on_fastbus(name
, i
):
705 ret
.append(self
.data
[name
].slowifdecl().format(i
, name
))
706 return '\n'.join(list(filter(None, ret
)))
708 def axi_fastmem_def(self
, *args
):
709 return self
._axi
_reg
_def
(0x50000000, *args
)
711 def axi_reg_def(self
, *args
):
712 return self
._axi
_reg
_def
(0x00011100, *args
)
714 def _axi_reg_def(self
, start
, *args
):
716 for (name
, count
) in self
.ifacecount
:
717 for i
in range(count
):
718 if self
.is_on_fastbus(name
, i
):
720 x
= self
.data
[name
].axi_reg_def(start
, i
)
721 #print ("ifc", name, x)
725 return '\n'.join(list(filter(None, ret
)))
727 def _axi_num_idx(self
, start
, template
, typ
, idxtype
, *args
):
729 for (name
, count
) in self
.ifacecount
:
730 for i
in range(count
):
731 if self
.is_on_fastbus(name
, i
):
734 fn
= self
.data
[name
].axi_master_idx
736 fn
= self
.data
[name
].axi_slave_idx
737 (rdef
, offs
) = fn(start
, i
, idxtype
)
738 #print ("ifc", name, rdef, offs)
741 ret
.append("typedef %d LastGen_%s_num;" % (start
- 1, typ
))
742 decls
= '\n'.join(list(filter(None, ret
)))
743 return template
.format(decls
)
745 def axi_slave_idx(self
, *args
):
746 return self
._axi
_num
_idx
(0, axi_slave_declarations
, 'slave',
749 def axi_fastslave_idx(self
, *args
):
750 return self
._axi
_num
_idx
(0, axi_fastslave_declarations
, 'fastslave',
753 def axi_master_idx(self
, *args
):
754 return self
._axi
_num
_idx
(2, axi_master_declarations
, 'master',
757 def axi_fastslave_idx(self
, *args
):
758 return self
._axi
_num
_idx
(0, axi_fastslave_declarations
, 'fastslave',
761 def axi_fastaddr_map(self
, *args
):
763 for (name
, count
) in self
.ifacecount
:
764 for i
in range(count
):
765 if self
.is_on_fastbus(name
, i
):
767 ret
.append(self
.data
[name
].axi_fastaddr_map(i
))
768 return '\n'.join(li(list(filter(None, ret
)), 8))
770 def axi_addr_map(self
, *args
):
772 for (name
, count
) in self
.ifacecount
:
773 for i
in range(count
):
774 if self
.is_on_fastbus(name
, i
):
776 ret
.append(self
.data
[name
].axi_addr_map(i
))
777 return '\n'.join(li(list(filter(None, ret
)), 8))
779 def mkfast_peripheral(self
, *args
):
781 for (name
, count
) in self
.ifacecount
:
782 for i
in range(count
):
783 if self
.is_on_fastbus(name
, i
):
785 #print "mkfast", name, count
786 x
= self
.data
[name
].mkfast_peripheral()
788 suffix
= self
.data
[name
].mksuffix(name
, i
)
789 ret
.append(x
.format(suffix
))
790 return '\n'.join(li(list(filter(None, ret
)), 8))
792 def mkslow_peripheral(self
, *args
):
794 for (name
, count
) in self
.ifacecount
:
795 for i
in range(count
):
796 if self
.is_on_fastbus(name
, i
):
798 #print "mkslow", name, count
799 x
= self
.data
[name
].mkslow_peripheral()
801 suffix
= self
.data
[name
].mksuffix(name
, i
)
802 ret
.append(x
.format(suffix
))
803 return '\n'.join(li(list(filter(None, ret
)), 8))
805 def _mk_connection(self
, fabric
, typ
, indent
, master
, *args
):
807 for (name
, count
) in self
.ifacecount
:
808 for i
in range(count
):
809 if self
.is_on_fastbus(name
, i
):
812 txt
= self
.data
[name
].mk_master_connection(i
, fabric
, typ
)
814 txt
= self
.data
[name
].mk_connection(i
, fabric
, typ
)
818 return '\n'.join(li(list(filter(None, ret
)), indent
))
820 def mk_master_connection(self
, *args
):
821 return self
._mk
_connection
("fabric", "fast", 8, True, *args
)
823 def mk_fast_connection(self
, *args
):
824 return self
._mk
_connection
("fabric", "fast", 12, False, *args
)
826 def mk_connection(self
, *args
):
827 return self
._mk
_connection
("slow_fabric", "", 8, False, *args
)
829 def mk_cellconn(self
):
832 for (name
, count
) in self
.ifacecount
:
833 for i
in range(count
):
834 if self
.is_on_fastbus(name
, i
):
836 res
= self
.data
[name
].mk_cellconn(cellcount
, name
, i
)
839 (txt
, cellcount
) = res
841 ret
= li('\n'.join(list(filter(None, ret
))), 4)
842 return li(pinmux_cellrule
.format(ret
), 4)
845 return self
._mk
_pincon
("slow")
847 def mk_fast_pincon(self
):
848 return self
._mk
_pincon
("fast")
850 def _mk_pincon(self
, typ
):
852 for (name
, count
) in self
.ifacecount
:
853 for i
in range(count
):
854 if self
.is_on_fastbus(name
, i
):
856 txt
= self
.data
[name
]._mk
_pincon
(name
, i
, typ
)
858 return '\n'.join(li(list(filter(None, ret
)), 4))
860 def mk_dma_irq(self
):
868 for (name
, count
) in self
.ifacecount
:
870 for i
in range(count
):
871 if not self
.is_on_fastbus(name
, i
):
873 txt
= self
.data
[name
].mk_dma_sync(name
, i
)
877 txt
= self
.data
[name
].mk_dma_rule(name
, i
)
878 ifacerules
.append(txt
)
879 txt
= self
.data
[name
].mk_dma_connect(name
, i
)
881 ifacerules
= list(filter(None, ifacerules
))
883 txt
= "rule synchronize_%s_interrupts;" % name
886 rules
.append("endrule")
888 cnct
= list(filter(None, cnct
))
890 _cnct
= ["rule rl_connect_interrupt_to_DMA;",
891 " Bit #(%d) lv_interrupt_to_DMA={" % ct
]
894 cnct
= _cnct
+ [spc
+ spcsep
.join(cnct
)]
896 cnct
.append(" dma.interrupt_from_peripherals(\n" +
897 " lv_interrupt_to_DMA);")
898 cnct
.append("endrule;")
900 ret
= list(filter(None, sync
+ rules
+ cnct
))
902 return '\n'.join(ret
)
904 def num_dmachannels(self
):
905 return "`define NUM_DMACHANNELS {0}".format(self
.dma_count
)
907 def mk_ext_ifacedef(self
):
909 for (name
, count
) in self
.ifacecount
:
910 for i
in range(count
):
911 if self
.is_on_fastbus(name
, i
):
913 txt
= self
.data
[name
].mk_ext_ifacedef(name
, i
)
915 return '\n'.join(li(list(filter(None, ret
)), 8))
919 irq_offs
= 8 # XXX: DMA scovers 0-7?
920 for (name
, count
) in self
.ifacecount
:
921 for i
in range(count
):
922 if self
.is_on_fastbus(name
, i
):
924 res
= self
.data
[name
].mk_plic(i
, irq_offs
)
927 (txt
, irq_offs
) = res
929 self
.num_slow_irqs
= irq_offs
930 return '\n'.join(li(list(filter(None, ret
)), 4))
932 def mk_sloirqsdef(self
):
933 return " `define NUM_SLOW_IRQS {0}".format(self
.num_slow_irqs
)
935 def mk_fastclk_con(self
):
936 return self
._mk
_clk
_con
("fast")
938 def mk_slowclk_con(self
):
939 return self
._mk
_clk
_con
("slow")
941 def _mk_clk_con(self
, ctype
):
943 for (name
, count
) in self
.ifacecount
:
944 for i
in range(count
):
945 if self
.is_on_fastbus(name
, i
):
947 txt
= self
.data
[name
]._mk
_clk
_con
(name
, i
, ctype
)
949 return '\n'.join(li(list(filter(None, ret
)), 8))
951 def is_on_fastbus(self
, name
, i
):
952 #print "fastbus mode", self.fastbusmode, name, i
953 iname
= self
.data
[name
].iname().format(i
)
955 return iname
not in self
.fastbus
956 return iname
in self
.fastbus
959 class PFactory(object):
960 def getcls(self
, name
):
961 from uart
import uart
962 from quart
import quart
963 from sdmmc
import sdmmc
965 from eint
import eint
966 from rs232
import rs232
968 from eint
import eint
969 from jtag
import jtag
970 from spi
import spi
, mspi
971 from qspi
import qspi
, mqspi
972 from gpio
import gpio
973 from rgbttl
import rgbttl
974 from flexbus
import flexbus
975 from sdram
import sdram
977 for k
, v
in {'uart': uart
,
994 if name
.startswith(k
):
999 slowfactory
= PFactory()
1001 if __name__
== '__main__':
1003 print p
.slowimport()
1004 print p
.slowifdecl()
1005 i
= PeripheralIface('uart')
1007 i
= PeripheralIface('gpioa')