src/bsv/peripheral_gen/base.py

   1 import types
   2
   3
   4 def li(txt, indent):
   5     indent = ' ' * indent
   6     istxt = False
   7     if isinstance(txt, str):
   8         istxt = True
   9         txt = txt.split('\n')
  10     res = []
  11     for line in txt:
  12         line = line.split('\n')
  13         res += line
  14     txt = res
  15     res = []
  16     for line in txt:
  17         res.append(indent + line)
  18     if istxt:
  19         res = '\n'.join(res)
  20     return res
  21
  22
  23 class PBase(object):
  24     def __init__(self, name):
  25         self.name = name
  26
  27     def extifdecl(self, name, count):
  28         sname = self.get_iname(count)
  29         return "interface PeripheralSide%s %s;" % (name.upper(), sname)
  30
  31     def has_axi_master(self):
  32         return False
  33
  34     def irq_name(self):
  35         return ""
  36
  37     def mk_dma_irq(self, name, count):
  38         if not self.irq_name():
  39             return ''
  40         sname = self.get_iname(count)
  41         return "{0}_interrupt".format(sname)
  42
  43     def mk_dma_rule(self, name, count):
  44         irqname = self.mk_dma_irq(name, count)
  45         if not irqname:
  46             return ''
  47         pirqname = self.irq_name().format(count)
  48         template = "   {0}_interrupt.send(\n" + \
  49                    "           slow_peripherals.{1});"
  50         return template.format(irqname, pirqname)
  51
  52     def get_clock_reset(self, name, count):
  53         return "slow_clock,slow_reset"
  54
  55     def mk_dma_sync(self, name, count):
  56         irqname = self.mk_dma_irq(name, count)
  57         if not irqname:
  58             return ''
  59         sname = self.peripheral.iname().format(count)
  60         template = "SyncBitIfc#(Bit#(1)) {0} <-\n" + \
  61                    "           <-mkSyncBitToCC({1});"
  62         return template.format(irqname, self.get_clock_reset(name, count))
  63
  64     def mk_dma_connect(self, name, count):
  65         irqname = self.mk_dma_irq(name, count)
  66         if not irqname:
  67             return ''
  68         return "{0}.read".format(irqname)
  69
  70     def fastifdecl(self, name, count):
  71         return ''
  72
  73     def slowifdeclmux(self, name, count):
  74         return ''
  75
  76     def slowimport(self):
  77         return ''
  78
  79     def num_axi_regs32(self):
  80         return 0
  81
  82     def slowifdecl(self):
  83         return ''
  84
  85     def get_iname(self, inum):
  86         return "{0}{1}".format(self.name, self.mksuffix(self.name, inum))
  87
  88     def axibase(self, name, ifacenum):
  89         name = name.upper()
  90         return "%(name)s%(ifacenum)dBase" % locals()
  91
  92     def axiend(self, name, ifacenum):
  93         name = name.upper()
  94         return "%(name)s%(ifacenum)dEnd" % locals()
  95
  96     def axi_reg_def(self, start, name, ifacenum):
  97         name = name.upper()
  98         offs = self.num_axi_regs32() * 4 * 16
  99         if offs == 0:
 100             return ('', 0)
 101         end = start + offs - 1
 102         bname = self.axibase(name, ifacenum)
 103         bend = self.axiend(name, ifacenum)
 104         comment = "%d 32-bit regs" % self.num_axi_regs32()
 105         return ("    `define %(bname)s 'h%(start)08X\n"
 106                 "    `define %(bend)s  'h%(end)08X // %(comment)s" % locals(),
 107                 offs)
 108
 109     def axi_master_name(self, name, ifacenum, typ=''):
 110         name = name.upper()
 111         return "{0}{1}_master_num".format(name, ifacenum)
 112
 113     def axi_slave_name(self, name, ifacenum, typ=''):
 114         name = name.upper()
 115         return "{0}{1}_{2}slave_num".format(name, ifacenum, typ)
 116
 117     def axi_master_idx(self, idx, name, ifacenum, typ):
 118         name = self.axi_master_name(name, ifacenum, typ)
 119         return ("typedef {0} {1};".format(idx, name), 1)
 120
 121     def axi_slave_idx(self, idx, name, ifacenum, typ):
 122         name = self.axi_slave_name(name, ifacenum, typ)
 123         return ("typedef {0} {1};".format(idx, name), 1)
 124
 125     def axi_fastaddr_map(self, name, ifacenum):
 126         return self.axi_addr_map(name, ifacenum, 'fast')
 127
 128     def axi_addr_map(self, name, ifacenum, typ=""):
 129         bname = self.axibase(name, ifacenum)
 130         bend = self.axiend(name, ifacenum)
 131         name = self.axi_slave_name(name, ifacenum, typ)
 132         template = """\
 133 if(addr>=`{0} && addr<=`{1})
 134     return tuple2(True,fromInteger(valueOf({2})));
 135 else"""
 136         return template.format(bname, bend, name)
 137
 138     def _mk_pincon(self, name, count, ptyp):
 139         # TODO: really should be using bsv.interface_decl.Interfaces
 140         # pin-naming rules.... logic here is hard-coded to duplicate
 141         # it (see Interface.__init__ outen)
 142         ret = []
 143         for p in self.peripheral.pinspecs:
 144             typ = p['type']
 145             pname = p['name']
 146             #n = "{0}{1}".format(self.name, self.mksuffix(name, count))
 147             n = name  # "{0}{1}".format(self.name, self.mksuffix(name, count))
 148             ret.append("//%s %s" % (n, str(p)))
 149             if ptyp == 'fast':
 150                 sname = self.get_iname(count)
 151                 sname = "{0}.{1}".format(sname, pname)
 152                 ps = "slow_peripherals.%s" % sname
 153             else:
 154                 sname = self.peripheral.iname().format(count)
 155                 sname = "{0}.{1}".format(sname, pname)
 156                 ps = "pinmux.peripheral_side.%s" % sname
 157             if typ == 'out' or typ == 'inout':
 158                 fname = self.pinname_out(pname)
 159                 if not n.startswith('gpio'):  # XXX EURGH! horrible hack
 160                     n_ = "{0}{1}".format(n, count)
 161                 else:
 162                     n_ = n
 163                 if fname:
 164                     if p.get('outen'):
 165                         ps_ = ps + '_out'
 166                     else:
 167                         ps_ = ps
 168                     ret.append("mkConnection({0},\n\t\t\t{1}.{2});"
 169                                .format(ps_, n_, fname))
 170                 fname = None
 171                 if p.get('outen'):
 172                     fname = self.pinname_outen(pname)
 173                 if fname:
 174                     if isinstance(fname, str):
 175                         fname = "{0}.{1}".format(n_, fname)
 176                     fname = self.pinname_tweak(pname, 'outen', fname)
 177                     ret.append("mkConnection({0}_outen,\n\t\t\t{1});"
 178                                .format(ps, fname))
 179             if typ == 'in' or typ == 'inout':
 180                 fname = self.pinname_in(pname)
 181                 if fname:
 182                     if p.get('outen'):
 183                         ps_ = ps + '_in'
 184                     else:
 185                         ps_ = ps
 186                     n_ = "{0}{1}".format(n, count)
 187                     n_ = '{0}.{1}'.format(n_, fname)
 188                     n_ = self.ifname_tweak(pname, 'in', n_)
 189                     ret.append(
 190                         "mkConnection({1},\n\t\t\t{0});".format(
 191                             ps_, n_))
 192         return '\n'.join(ret)
 193
 194     def mk_cellconn(self, *args):
 195         return ''
 196
 197     def mkfast_peripheral(self, size=0):
 198         return ''
 199
 200     def mkslow_peripheral(self, size=0):
 201         return ''
 202
 203     def mksuffix(self, name, i):
 204         return i
 205
 206     def __mk_connection(self, con, aname, fabricname):
 207         txt = "mkConnection ({2}.v_to_slaves\n" + \
 208               "            [fromInteger(valueOf({1}))],\n" + \
 209               "            {0});"
 210
 211         print "PBase __mk_connection", self.name, aname
 212         if not con:
 213             return ''
 214         return txt.format(con, aname, fabricname)
 215
 216     def __mk_master_connection(self, con, aname):
 217         txt = "mkConnection (slow_fabric.v_to_slaves\n" + \
 218               "            [fromInteger(valueOf({1}))],\n" + \
 219               "            {0});"
 220
 221         print "PBase __mk_connection", self.name, aname
 222         if not con:
 223             return ''
 224         return txt.format(con, aname)
 225
 226     def mk_connection(self, count, fabricname, typ, name=None):
 227         if name is None:
 228             name = self.name
 229         print "PBase mk_conn", self.name, count
 230         aname = self.axi_slave_name(name, count, typ)
 231         #dname = self.mksuffix(name, count)
 232         #dname = "{0}{1}".format(name, dname)
 233         con = self._mk_connection(name, count).format(count, aname)
 234         return self.__mk_connection(con, aname, fabricname)
 235
 236     def _mk_connection(self, name=None, count=0):
 237         return ''
 238
 239     def pinname_out(self, pname):
 240         return ''
 241
 242     def pinname_in(self, pname):
 243         return ''
 244
 245     def pinname_outen(self, pname):
 246         return ''
 247
 248     def ifname_tweak(self, pname, typ, txt):
 249         return txt
 250
 251     def pinname_tweak(self, pname, typ, txt):
 252         return txt
 253
 254     def num_irqs(self):
 255         return 0
 256
 257     def mk_plic(self, inum, irq_offs):
 258         res = []
 259         print "mk_plic", self.name, inum, irq_offs
 260         niq = self.num_irqs()
 261         if niq == 0:
 262             return ('', irq_offs)
 263         name = self.get_iname(inum)
 264         res.append("// PLIC rules for {0}".format(name))
 265         for idx in range(niq):
 266             plic_obj = self.plic_object(name, idx)
 267             print "plic_obj", name, idx, plic_obj
 268             plic = mkplic_rule.format(name, plic_obj, irq_offs)
 269             res.append(plic)
 270             irq_offs += 1  # increment to next irq
 271         return ('\n'.join(res), irq_offs)
 272
 273     def mk_ext_ifacedef(self, iname, inum):
 274         return ''
 275
 276     def extfastifinstance(self, name, count):
 277         return ''
 278
 279     def _extifinstance(self, name, count, suffix, prefix, samename=False,
 280                        ifsuffix=None):
 281         if ifsuffix is None:
 282             ifsuffix = ''
 283         pname = self.get_iname(count)
 284         if samename:
 285             sname = pname
 286         else:
 287             sname = self.peripheral.iname().format(count)
 288         template = "interface {0}{3} = {2}{1}{4};"
 289         return template.format(pname, sname, prefix, suffix, ifsuffix)
 290
 291     def extifinstance2(self, name, count):
 292         return ''
 293
 294     def extifinstance(self, name, count):
 295         return self._extifinstance(name, count, "",
 296                                    "pinmux.peripheral_side.")
 297
 298
 299 mkplic_rule = """\
 300 rule rl_connect_{0}_to_plic_{2};
 301    if({1} == 1'b1) begin
 302        ff_gateway_queue[{2}].enq(1);
 303        plic.ifc_external_irq[{2}].irq_frm_gateway(True);
 304    end
 305 endrule
 306 """
 307
 308 axi_master_declarations = """\
 309 typedef 0 Dmem_master_num;
 310 typedef 1 Imem_master_num;
 311 {0}
 312 typedef TAdd#(LastGen_master_num, `ifdef Debug 1 `else 0 `endif )
 313                 Debug_master_num;
 314 typedef TAdd#(Debug_master_num, `ifdef DMA 1 `else 0 `endif )
 315                 DMA_master_num;
 316 typedef TAdd#(DMA_master_num,1)
 317                 Num_Masters;
 318 """
 319
 320 axi_fastslave_declarations = """\
 321 {0}
 322 typedef  TAdd#(LastGen_fastslave_num,1)      Sdram_slave_num;
 323 typedef  TAdd#(Sdram_slave_num   ,`ifdef SDRAM      1 `else 0 `endif )
 324                       Sdram_cfg_slave_num;
 325 typedef TAdd#(Sdram_cfg_slave_num,`ifdef BOOTROM    1 `else 0 `endif )
 326                 BootRom_slave_num   ;
 327 typedef TAdd#(BootRom_slave_num  ,`ifdef Debug      1 `else 0 `endif )
 328                 Debug_slave_num ;
 329 typedef  TAdd#(Debug_slave_num   , `ifdef TCMemory  1 `else 0 `endif )
 330                 TCM_slave_num;
 331 typedef  TAdd#(TCM_slave_num     ,`ifdef DMA        1 `else 0 `endif )
 332                 Dma_slave_num;
 333 typedef  TAdd#(Dma_slave_num      ,1 )      SlowPeripheral_slave_num;
 334 typedef  TAdd#(SlowPeripheral_slave_num,`ifdef VME  1 `else 0 `endif )
 335                 VME_slave_num;
 336 typedef TAdd#(VME_slave_num,1) Num_Fast_Slaves;
 337 """
 338
 339 axi_slave_declarations = """\
 340 typedef  0  SlowMaster;
 341 {0}
 342 typedef  TAdd#(LastGen_slave_num,`ifdef CLINT       1 `else 0 `endif )
 343               CLINT_slave_num;
 344 typedef  TAdd#(CLINT_slave_num  ,`ifdef PLIC        1 `else 0 `endif )
 345               Plic_slave_num;
 346 typedef  TAdd#(Plic_slave_num   ,`ifdef AXIEXP      1 `else 0 `endif )
 347               AxiExp1_slave_num;
 348 typedef TAdd#(AxiExp1_slave_num,1) Num_Slow_Slaves;
 349 """
 350
 351 pinmux_cellrule = """\
 352 rule connect_select_lines_pinmux;
 353 {0}
 354 endrule
 355 """
 356
 357
 358 class CallFn(object):
 359     def __init__(self, peripheral, name):
 360         self.peripheral = peripheral
 361         self.name = name
 362
 363     def __call__(self, *args):
 364         #print "__call__", self.name, self.peripheral.slow, args
 365         if not self.peripheral.slow:
 366             return ''
 367         return getattr(self.peripheral.slow, self.name)(*args[1:])
 368
 369
 370 class PeripheralIface(object):
 371     def __init__(self, ifacename):
 372         self.slow = None
 373         slow = slowfactory.getcls(ifacename)
 374         print "Iface", ifacename, slow
 375         if slow:
 376             self.slow = slow(ifacename)
 377             self.slow.peripheral = self
 378         for fname in ['slowimport',
 379                       'extfastifinstance',
 380                       'extifinstance2', 'extifinstance', 'extifdecl',
 381                       'slowifdecl', 'slowifdeclmux',
 382                       'fastifdecl',
 383                       'mkslow_peripheral',
 384                       'mk_dma_sync', 'mk_dma_connect', 'mk_dma_rule',
 385                       'mkfast_peripheral',
 386                       'mk_plic', 'mk_ext_ifacedef',
 387                       'mk_connection', 'mk_cellconn', '_mk_pincon']:
 388             fn = CallFn(self, fname)
 389             setattr(self, fname, types.MethodType(fn, self))
 390
 391         #print "PeripheralIface"
 392         #print dir(self)
 393
 394     def mksuffix(self, name, i):
 395         if self.slow is None:
 396             return i
 397         return self.slow.mksuffix(name, i)
 398
 399     def axi_reg_def(self, start, count):
 400         if not self.slow:
 401             return ('', 0)
 402         return self.slow.axi_reg_def(start, self.ifacename, count)
 403
 404     def axi_master_idx(self, start, count, typ):
 405         if not self.slow or not self.slow.has_axi_master():
 406             return ('', 0)
 407         return self.slow.axi_master_idx(start, self.ifacename, count, typ)
 408
 409     def axi_slave_idx(self, start, count, typ):
 410         if not self.slow:
 411             return ('', 0)
 412         return self.slow.axi_slave_idx(start, self.ifacename, count, typ)
 413
 414     def axi_fastaddr_map(self, count):
 415         if not self.slow:
 416             return ''
 417         return self.slow.axi_fastaddr_map(self.ifacename, count)
 418
 419     def axi_addr_map(self, count):
 420         if not self.slow:
 421             return ''
 422         return self.slow.axi_addr_map(self.ifacename, count)
 423
 424
 425 class PeripheralInterfaces(object):
 426     def __init__(self):
 427         self.fastbusmode = False
 428
 429     def slowimport(self, *args):
 430         ret = []
 431         for (name, count) in self.ifacecount:
 432             #print "slowimport", name, self.data[name].slowimport
 433             ret.append(self.data[name].slowimport())
 434         return '\n'.join(li(list(filter(None, ret)), 4))
 435
 436     def extfastifinstance(self, *args):
 437         ret = []
 438         for (name, count) in self.ifacecount:
 439             for i in range(count):
 440                 iname = self.data[name].iname().format(i)
 441                 print "extfast", iname, self.is_on_fastbus(name, i)
 442                 if self.is_on_fastbus(name, i):
 443                     continue
 444                 ret.append(self.data[name].extfastifinstance(name, i))
 445         return '\n'.join(li(list(filter(None, ret)), 8))
 446
 447     def extifinstance2(self, *args):
 448         ret = []
 449         for (name, count) in self.ifacecount:
 450             for i in range(count):
 451                 iname = self.data[name].iname().format(i)
 452                 ret.append(self.data[name].extifinstance2(name, i))
 453         return '\n'.join(li(list(filter(None, ret)), 8))
 454
 455     def extifinstance(self, *args):
 456         ret = []
 457         for (name, count) in self.ifacecount:
 458             for i in range(count):
 459                 iname = self.data[name].iname().format(i)
 460                 if not self.is_on_fastbus(name, i):
 461                     continue
 462                 ret.append(self.data[name].extifinstance(name, i))
 463         return '\n'.join(li(list(filter(None, ret)), 8))
 464
 465     def extifdecl(self, *args):
 466         ret = []
 467         for (name, count) in self.ifacecount:
 468             for i in range(count):
 469                 if not self.is_on_fastbus(name, i):
 470                     continue
 471                 ret.append(self.data[name].extifdecl(name, i))
 472         return '\n'.join(li(list(filter(None, ret)), 8))
 473
 474     def slowifdeclmux(self, *args):
 475         ret = []
 476         for (name, count) in self.ifacecount:
 477             for i in range(count):
 478                 ret.append(self.data[name].slowifdeclmux(name, i))
 479         return '\n'.join(li(list(filter(None, ret)), 8))
 480
 481     def fastifdecl(self, *args):
 482         ret = []
 483         for (name, count) in self.ifacecount:
 484             for i in range(count):
 485                 print "fastifdecl", name, i, self.is_on_fastbus(name, i)
 486                 if self.is_on_fastbus(name, i):
 487                     continue
 488                 ret.append(self.data[name].fastifdecl(name, i))
 489         return '\n'.join(li(list(filter(None, ret)), 4))
 490
 491     def slowifdecl(self, *args):
 492         ret = []
 493         for (name, count) in self.ifacecount:
 494             for i in range(count):
 495                 if self.is_on_fastbus(name, i):
 496                     continue
 497                 ret.append(self.data[name].slowifdecl().format(i, name))
 498         return '\n'.join(list(filter(None, ret)))
 499
 500     def axi_fastmem_def(self, *args):
 501         return self._axi_reg_def(0x50000000, *args)
 502
 503     def axi_reg_def(self, *args):
 504         return self._axi_reg_def(0x00011100, *args)
 505
 506     def _axi_reg_def(self, start, *args):
 507         ret = []
 508         for (name, count) in self.ifacecount:
 509             for i in range(count):
 510                 if self.is_on_fastbus(name, i):
 511                     continue
 512                 x = self.data[name].axi_reg_def(start, i)
 513                 #print ("ifc", name, x)
 514                 (rdef, offs) = x
 515                 ret.append(rdef)
 516                 start += offs
 517         return '\n'.join(list(filter(None, ret)))
 518
 519     def _axi_num_idx(self, start, template, typ, idxtype, *args):
 520         ret = []
 521         for (name, count) in self.ifacecount:
 522             for i in range(count):
 523                 if self.is_on_fastbus(name, i):
 524                     continue
 525                 if typ == 'master':
 526                     fn = self.data[name].axi_master_idx
 527                 else:
 528                     fn = self.data[name].axi_slave_idx
 529                 (rdef, offs) = fn(start, i, idxtype)
 530                 #print ("ifc", name, rdef, offs)
 531                 ret.append(rdef)
 532                 start += offs
 533         ret.append("typedef %d LastGen_%s_num;" % (start - 1, typ))
 534         decls = '\n'.join(list(filter(None, ret)))
 535         return template.format(decls)
 536
 537     def axi_slave_idx(self, *args):
 538         return self._axi_num_idx(0, axi_slave_declarations, 'slave',
 539                                  '', *args)
 540
 541     def axi_fastslave_idx(self, *args):
 542         return self._axi_num_idx(0, axi_fastslave_declarations, 'fastslave',
 543                                  'fast', *args)
 544
 545     def axi_master_idx(self, *args):
 546         return self._axi_num_idx(2, axi_master_declarations, 'master',
 547                                  'master', *args)
 548
 549     def axi_fastslave_idx(self, *args):
 550         return self._axi_num_idx(0, axi_fastslave_declarations, 'fastslave',
 551                                  'fast', *args)
 552
 553     def axi_fastaddr_map(self, *args):
 554         ret = []
 555         for (name, count) in self.ifacecount:
 556             for i in range(count):
 557                 if self.is_on_fastbus(name, i):
 558                     continue
 559                 ret.append(self.data[name].axi_fastaddr_map(i))
 560         return '\n'.join(li(list(filter(None, ret)), 8))
 561
 562     def axi_addr_map(self, *args):
 563         ret = []
 564         for (name, count) in self.ifacecount:
 565             for i in range(count):
 566                 if self.is_on_fastbus(name, i):
 567                     continue
 568                 ret.append(self.data[name].axi_addr_map(i))
 569         return '\n'.join(li(list(filter(None, ret)), 8))
 570
 571     def mkfast_peripheral(self, *args):
 572         ret = []
 573         for (name, count) in self.ifacecount:
 574             for i in range(count):
 575                 if self.is_on_fastbus(name, i):
 576                     continue
 577                 #print "mkfast", name, count
 578                 x = self.data[name].mkfast_peripheral()
 579                 print name, count, x
 580                 suffix = self.data[name].mksuffix(name, i)
 581                 ret.append(x.format(suffix))
 582         return '\n'.join(li(list(filter(None, ret)), 8))
 583
 584     def mkslow_peripheral(self, *args):
 585         ret = []
 586         for (name, count) in self.ifacecount:
 587             for i in range(count):
 588                 if self.is_on_fastbus(name, i):
 589                     continue
 590                 #print "mkslow", name, count
 591                 x = self.data[name].mkslow_peripheral()
 592                 print name, count, x
 593                 suffix = self.data[name].mksuffix(name, i)
 594                 ret.append(x.format(suffix))
 595         return '\n'.join(li(list(filter(None, ret)), 8))
 596
 597     def mk_fast_connection(self, *args):
 598         ret = []
 599         for (name, count) in self.ifacecount:
 600             for i in range(count):
 601                 if self.is_on_fastbus(name, i):
 602                     continue
 603                 txt = self.data[name].mk_connection(i, "fabric", "fast")
 604                 if name == 'gpioa':
 605                     print "txt", txt
 606                     print self.data[name].mk_connection
 607                 ret.append(txt)
 608         return '\n'.join(li(list(filter(None, ret)), 12))
 609
 610     def mk_connection(self, *args):
 611         ret = []
 612         for (name, count) in self.ifacecount:
 613             for i in range(count):
 614                 if self.is_on_fastbus(name, i):
 615                     continue
 616                 txt = self.data[name].mk_connection(i, "slow_fabric", "")
 617                 if name == 'gpioa':
 618                     print "txt", txt
 619                     print self.data[name].mk_connection
 620                 ret.append(txt)
 621         return '\n'.join(li(list(filter(None, ret)), 8))
 622
 623     def mk_cellconn(self):
 624         ret = []
 625         cellcount = 0
 626         for (name, count) in self.ifacecount:
 627             for i in range(count):
 628                 if self.is_on_fastbus(name, i):
 629                     continue
 630                 res = self.data[name].mk_cellconn(cellcount, name, i)
 631                 if not res:
 632                     continue
 633                 (txt, cellcount) = res
 634                 ret.append(txt)
 635         ret = li('\n'.join(list(filter(None, ret))), 4)
 636         return li(pinmux_cellrule.format(ret), 4)
 637
 638     def mk_pincon(self):
 639         return self._mk_pincon("slow")
 640
 641     def mk_fast_pincon(self):
 642         return self._mk_pincon("fast")
 643
 644     def _mk_pincon(self, typ):
 645         ret = []
 646         for (name, count) in self.ifacecount:
 647             for i in range(count):
 648                 if self.is_on_fastbus(name, i):
 649                     continue
 650                 txt = self.data[name]._mk_pincon(name, i, typ)
 651                 ret.append(txt)
 652         return '\n'.join(li(list(filter(None, ret)), 4))
 653
 654     def mk_dma_irq(self):
 655         ret = []
 656         sync = []
 657         rules = []
 658         cnct = []
 659
 660         self.dma_count = 0
 661
 662         for (name, count) in self.ifacecount:
 663             ifacerules = []
 664             for i in range(count):
 665                 if not self.is_on_fastbus(name, i):
 666                     continue
 667                 txt = self.data[name].mk_dma_sync(name, i)
 668                 if txt:
 669                     self.dma_count += 1
 670                 sync.append(txt)
 671                 txt = self.data[name].mk_dma_rule(name, i)
 672                 ifacerules.append(txt)
 673                 txt = self.data[name].mk_dma_connect(name, i)
 674                 cnct.append(txt)
 675             ifacerules = list(filter(None, ifacerules))
 676             if ifacerules:
 677                 txt = "rule synchronize_%s_interrupts;" % name
 678                 rules.append(txt)
 679                 rules += ifacerules
 680                 rules.append("endrule")
 681
 682         cnct = list(filter(None, cnct))
 683         ct = self.dma_count
 684         _cnct = ["rule rl_connect_interrupt_to_DMA;",
 685                  "  Bit #(%d) lv_interrupt_to_DMA={" % ct]
 686         spc = "                      "
 687         spcsep = ",\n" + spc
 688         cnct = _cnct + [spc + spcsep.join(cnct)]
 689         cnct.append("   };")
 690         cnct.append("   dma.interrupt_from_peripherals(\n" +
 691                     "       lv_interrupt_to_DMA);")
 692         cnct.append("endrule;")
 693
 694         ret = list(filter(None, sync + rules + cnct))
 695         ret = li(ret, 15)
 696         return '\n'.join(ret)
 697
 698     def num_dmachannels(self):
 699         return "`define NUM_DMACHANNELS {0}".format(self.dma_count)
 700
 701     def mk_ext_ifacedef(self):
 702         ret = []
 703         for (name, count) in self.ifacecount:
 704             for i in range(count):
 705                 if self.is_on_fastbus(name, i):
 706                     continue
 707                 txt = self.data[name].mk_ext_ifacedef(name, i)
 708                 ret.append(txt)
 709         return '\n'.join(li(list(filter(None, ret)), 8))
 710
 711     def mk_plic(self):
 712         ret = []
 713         irq_offs = 8  # XXX: DMA scovers 0-7?
 714         for (name, count) in self.ifacecount:
 715             for i in range(count):
 716                 if self.is_on_fastbus(name, i):
 717                     continue
 718                 res = self.data[name].mk_plic(i, irq_offs)
 719                 if not res:
 720                     continue
 721                 (txt, irq_offs) = res
 722                 ret.append(txt)
 723         self.num_slow_irqs = irq_offs
 724         return '\n'.join(li(list(filter(None, ret)), 4))
 725
 726     def mk_sloirqsdef(self):
 727         return "    `define NUM_SLOW_IRQS {0}".format(self.num_slow_irqs)
 728
 729     def is_on_fastbus(self, name, i):
 730         #print "fastbus mode", self.fastbusmode, name, i
 731         iname = self.data[name].iname().format(i)
 732         if self.fastbusmode:
 733             return iname not in self.fastbus
 734         return iname in self.fastbus
 735
 736
 737 class PFactory(object):
 738     def getcls(self, name):
 739         from uart import uart
 740         from quart import quart
 741         from sdmmc import sdmmc
 742         from pwm import pwm
 743         from eint import eint
 744         from rs232 import rs232
 745         from twi import twi
 746         from eint import eint
 747         from jtag import jtag
 748         from spi import spi, mspi
 749         from qspi import qspi, mqspi
 750         from gpio import gpio
 751         from rgbttl import rgbttl
 752         from flexbus import flexbus
 753
 754         for k, v in {'uart': uart,
 755                      'rs232': rs232,
 756                      'twi': twi,
 757                      'quart': quart,
 758                      'mqspi': mqspi,
 759                      'mspi': mspi,
 760                      'qspi': qspi,
 761                      'spi': spi,
 762                      'pwm': pwm,
 763                      'eint': eint,
 764                      'sd': sdmmc,
 765                      'jtag': jtag,
 766                      'lcd': rgbttl,
 767                      'fb': flexbus,
 768                      'gpio': gpio
 769                      }.items():
 770             if name.startswith(k):
 771                 return v
 772         return None
 773
 774
 775 slowfactory = PFactory()
 776
 777 if __name__ == '__main__':
 778     p = uart('uart')
 779     print p.slowimport()
 780     print p.slowifdecl()
 781     i = PeripheralIface('uart')
 782     print i, i.slow
 783     i = PeripheralIface('gpioa')
 784     print i, i.slow