src/bsv/peripheral_gen/base.py

   1 import types
   2 from copy import deepcopy
   3
   4
   5 class PBase(object):
   6     def __init__(self, name):
   7         self.name = name
   8
   9     def slowifdeclmux(self):
  10         return ''
  11
  12     def slowifinstance(self):
  13         return ''
  14
  15     def slowimport(self):
  16         return ''
  17
  18     def num_axi_regs32(self):
  19         return 0
  20
  21     def slowifdecl(self):
  22         return ''
  23
  24     def get_iname(self, inum):
  25         return "{0}{1}".format(self.name, self.mksuffix(self.name, inum))
  26
  27     def axibase(self, name, ifacenum):
  28         name = name.upper()
  29         return "%(name)s%(ifacenum)dBase" % locals()
  30
  31     def axiend(self, name, ifacenum):
  32         name = name.upper()
  33         return "%(name)s%(ifacenum)dEnd" % locals()
  34
  35     def axi_reg_def(self, start, name, ifacenum):
  36         name = name.upper()
  37         offs = self.num_axi_regs32() * 4 * 16
  38         if offs == 0:
  39             return ('', 0)
  40         end = start + offs - 1
  41         bname = self.axibase(name, ifacenum)
  42         bend = self.axiend(name, ifacenum)
  43         comment = "%d 32-bit regs" % self.num_axi_regs32()
  44         return ("    `define %(bname)s 'h%(start)08X\n"
  45                 "    `define %(bend)s  'h%(end)08X // %(comment)s" % locals(),
  46                 offs)
  47
  48     def axi_slave_name(self, name, ifacenum):
  49         name = name.upper()
  50         return "{0}{1}_slave_num".format(name, ifacenum)
  51
  52     def axi_slave_idx(self, idx, name, ifacenum):
  53         name = self.axi_slave_name(name, ifacenum)
  54         return ("typedef {0} {1};".format(idx, name), 1)
  55
  56     def axi_addr_map(self, name, ifacenum):
  57         bname = self.axibase(name, ifacenum)
  58         bend = self.axiend(name, ifacenum)
  59         name = self.axi_slave_name(name, ifacenum)
  60         return """\
  61         if(addr>=`{0} && addr<=`{1})
  62             return tuple2(True,fromInteger(valueOf({2})));
  63         else""".format(bname, bend, name)
  64
  65     def mk_pincon(self, name, count):
  66         # TODO: really should be using bsv.interface_decl.Interfaces
  67         # pin-naming rules.... logic here is hard-coded to duplicate
  68         # it (see Interface.__init__ outen)
  69         ret = []
  70         for p in self.peripheral.pinspecs:
  71             typ = p['type']
  72             pname = p['name']
  73             #n = "{0}{1}".format(self.name, self.mksuffix(name, count))
  74             n = name  # "{0}{1}".format(self.name, self.mksuffix(name, count))
  75             ret.append("    //%s %s" % (n, str(p)))
  76             sname = self.peripheral.pname(pname).format(count)
  77             ps = "pinmux.peripheral_side.%s" % sname
  78             if typ == 'out' or typ == 'inout':
  79                 ret.append("    rule con_%s%d_%s_out;" % (name, count, pname))
  80                 fname = self.pinname_out(pname)
  81                 if not n.startswith('gpio'):  # XXX EURGH! horrible hack
  82                     n_ = "{0}{1}".format(n, count)
  83                 else:
  84                     n_ = n
  85                 if fname:
  86                     if p.get('outen'):
  87                         ps_ = ps + '_out'
  88                     else:
  89                         ps_ = ps
  90                     ret.append("      {0}({1}.{2});".format(ps_, n_, fname))
  91                 fname = None
  92                 if p.get('outen'):
  93                     fname = self.pinname_outen(pname)
  94                 if fname:
  95                     if isinstance(fname, str):
  96                         fname = "{0}.{1}".format(n_, fname)
  97                     fname = self.pinname_tweak(pname, 'outen', fname)
  98                     ret.append("      {0}_outen({1});".format(ps, fname))
  99                 ret.append("    endrule")
 100             if typ == 'in' or typ == 'inout':
 101                 fname = self.pinname_in(pname)
 102                 if fname:
 103                     if p.get('outen'):
 104                         ps_ = ps + '_in'
 105                     else:
 106                         ps_ = ps
 107                     ret.append(
 108                         "    rule con_%s%d_%s_in;" %
 109                         (name, count, pname))
 110                     n_ = "{0}{1}".format(n, count)
 111                     n_ = '{0}.{1}'.format(n_, fname)
 112                     n_ = self.ifname_tweak(pname, 'in', n_)
 113                     ret.append("      {1}({0});".format(ps_, n_))
 114                     ret.append("    endrule")
 115         return '\n'.join(ret)
 116
 117     def mk_cellconn(self, *args):
 118         return ''
 119
 120     def mkslow_peripheral(self, size=0):
 121         return ''
 122
 123     def mksuffix(self, name, i):
 124         return i
 125
 126     def __mk_connection(self, con, aname):
 127         txt = "        mkConnection (slow_fabric.v_to_slaves\n" + \
 128             "                    [fromInteger(valueOf({1}))],\n" + \
 129             "                    {0});"
 130
 131         print "PBase __mk_connection", self.name, aname
 132         if not con:
 133             return ''
 134         return txt.format(con, aname)
 135
 136     def mk_connection(self, count, name=None):
 137         if name is None:
 138             name = self.name
 139         print "PBase mk_conn", self.name, count
 140         aname = self.axi_slave_name(name, count)
 141         #dname = self.mksuffix(name, count)
 142         #dname = "{0}{1}".format(name, dname)
 143         con = self._mk_connection(name, count).format(count, aname)
 144         return self.__mk_connection(con, aname)
 145
 146     def _mk_connection(self, name=None, count=0):
 147         return ''
 148
 149     def pinname_out(self, pname):
 150         return ''
 151
 152     def pinname_in(self, pname):
 153         return ''
 154
 155     def pinname_outen(self, pname):
 156         return ''
 157
 158     def ifname_tweak(self, pname, typ, txt):
 159         return txt
 160
 161     def pinname_tweak(self, pname, typ, txt):
 162         return txt
 163
 164     def num_irqs(self):
 165         return 0
 166
 167     def mk_plic(self, inum, irq_offs):
 168         res = []
 169         print "mk_plic", self.name, inum, irq_offs
 170         niq = self.num_irqs()
 171         if niq == 0:
 172             return ('', irq_offs)
 173         name = self.get_iname(inum)
 174         res.append("    // PLIC rules for {0}".format(name))
 175         for idx in range(niq):
 176             plic_obj = self.plic_object(name, idx)
 177             print "plic_obj", name, idx, plic_obj
 178             plic = mkplic_rule.format(name, plic_obj, irq_offs)
 179             res.append(plic)
 180             irq_offs += 1 # increment to next irq
 181         return ('\n'.join(res), irq_offs)
 182
 183     def mk_ext_ifacedef(self, iname, inum):
 184         return ''
 185
 186
 187 mkplic_rule = """\
 188      rule rl_connect_{0}_to_plic_{2};
 189         if({1} == 1'b1) begin
 190             ff_gateway_queue[{2}].enq(1);
 191             plic.ifc_external_irq[{2}].irq_frm_gateway(True);
 192         end
 193      endrule
 194 """
 195
 196 class uart(PBase):
 197
 198     def slowimport(self):
 199         return "    import Uart_bs         :: *;\n" + \
 200                "    import RS232_modified::*;"
 201
 202     def slowifdecl(self):
 203         return "            interface RS232 uart{0}_coe;\n" + \
 204                "            method Bit#(1) uart{0}_intr;"
 205
 206     def num_axi_regs32(self):
 207         return 8
 208
 209     def mkslow_peripheral(self, size=0):
 210         return "        Ifc_Uart_bs uart{0} <- \n" + \
 211                "                mkUart_bs(clocked_by sp_clock,\n" + \
 212                "                    reset_by uart_reset, sp_clock, sp_reset);"
 213
 214     def _mk_connection(self, name=None, count=0):
 215         return "uart{0}.slave_axi_uart"
 216
 217     def pinname_out(self, pname):
 218         return {'tx': 'coe_rs232.sout'}.get(pname, '')
 219
 220     def pinname_in(self, pname):
 221         return {'rx': 'coe_rs232.sin'}.get(pname, '')
 222
 223
 224 class quart(PBase):
 225
 226     def slowimport(self):
 227         return "    import Uart16550         :: *;"
 228
 229     def slowifdecl(self):
 230         return "            interface RS232_PHY_Ifc quart{0}_coe;\n" + \
 231                "            method Bit#(1) quart{0}_intr;"
 232
 233     def num_axi_regs32(self):
 234         return 8
 235
 236     def mkslow_peripheral(self, size=0):
 237         return "        Uart16550_AXI4_Lite_Ifc quart{0} <- \n" + \
 238                "                mkUart16550(clocked_by sp_clock,\n" + \
 239                "                    reset_by uart_reset, sp_clock, sp_reset);"
 240
 241     def _mk_connection(self, name=None, count=0):
 242         return "quart{0}.slave_axi_uart"
 243
 244     def pinname_out(self, pname):
 245         return {'tx' : 'coe_rs232.modem_output_stx',
 246                 'rts': 'coe_rs232.modem_output_rts',
 247                }.get(pname, '')
 248
 249     def _pinname_in(self, pname):
 250         return {'rx': 'coe_rs232.modem_input.srx',
 251                 'cts': 'coe_rs232.modem_input.cts'
 252                }.get(pname, '')
 253
 254     def mk_pincon(self, name, count):
 255         ret = [PBase.mk_pincon(self, name, count)]
 256         ret.append("    rule con_%s%d_io_in;" % (name, count))
 257         ret.append("       {0}{1}.coe_rs232.modem_input(".format(name, count))
 258         for idx, pname in enumerate(['rx', 'cts']):
 259             sname = self.peripheral.pname(pname).format(count)
 260             ps = "pinmux.peripheral_side.%s" % sname
 261             ret.append("            {0},".format(ps))
 262         ret.append("            1'b1,1'b0,1'b1")
 263         ret.append("        );")
 264         ret.append("    endrule")
 265
 266         return '\n'.join(ret)
 267
 268     def num_irqs(self):
 269         return 1
 270
 271     def plic_object(self, pname, idx):
 272         return "{0}_interrupt.read".format(pname)
 273
 274     def mk_plic(self, inum, irq_offs):
 275         name = self.get_iname(inum)
 276         ret = [uart_plic_template.format(name, irq_offs)]
 277         (ret2, irq_offs) = PBase.mk_plic(self, inum, irq_offs)
 278         ret.append(ret2)
 279         return ('\n'.join(ret), irq_offs)
 280
 281     def mk_ext_ifacedef(self, iname, inum):
 282         name = self.get_iname(inum)
 283         return "        method {0}_intr = {0}.irq;".format(name)
 284
 285     def slowifdeclmux(self):
 286         return "        method Bit#(1) {1}{0}_intr;"
 287
 288 uart_plic_template = """\
 289      // PLIC {0} synchronisation with irq {1}
 290      SyncBitIfc#(Bit#(1)) {0}_interrupt <-
 291                                 mkSyncBitToCC(sp_clock, uart_reset);
 292      rule plic_synchronize_{0}_interrupt_{1};
 293          {0}_interrupt.send({0}.irq);
 294      endrule
 295 """
 296
 297 class rs232(PBase):
 298
 299     def slowimport(self):
 300         return "    import Uart_bs::*;\n" + \
 301                "    import RS232_modified::*;"
 302
 303     def slowifdecl(self):
 304         return "            interface RS232 uart{0}_coe;"
 305
 306     def num_axi_regs32(self):
 307         return 2
 308
 309     def mkslow_peripheral(self, size=0):
 310         return "        //Ifc_Uart_bs uart{0} <-" + \
 311                "        //       mkUart_bs(clocked_by uart_clock,\n" + \
 312                "        //          reset_by uart_reset,sp_clock, sp_reset);" +\
 313                "        Ifc_Uart_bs uart{0} <-" + \
 314                "                mkUart_bs(clocked_by sp_clock,\n" + \
 315                "                    reset_by sp_reset, sp_clock, sp_reset);"
 316
 317     def _mk_connection(self, name=None, count=0):
 318         return "uart{0}.slave_axi_uart"
 319
 320     def pinname_out(self, pname):
 321         return {'tx': 'coe_rs232.sout'}.get(pname, '')
 322
 323     def pinname_in(self, pname):
 324         return {'rx': 'coe_rs232.sin'}.get(pname, '')
 325
 326
 327 class twi(PBase):
 328
 329     def slowimport(self):
 330         return "    import I2C_top           :: *;"
 331
 332     def slowifdecl(self):
 333         return "            interface I2C_out twi{0}_out;\n" + \
 334                "            method Bit#(1) twi{0}_isint;"
 335
 336     def num_axi_regs32(self):
 337         return 8
 338
 339     def mkslow_peripheral(self, size=0):
 340         return "        I2C_IFC twi{0} <- mkI2CController();"
 341
 342     def _mk_connection(self, name=None, count=0):
 343         return "twi{0}.slave_i2c_axi"
 344
 345     def pinname_out(self, pname):
 346         return {'sda': 'out.sda_out',
 347                 'scl': 'out.scl_out'}.get(pname, '')
 348
 349     def pinname_in(self, pname):
 350         return {'sda': 'out.sda_in',
 351                 'scl': 'out.scl_in'}.get(pname, '')
 352
 353     def pinname_outen(self, pname):
 354         return {'sda': 'out.sda_out_en',
 355                 'scl': 'out.scl_out_en'}.get(pname, '')
 356
 357     def pinname_tweak(self, pname, typ, txt):
 358         if typ == 'outen':
 359             return "pack({0})".format(txt)
 360         return txt
 361
 362     def num_irqs(self):
 363         return 3
 364
 365     def plic_object(self, pname, idx):
 366         return ["{0}.isint()",
 367                 "{0}.timerint()",
 368                 "{0}.isber()"
 369                ][idx].format(pname)
 370
 371     def mk_ext_ifacedef(self, iname, inum):
 372         name = self.get_iname(inum)
 373         return "        method {0}_isint = {0}.isint;".format(name)
 374
 375     def slowifdeclmux(self):
 376         return "        method Bit#(1) {1}{0}_isint;"
 377
 378
 379 class eint(PBase):
 380
 381     def slowimport(self):
 382         size = len(self.peripheral.pinspecs)
 383         return "    `define NUM_EINTS %d" % size
 384
 385     def mkslow_peripheral(self, size=0):
 386         size = len(self.peripheral.pinspecs)
 387         return "        Wire#(Bit#(%d)) wr_interrupt <- mkWire();" % size
 388
 389     def axi_slave_name(self, name, ifacenum):
 390         return ''
 391
 392     def axi_slave_idx(self, idx, name, ifacenum):
 393         return ('', 0)
 394
 395     def axi_addr_map(self, name, ifacenum):
 396         return ''
 397
 398     def ifname_tweak(self, pname, typ, txt):
 399         if typ != 'in':
 400             return txt
 401         print "ifnameweak", pname, typ, txt
 402         return "wr_interrupt[{0}] <= ".format(pname)
 403
 404     def mk_pincon(self, name, count):
 405         ret = [PBase.mk_pincon(self, name, count)]
 406         size = len(self.peripheral.pinspecs)
 407         ret.append(eint_pincon_template.format(size))
 408         ret.append("    rule con_%s%d_io_in;" % (name, count))
 409         ret.append("    wr_interrupt <= ({")
 410         for idx, p in enumerate(self.peripheral.pinspecs):
 411             pname = p['name']
 412             sname = self.peripheral.pname(pname).format(count)
 413             ps = "pinmux.peripheral_side.%s" % sname
 414             comma = '' if idx == size - 1 else ','
 415             ret.append("             {0}{1}".format(ps, comma))
 416         ret.append("        });")
 417         ret.append("    endrule")
 418
 419         return '\n'.join(ret)
 420
 421
 422 eint_pincon_template = '''\
 423     // EINT is offset at end of other peripheral interrupts
 424 `ifdef PLIC
 425     for(Integer i=0;i<{0};i=i+ 1)begin
 426       rule connect_int_to_plic(wr_interrupt[i]==1);
 427                 ff_gateway_queue[i+`NUM_SLOW_IRQS].enq(1);
 428                 plic.ifc_external_irq[i+`NUM_SLOW_IRQS].irq_frm_gateway(True);
 429       endrule
 430     end
 431 `endif
 432 '''
 433
 434
 435 class jtag(PBase):
 436
 437     def axi_slave_name(self, name, ifacenum):
 438         return ''
 439
 440     def axi_slave_idx(self, idx, name, ifacenum):
 441         return ('', 0)
 442
 443     def axi_addr_map(self, name, ifacenum):
 444         return ''
 445
 446     def slowifdeclmux(self):
 447         return "        method  Action jtag_ms (Bit#(1) in);\n" +  \
 448                "        method  Bit#(1) jtag_di;\n" + \
 449                "        method  Action jtag_do (Bit#(1) in);\n" + \
 450                "        method  Action jtag_ck (Bit#(1) in);"
 451
 452     def slowifinstance(self):
 453         return jtag_method_template # bit of a lazy hack this...
 454
 455 jtag_method_template = """\
 456         method  Action jtag_ms (Bit#(1) in);
 457           pinmux.peripheral_side.jtag_ms(in);
 458         endmethod
 459         method  Bit#(1) jtag_di=pinmux.peripheral_side.jtag_di;
 460         method  Action jtag_do (Bit#(1) in);
 461           pinmux.peripheral_side.jtag_do(in);
 462         endmethod
 463         method  Action jtag_ck (Bit#(1) in);
 464           pinmux.peripheral_side.jtag_ck(in);
 465         endmethod
 466 """
 467
 468 class sdmmc(PBase):
 469
 470     def slowimport(self):
 471         return "    import sdcard_dummy              :: *;"
 472
 473     def slowifdecl(self):
 474         return "            interface QSPI_out sd{0}_out;\n" + \
 475                "            method Bit#(1) sd{0}_isint;"
 476
 477     def num_axi_regs32(self):
 478         return 13
 479
 480     def mkslow_peripheral(self):
 481         return "        Ifc_sdcard_dummy sd{0} <-  mksdcard_dummy();"
 482
 483     def _mk_connection(self, name=None, count=0):
 484         return "sd{0}.slave"
 485
 486     def pinname_in(self, pname):
 487         return "%s_in" % pname
 488
 489     def pinname_out(self, pname):
 490         if pname.startswith('d'):
 491             return "%s_out" % pname
 492         return pname
 493
 494     def pinname_outen(self, pname):
 495         if pname.startswith('d'):
 496             return "%s_outen" % pname
 497
 498
 499 class spi(PBase):
 500
 501     def slowimport(self):
 502         return "    import qspi              :: *;"
 503
 504     def slowifdecl(self):
 505         return "            interface QSPI_out spi{0}_out;\n" + \
 506                "            method Bit#(1) spi{0}_isint;"
 507
 508     def num_axi_regs32(self):
 509         return 13
 510
 511     def mkslow_peripheral(self):
 512         return "        Ifc_qspi spi{0} <-  mkqspi();"
 513
 514     def _mk_connection(self, name=None, count=0):
 515         return "spi{0}.slave"
 516
 517     def pinname_out(self, pname):
 518         return {'clk': 'out.clk_o',
 519                 'nss': 'out.ncs_o',
 520                 'mosi': 'out.io_o[0]',
 521                 'miso': 'out.io_o[1]',
 522                 }.get(pname, '')
 523
 524     def pinname_outen(self, pname):
 525         return {'clk': 1,
 526                 'nss': 1,
 527                 'mosi': 'out.io_enable[0]',
 528                 'miso': 'out.io_enable[1]',
 529                 }.get(pname, '')
 530
 531     def mk_pincon(self, name, count):
 532         ret = [PBase.mk_pincon(self, name, count)]
 533         # special-case for gpio in, store in a temporary vector
 534         plen = len(self.peripheral.pinspecs)
 535         ret.append("    // XXX NSS and CLK are hard-coded master")
 536         ret.append("    // TODO: must add spi slave-mode")
 537         ret.append("    // all ins done in one rule from 4-bitfield")
 538         ret.append("    rule con_%s%d_io_in;" % (name, count))
 539         ret.append("       {0}{1}.out.io_i({{".format(name, count))
 540         for idx, pname in enumerate(['mosi', 'miso']):
 541             sname = self.peripheral.pname(pname).format(count)
 542             ps = "pinmux.peripheral_side.%s_in" % sname
 543             ret.append("            {0},".format(ps))
 544         ret.append("            1'b0,1'b0")
 545         ret.append("        });")
 546         ret.append("    endrule")
 547         return '\n'.join(ret)
 548
 549     def mk_ext_ifacedef(self, iname, inum):
 550         name = self.get_iname(inum)
 551         return "        method {0}_isint = {0}.interrupts[5];".format(name)
 552
 553     def slowifdeclmux(self):
 554         return "        method Bit#(1) {1}{0}_isint;"
 555
 556
 557 class qspi(PBase):
 558
 559     def slowimport(self):
 560         return "    import qspi              :: *;"
 561
 562     def slowifdecl(self):
 563         return "            interface QSPI_out qspi{0}_out;\n" + \
 564                "            method Bit#(1) qspi{0}_isint;"
 565
 566     def num_axi_regs32(self):
 567         return 13
 568
 569     def mkslow_peripheral(self, size=0):
 570         return "        Ifc_qspi qspi{0} <-  mkqspi();"
 571
 572     def _mk_connection(self, name=None, count=0):
 573         return "qspi{0}.slave"
 574
 575     def pinname_out(self, pname):
 576         return {'ck': 'out.clk_o',
 577                 'nss': 'out.ncs_o',
 578                 'io0': 'out.io_o[0]',
 579                 'io1': 'out.io_o[1]',
 580                 'io2': 'out.io_o[2]',
 581                 'io3': 'out.io_o[3]',
 582                 }.get(pname, '')
 583
 584     def pinname_outen(self, pname):
 585         return {'ck': 1,
 586                 'nss': 1,
 587                 'io0': 'out.io_enable[0]',
 588                 'io1': 'out.io_enable[1]',
 589                 'io2': 'out.io_enable[2]',
 590                 'io3': 'out.io_enable[3]',
 591                 }.get(pname, '')
 592
 593     def mk_pincon(self, name, count):
 594         ret = [PBase.mk_pincon(self, name, count)]
 595         # special-case for gpio in, store in a temporary vector
 596         plen = len(self.peripheral.pinspecs)
 597         ret.append("    // XXX NSS and CLK are hard-coded master")
 598         ret.append("    // TODO: must add qspi slave-mode")
 599         ret.append("    // all ins done in one rule from 4-bitfield")
 600         ret.append("    rule con_%s%d_io_in;" % (name, count))
 601         ret.append("       {0}{1}.out.io_i({{".format(name, count))
 602         for i, p in enumerate(self.peripheral.pinspecs):
 603             typ = p['type']
 604             pname = p['name']
 605             if not pname.startswith('io'):
 606                 continue
 607             idx = pname[1:]
 608             n = name
 609             sname = self.peripheral.pname(pname).format(count)
 610             ps = "pinmux.peripheral_side.%s_in" % sname
 611             comma = '' if i == 5 else ','
 612             ret.append("            {0}{1}".format(ps, comma))
 613         ret.append("        });")
 614         ret.append("    endrule")
 615         return '\n'.join(ret)
 616
 617     def num_irqs(self):
 618         return 6
 619
 620     def plic_object(self, pname, idx):
 621         return "{0}.interrupts()[{1}]".format(pname, idx)
 622
 623     def mk_ext_ifacedef(self, iname, inum):
 624         name = self.get_iname(inum)
 625         return "        method {0}_isint = {0}.interrupts[5];".format(name)
 626
 627     def slowifdeclmux(self):
 628         return "        method Bit#(1) {1}{0}_isint;"
 629
 630
 631
 632 class pwm(PBase):
 633
 634     def slowimport(self):
 635         return "    import pwm::*;"
 636
 637     def slowifdecl(self):
 638         return "        interface PWMIO pwm{0}_io;"
 639
 640     def num_axi_regs32(self):
 641         return 4
 642
 643     def mkslow_peripheral(self, size=0):
 644         return "        Ifc_PWM_bus pwm{0} <- mkPWM_bus(sp_clock);"
 645
 646     def _mk_connection(self, name=None, count=0):
 647         return "pwm{0}.axi4_slave"
 648
 649     def pinname_out(self, pname):
 650         return {'out': 'pwm_io.pwm_o'}.get(pname, '')
 651
 652
 653 class gpio(PBase):
 654
 655     def slowimport(self):
 656         return "    import pinmux::*;\n" + \
 657                "    import mux::*;\n" + \
 658                "    import gpio::*;\n"
 659
 660     def slowifdeclmux(self):
 661         size = len(self.peripheral.pinspecs)
 662         return "        interface GPIO_config#(%d) pad_config{0};" % size
 663
 664     def num_axi_regs32(self):
 665         return 2
 666
 667     def axi_slave_idx(self, idx, name, ifacenum):
 668         """ generates AXI slave number definition, except
 669             GPIO also has a muxer per bank
 670         """
 671         name = name.upper()
 672         mname = 'mux' + name[4:]
 673         mname = mname.upper()
 674         print "AXIslavenum", name, mname
 675         (ret, x) = PBase.axi_slave_idx(self, idx, name, ifacenum)
 676         (ret2, x) = PBase.axi_slave_idx(self, idx + 1, mname, ifacenum)
 677         return ("%s\n%s" % (ret, ret2), 2)
 678
 679     def mkslow_peripheral(self, size=0):
 680         print "gpioslow", self.peripheral, dir(self.peripheral)
 681         size = len(self.peripheral.pinspecs)
 682         return "        MUX#(%d) mux{0} <- mkmux();\n" % size + \
 683                "        GPIO#(%d) gpio{0} <- mkgpio();" % size
 684
 685     def mk_connection(self, count):
 686         print "GPIO mk_conn", self.name, count
 687         res = []
 688         dname = self.mksuffix(self.name, count)
 689         for i, n in enumerate(['gpio' + dname, 'mux' + dname]):
 690             res.append(PBase.mk_connection(self, count, n))
 691         return '\n'.join(res)
 692
 693     def _mk_connection(self, name=None, count=0):
 694         n = self.mksuffix(name, count)
 695         if name.startswith('gpio'):
 696             return "gpio{0}.axi_slave".format(n)
 697         if name.startswith('mux'):
 698             return "mux{0}.axi_slave".format(n)
 699
 700     def mksuffix(self, name, i):
 701         if name.startswith('mux'):
 702             return name[3:]
 703         return name[4:]
 704
 705     def mk_cellconn(self, cellnum, name, count):
 706         ret = []
 707         bank = self.mksuffix(name, count)
 708         txt = "       pinmux.mux_lines.cell{0}_mux(mux{1}.mux_config.mux[{2}]);"
 709         for p in self.peripheral.pinspecs:
 710             ret.append(txt.format(cellnum, bank, p['name'][1:]))
 711             cellnum += 1
 712         return ("\n".join(ret), cellnum)
 713
 714     def pinname_out(self, pname):
 715         return "func.gpio_out[{0}]".format(pname[1:])
 716
 717     def pinname_outen(self, pname):
 718         return "func.gpio_out_en[{0}]".format(pname[1:])
 719
 720     def mk_pincon(self, name, count):
 721         ret = [PBase.mk_pincon(self, name, count)]
 722         # special-case for gpio in, store in a temporary vector
 723         plen = len(self.peripheral.pinspecs)
 724         ret.append("    rule con_%s%d_in;" % (name, count))
 725         ret.append("       Vector#({0},Bit#(1)) temp;".format(plen))
 726         for p in self.peripheral.pinspecs:
 727             typ = p['type']
 728             pname = p['name']
 729             idx = pname[1:]
 730             n = name
 731             sname = self.peripheral.pname(pname).format(count)
 732             ps = "pinmux.peripheral_side.%s_in" % sname
 733             ret.append("        temp[{0}]={1};".format(idx, ps))
 734         ret.append("        {0}.func.gpio_in(temp);".format(name))
 735         ret.append("    endrule")
 736         return '\n'.join(ret)
 737
 738
 739 axi_slave_declarations = """\
 740 typedef  0  SlowMaster;
 741 {0}
 742 typedef  TAdd#(LastGen_slave_num,`ifdef CLINT       1 `else 0 `endif )
 743               CLINT_slave_num;
 744 typedef  TAdd#(CLINT_slave_num  ,`ifdef PLIC        1 `else 0 `endif )
 745               Plic_slave_num;
 746 typedef  TAdd#(Plic_slave_num   ,`ifdef AXIEXP      1 `else 0 `endif )
 747               AxiExp1_slave_num;
 748 typedef TAdd#(AxiExp1_slave_num,1) Num_Slow_Slaves;
 749 """
 750
 751 pinmux_cellrule = """\
 752     rule connect_select_lines_pinmux;
 753 {0}
 754     endrule
 755 """
 756
 757
 758 class CallFn(object):
 759     def __init__(self, peripheral, name):
 760         self.peripheral = peripheral
 761         self.name = name
 762
 763     def __call__(self, *args):
 764         #print "__call__", self.name, self.peripheral.slow, args
 765         if not self.peripheral.slow:
 766             return ''
 767         return getattr(self.peripheral.slow, self.name)(*args[1:])
 768
 769
 770 class PeripheralIface(object):
 771     def __init__(self, ifacename):
 772         self.slow = None
 773         slow = slowfactory.getcls(ifacename)
 774         print "Iface", ifacename, slow
 775         if slow:
 776             self.slow = slow(ifacename)
 777             self.slow.peripheral = self
 778         for fname in ['slowimport',
 779                       'slowifinstance', 'slowifdecl', 'slowifdeclmux',
 780                       'mkslow_peripheral', 'mk_plic', 'mk_ext_ifacedef',
 781                       'mk_connection', 'mk_cellconn', 'mk_pincon']:
 782             fn = CallFn(self, fname)
 783             setattr(self, fname, types.MethodType(fn, self))
 784
 785         #print "PeripheralIface"
 786         #print dir(self)
 787
 788     def mksuffix(self, name, i):
 789         if self.slow is None:
 790             return i
 791         return self.slow.mksuffix(name, i)
 792
 793     def axi_reg_def(self, start, count):
 794         if not self.slow:
 795             return ('', 0)
 796         return self.slow.axi_reg_def(start, self.ifacename, count)
 797
 798     def axi_slave_idx(self, start, count):
 799         if not self.slow:
 800             return ('', 0)
 801         return self.slow.axi_slave_idx(start, self.ifacename, count)
 802
 803     def axi_addr_map(self, count):
 804         if not self.slow:
 805             return ''
 806         return self.slow.axi_addr_map(self.ifacename, count)
 807
 808
 809 class PeripheralInterfaces(object):
 810     def __init__(self):
 811         pass
 812
 813     def slowimport(self, *args):
 814         ret = []
 815         for (name, count) in self.ifacecount:
 816             #print "slowimport", name, self.data[name].slowimport
 817             ret.append(self.data[name].slowimport())
 818         return '\n'.join(list(filter(None, ret)))
 819
 820     def slowifinstance(self, *args):
 821         ret = []
 822         for (name, count) in self.ifacecount:
 823             #print "slowimport", name, self.data[name].slowimport
 824             ret.append(self.data[name].slowifinstance())
 825         return '\n'.join(list(filter(None, ret)))
 826
 827     def slowifdeclmux(self, *args):
 828         ret = []
 829         for (name, count) in self.ifacecount:
 830             for i in range(count):
 831                 ret.append(self.data[name].slowifdeclmux().format(i, name))
 832         return '\n'.join(list(filter(None, ret)))
 833
 834     def slowifdecl(self, *args):
 835         ret = []
 836         for (name, count) in self.ifacecount:
 837             for i in range(count):
 838                 ret.append(self.data[name].slowifdecl().format(i, name))
 839         return '\n'.join(list(filter(None, ret)))
 840
 841     def axi_reg_def(self, *args):
 842         ret = []
 843         start = 0x00011100  # start of AXI peripherals address
 844         for (name, count) in self.ifacecount:
 845             for i in range(count):
 846                 x = self.data[name].axi_reg_def(start, i)
 847                 #print ("ifc", name, x)
 848                 (rdef, offs) = x
 849                 ret.append(rdef)
 850                 start += offs
 851         return '\n'.join(list(filter(None, ret)))
 852
 853     def axi_slave_idx(self, *args):
 854         ret = []
 855         start = 0
 856         for (name, count) in self.ifacecount:
 857             for i in range(count):
 858                 (rdef, offs) = self.data[name].axi_slave_idx(start, i)
 859                 #print ("ifc", name, rdef, offs)
 860                 ret.append(rdef)
 861                 start += offs
 862         ret.append("typedef %d LastGen_slave_num;" % (start - 1))
 863         decls = '\n'.join(list(filter(None, ret)))
 864         return axi_slave_declarations.format(decls)
 865
 866     def axi_addr_map(self, *args):
 867         ret = []
 868         for (name, count) in self.ifacecount:
 869             for i in range(count):
 870                 ret.append(self.data[name].axi_addr_map(i))
 871         return '\n'.join(list(filter(None, ret)))
 872
 873     def mkslow_peripheral(self, *args):
 874         ret = []
 875         for (name, count) in self.ifacecount:
 876             for i in range(count):
 877                 print "mkslow", name, count
 878                 x = self.data[name].mkslow_peripheral()
 879                 print name, count, x
 880                 suffix = self.data[name].mksuffix(name, i)
 881                 ret.append(x.format(suffix))
 882         return '\n'.join(list(filter(None, ret)))
 883
 884     def mk_connection(self, *args):
 885         ret = []
 886         for (name, count) in self.ifacecount:
 887             for i in range(count):
 888                 print "mk_conn", name, i
 889                 txt = self.data[name].mk_connection(i)
 890                 if name == 'gpioa':
 891                     print "txt", txt
 892                     print self.data[name].mk_connection
 893                 ret.append(txt)
 894         return '\n'.join(list(filter(None, ret)))
 895
 896     def mk_cellconn(self):
 897         ret = []
 898         cellcount = 0
 899         for (name, count) in self.ifacecount:
 900             for i in range(count):
 901                 res = self.data[name].mk_cellconn(cellcount, name, i)
 902                 if not res:
 903                     continue
 904                 (txt, cellcount) = res
 905                 ret.append(txt)
 906         ret = '\n'.join(list(filter(None, ret)))
 907         return pinmux_cellrule.format(ret)
 908
 909     def mk_pincon(self):
 910         ret = []
 911         for (name, count) in self.ifacecount:
 912             for i in range(count):
 913                 txt = self.data[name].mk_pincon(name, i)
 914                 ret.append(txt)
 915         return '\n'.join(list(filter(None, ret)))
 916
 917     def mk_ext_ifacedef(self):
 918         ret = []
 919         for (name, count) in self.ifacecount:
 920             for i in range(count):
 921                 txt = self.data[name].mk_ext_ifacedef(name, i)
 922                 ret.append(txt)
 923         return '\n'.join(list(filter(None, ret)))
 924
 925
 926     def mk_plic(self):
 927         ret = []
 928         irq_offs = 8 # XXX: DMA scovers 0-7?
 929         for (name, count) in self.ifacecount:
 930             for i in range(count):
 931                 res = self.data[name].mk_plic(i, irq_offs)
 932                 if not res:
 933                     continue
 934                 (txt, irq_offs) = res
 935                 ret.append(txt)
 936         self.num_slow_irqs = irq_offs
 937         return '\n'.join(list(filter(None, ret)))
 938
 939     def mk_sloirqsdef(self):
 940         return "    `define NUM_SLOW_IRQS {0}".format(self.num_slow_irqs)
 941
 942
 943 class PFactory(object):
 944     def getcls(self, name):
 945         for k, v in {'uart': uart,
 946                      'rs232': rs232,
 947                      'twi': twi,
 948                      'quart': quart,
 949                      'qspi': qspi,
 950                      'spi': spi,
 951                      'pwm': pwm,
 952                      'eint': eint,
 953                      'sd': sdmmc,
 954                      'jtag': jtag,
 955                      'gpio': gpio
 956                      }.items():
 957             if name.startswith(k):
 958                 return v
 959         return None
 960
 961
 962 slowfactory = PFactory()
 963
 964 if __name__ == '__main__':
 965     p = uart('uart')
 966     print p.slowimport()
 967     print p.slowifdecl()
 968     i = PeripheralIface('uart')
 969     print i, i.slow
 970     i = PeripheralIface('gpioa')
 971     print i, i.slow